Single-control double-stage boost PFC circuit and surge suppression circuit

Abstract

The application comprises a single-control double-stage boost PFC circuit and a surge suppression circuit. The PFC circuit uses a control chip to control two-stage boost circuit, and only needs a power inductor. The first stage is a sub-PFC, and the second stage is a main PFC, and the power input of the second stage circuit is derived from the coupling inductor of the first stage boost inductor. The sub-PFC uses a Cz capacitor network to replace the traditional single-capacitor filter, and provides more flexible output voltage for the second stage. The control part also adjusts the working frequency and duty cycle of the power circuit to realize the optimization of the working efficiency of the PFC circuit, and realizes the dynamic optimization of the overall efficiency of the PFC circuit and the second stage circuit of the PFC. In addition, the surge suppression resistor is moved from the traditional series in the main power loop to the lower end of the energy storage capacitor, and is connected in series with the energy storage capacitor, and a transistor delay short circuit is used, so that the power consumption is greatly reduced, and a relay is no longer needed.

Description

Technical Field

[0001] This invention relates to a single-controlled dual-stage boost PFC circuit and a surge suppression circuit based on a novel wide-bandgap semiconductor device. Background Technology

[0002] With the development of power electronics technology, the issue of power quality has become a major concern. In power supply circuits, the presence of high-capacitance energy storage capacitors leads to a smaller rectifier bridge conduction angle, resulting in high current ripple and large current peaks on the AC input side, introducing abundant harmonic interference, which seriously affects power quality. Therefore, power factor correction (PFC) circuits are widely used to correct the waveform of AC input current, making it a more perfect sine wave, similar to the AC input voltage. Common input-side solutions include... Figure 1 As shown, the PFC solution is as follows: Figure 3 The diagram shows a single-stage boost converter structure. However, using a single-stage boost topology results in a large output filter capacitor and an output voltage of approximately 380V. Generally, the lower the output voltage of this stage, the higher its efficiency. However, the opposite is true for subsequent stages; higher PFC output voltages lead to higher efficiency. A single-stage boost PFC solution struggles to achieve optimal design between the PFC circuit and the subsequent PFC stage, requiring a compromise PFC output voltage value. Therefore, a two-stage boost PFC solution, comprising a main PFC circuit and a sub-PFC circuit, has been proposed, such as... Figure 2 and Figure 4 As shown, the first stage is the main PFC, and the second stage is the sub-PFC. The output filter capacitor of the main PFC circuit has a small capacitance, while the output filter capacitor of the sub-PFC circuit has a large capacitance. Initially, the two-stage structure was conceived solely to reduce the size of the energy storage capacitor, as the first stage could extend the input voltage range of the second stage. However, the two-stage boost circuit requires two independent control chips, which significantly increases the complexity and cost of the circuit.

[0003] On the other hand, traditional surge suppression circuits are connected in series between the bridge rectifier and the energy storage capacitor, using a surge suppression limiting resistor RT in parallel with a relay. The circuit is placed at positions A, B, or C. This circuit is simple, easy to drive, low in cost, and not complex to control. However, the relay is large, and its resistance after conduction is over 50mΩ, resulting in relatively high operating losses, which is not conducive to the design of high-power, high-density, and high-efficiency power supplies. RT commonly uses a thermistor to suppress the inrush current generated at the moment of power-on. After the power supply is operating normally, the relay delays and short-circuits the current-limiting current to reduce power consumption. Figure 5As shown. However, since the relay's on-resistance of approximately 100 milliohms is still quite high, and the surge suppression circuit is connected in series in the main power circuit, its conduction current is very large. The losses generated by the relay are still not negligible. Moreover, the relay is also quite large, which is not conducive to the design requirements of high power density power supplies. The relay also requires additional drive and third-party power supply, making the circuit complex and costly. Therefore, how to simplify the circuit while achieving the original function becomes the primary consideration. Summary of the Invention

[0004] The purpose of this invention is to provide a single-control, two-stage boost PFC circuit.

[0005] The objective of this invention is achieved through the following technical solution:

[0006] A single-control dual-stage boost PFC circuit is characterized by comprising: a sub-PFC circuit and a main PFC circuit, wherein the AC input signal is rectified by a rectifier circuit and then input to the sub-PFC circuit;

[0007] The sub-PFC circuit includes a boost circuit, a Cz capacitor network, and a capacitor C4. Two to eight capacitors are connected in series and grounded, and then connected in parallel with C4 to form the Cz capacitor network. The boost circuit is inductively coupled to the main PFC circuit, and the boost circuit is controlled by a control chip.

[0008] The main PFC circuit includes an inductor LPFC:B, two diodes DPFC2 and DPFC3, and a capacitor C5. One end of the inductor LPFC:B is connected to the anode of DPFC2, and the other end is connected to any series capacitor in the Cz capacitor network. The cathode of DPFC2 is connected to the upper end of capacitor C5. The anode of DPFC3 is connected to the boost circuit, and the cathode is also connected to the upper end of capacitor C5. The upper end of C4 is connected between the boost circuit and the anode of DPFC3, and the lower end is connected to the lower end of C5 and grounded.

[0009] It also includes an output voltage monitoring module and an output power monitoring module to monitor the signals output from the cathodes of DPFC2 and DPFC3, and input the monitoring signals to the control chip;

[0010] It also includes an input power monitoring module, which monitors the AC input signal and inputs the monitoring signal to the control chip.

[0011] Preferably, the boost circuit includes an inductor LPFC:A, a diode DPFC1, a switching transistor QPFC, and a driving circuit for the switching transistor QPFC. The inductor LPFC:A is coupled to an inductor LPFC:B. One end of the inductor LPFC:A is connected to the AC input signal rectified by the rectifier circuit, and the other end is connected to the anode of the diode DPFC1. The cathode of the diode DPFC1 is connected to the anode of the DPFC2. The positive terminal of the switching transistor QPFC is connected to the AC input signal rectified by the rectifier circuit and grounded, and the negative terminal is connected to the anode of the diode DPFC1. The control chip controls the driving of QPFC through the driving circuit.

[0012] Preferably, C4 is a high-voltage electrolytic capacitor.

[0013] Preferably, the field-effect transistor is a third-generation wide-bandgap semiconductor power MOSFET or HEMT.

[0014] Preferably, it also includes a second output power monitoring module to monitor the output power of the subsequent stage circuit and input the monitoring signal into the control chip.

[0015] The present invention also discloses a surge suppression circuit, which is used in conjunction with the above-mentioned single-controlled dual-stage boost PFC circuit. It includes a switching transistor Qr, a control and drive circuit for the switching transistor Qr, a diode Din, and a surge suppression resistor RT. The negative terminal of Qr is connected to the lower end of C5, the positive terminal of Qr is connected to the positive terminal of QPFC and grounded, the control and drive circuit is connected to Qr to realize the control and drive of Qr, the RT is connected in parallel between the positive and negative terminals of Qr, the output terminal of the rectifier circuit is connected to the anode of Din, and the cathode of Din is connected to the upper end of C5.

[0016] This invention relates to the circuit application of a novel wide-bandgap semiconductor device, comprising a two-stage boost power factor correction (PFC) circuit and a surge suppression circuit. The PFC circuit uses a single control chip to control two boost circuits and requires only one power inductor. The first stage is a sub-PFC, and the second stage is the main PFC. The power input of the second stage circuit comes from the coupling inductor of the first stage boost inductor. The sub-PFC uses a Cz capacitor network instead of the traditional single-capacitor filter, providing a more flexible output voltage for the second stage. The control section also optimizes the PFC circuit's efficiency by adjusting the operating frequency and duty cycle of the power circuit, achieving dynamic optimization of the overall efficiency of the PFC circuit and the subsequent stage. Furthermore, the surge suppression resistor, traditionally connected in series in the main power circuit, is moved to the lower end of the energy storage capacitor, connected in series with it. A transistor delay short circuit is used, significantly reducing power consumption and eliminating the need for a relay. This solution features a simple circuit, easy control, and low cost.

[0017] The beneficial effects of this invention are as follows:

[0018] 1. A dual boost topology circuit structure with master and sub-boost, but different from the traditional scheme. In this structure, the first stage is a sub-PFC and the second stage is a master PFC (in the traditional scheme, the first stage is a master PFC and the second stage is a sub-PFC). The main control is in the second stage.

[0019] 2. The sub-PFC uses a Cz capacitor network to replace the traditional single capacitor filter, providing a more flexible output voltage for the next stage.

[0020] 3. This circuit only requires one coupling inductor and one control chip, making control simple.

[0021] 4. Efficiency optimization intelligent control is added. By adjusting the operating frequency and duty cycle of the power circuit, the working efficiency of the PFC circuit is optimized, and the overall efficiency of the PFC circuit and the PFC downstream circuit is dynamically optimized.

[0022] 5. The surge suppression resistor has been moved from being connected in series in the main power circuit to the lower end of the energy storage capacitor and connected in series with the energy storage capacitor. At the same time, a transistor delay short circuit is used, which greatly reduces its power consumption and eliminates the need for a relay. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of a single PFC solution on the power input side.

[0024] Figure 2 This is a schematic diagram of a dual PFC solution on the power input side.

[0025] Figure 3 This is a traditional single-stage boost PFC solution.

[0026] Figure 4 This is a traditional two-stage boost PFC solution.

[0027] Figure 5 This is a traditional surge suppression solution.

[0028] Figure 6 This is a schematic diagram of the single-control, two-stage boost PFC circuit of the present invention.

[0029] Figure 7 This is an embodiment of the single-control, two-stage boost PFC circuit of the present invention.

[0030] Figure 8 This is an embodiment of the surge suppression method of the present invention. Detailed Implementation

[0031] Example 1

[0032] This single-control dual-stage boost PFC circuit includes: a sub-PFC circuit and a main PFC circuit. The AC input signal is rectified by the rectifier circuit and then input to the sub-PFC circuit.

[0033] The sub-PFC circuit includes a boost circuit, a Cz capacitor network, and a capacitor C4. The Cz capacitor network consists of three capacitors C1, C2, and C3 connected in series and grounded. The Cz capacitor network is connected in parallel with C4. The boost circuit is inductively coupled to the main PFC circuit. The boost circuit is controlled by a control chip.

[0034] The main PFC circuit includes an inductor LPFC:B, two diodes DPFC2 and DPFC3, and a capacitor C5. One end of the inductor LPFC:B is connected to the anode of DPFC2, and the other end is connected to the upper end of any series capacitor C1, C2, or C3 in the Cz capacitor network. The cathode of DPFC2 is connected to the upper end of capacitor C5. The anode of DPFC3 is connected to the boost circuit, and the cathode is also connected to the upper end of capacitor C5. The upper end of C4 is connected between the boost circuit and the anode of DPFC3, and the lower end is connected to the lower end of C5 and grounded.

[0035] It also includes an output voltage monitoring module and an output power monitoring module to monitor the signals output from the cathodes of DPFC2 and DPFC3, and input the monitoring signals to the control chip;

[0036] It also includes an input power monitoring module, which monitors the AC input signal and inputs the monitoring signal to the control chip.

[0037] The boost circuit includes an inductor LPFC:A, a diode DPFC1, a switching transistor QPFC, and a driving circuit for the switching transistor QPFC. The inductor LPFC:A is coupled to an inductor LPFC:B. One end of the inductor LPFC:A is connected to the AC input signal rectified by the rectifier circuit, and the other end is connected to the anode of the diode DPFC1. The cathode of the diode DPFC1 is connected to the anode of the DPFC2. The positive terminal of the switching transistor QPFC is connected to the AC input signal rectified by the rectifier circuit and grounded, and the negative terminal is connected to the anode of the diode DPFC1. The control chip controls the driving of QPFC through the driving circuit.

[0038] C4 is a high-voltage electrolytic capacitor.

[0039] The field-effect transistor is a third-generation wide-bandgap semiconductor power MOSFET or HEMT.

[0040] It also includes a second output power monitoring module, which monitors the output power of the next stage circuit and inputs the monitoring signal into the control chip.

[0041] Explanation of working principle and process:

[0042] C1 - C3 are connected in series (the series connection of C1 - C3 can be 2 - 8 capacitors in series, not limited to 3 in series, and all are high - voltage ceramic capacitors), and then connected in parallel with C4. C4 is a high - voltage electrolytic capacitor with a relatively large capacitance value. These series - parallel capacitors together constitute the Cz capacitor network system.

[0043] Q PFC When it is turned on, L PFC:A stores energy, and the coupling coil L PFC:B also stores energy. At this time, D PFC1 and D PFC2 are both reverse - cut - off. The Cz capacitor network and C5 jointly supply power to the output load, but mainly C5 supplies power to the output load because when the AC input normally provides energy, the voltage on C5 is higher than the voltage on the Cz capacitor network, making D PFC3 reverse - cut - off. Only when the AC input is removed or the voltage of C5 is abnormal, the voltage of C5 drops until the voltage on C5 is lower than the voltage on the Cz capacitor network. At this time, D PFC3 conducts, and the Cz capacitor network and C5 will jointly supply power to the output load.

[0044] Q PFC When it is turned off, L PFC:A stores energy and generates a reverse electromotive force, making D PFC1 conduct. The energy of the inductor L PFC:A charges the Cz capacitor network, realizing the first - stage boost function (sub - PFC). One end of the L PFC：B coil is connected to point a, b, c or d of the series capacitor network, depending on the required output voltage level on C5. When connected to point a, the voltage on C5 is the highest, and it decreases in turn. When connected to point d, the voltage on C5 is the lowest. L PFC:B stores energy and generates a reverse electromotive force, making D PFC2 conduct. The energy of the inductor L PFC:B charges C5, realizing the second - stage boost function (main PFC).

[0045] The voltage of the first - stage sub - PFC Va = Vin / (1 - D), 0 < D < 1. Therefore, the boost function is realized. At this time, the effective energy of the inductor L PFC:A is 0.5·L PFC:A ·i1 2 . When operating in a steady state, a small part of the energy of the inductor L PFC:A charges the Cz capacitor network when Q PFC is turned off, and most of the energy is transferred to the secondary - side coil L PFC when Q PFC:B is turned off, that is, 0.5·L PFC:B ·i2 2 . At this time, the voltage difference between the two ends is (Va - Vin). Assuming L PFC:A and LPFC:B If the turns ratio is 1:2, then Vo = Vc + 2(Va - Vin) = Vc + 2(Vin / (1-D) - Vin) = Vc + 2Vin·D / (1-D). Therefore, the difference between Vo and Va is Vo - Va = Vc + Vin / (1-D)·(2D-1).

[0046] The control chip simultaneously monitors both output power and input power, calculates operating efficiency, and adjusts the operating frequency of the PFC power circuit to optimize efficiency. When output efficiency is low, the operating frequency is reduced to improve efficiency. This adjustment optimizes the efficiency of the PFC stage power circuit.

[0047] The control chip also monitors the output power 1 and the output power 2 of the next stage circuit, calculates the working efficiency of the next stage circuit, and adjusts the working duty cycle of the PFC power circuit through the control chip to achieve a dynamic optimization of the efficiency of the PFC circuit and the efficiency of the PFC next stage circuit, that is, an optimal compromise value.

[0048] Example 2

[0049] This surge suppression circuit, used in conjunction with the aforementioned single-controlled dual-stage boost PFC circuit, includes a switching transistor Qr, a control and control circuit for the switching transistor Qr, a diode Din, and a surge suppression resistor RT. The negative terminal of Qr is connected to the lower end of C5, the positive terminal of Qr is connected to the positive terminal of QPFC and grounded, and the control and control circuit is connected to Qr to control and drive Qr. RT is connected in parallel between the positive and negative terminals of Qr.

[0050] Explanation of working principle and process:

[0051] This design places the surge suppression resistor RT at the lower end of C5, with the other end grounded. At power-on, because RT is connected in series with C5, it suppresses current. Once C5 is fully charged and the surge current returns to normal, Qr is turned on by the control and drive circuit, short-circuiting RT. Current then flows through Qr, eliminating power consumption on RT. Furthermore, Qr has very low on-resistance and therefore very low power consumption. Simultaneously, since neither Qr nor RT is in the main power circuit, the current flowing through them is only 3%-20% of that in the main power circuit, further reducing power consumption.

[0052] The above embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the above embodiments. Any changes, modifications, substitutions, combinations, or simplifications made without departing from the spirit and principle of the present invention shall be considered equivalent substitutions and shall be included within the protection scope of the present invention.

Claims

1. A single-control two-stage boost PFC circuit, characterized by include: The sub-PFC circuit and the main PFC circuit are used. The AC input signal is rectified by the rectifier circuit and then input into the sub-PFC circuit. The sub-PFC circuit includes a boost circuit and a Cz capacitor network. 2-8 capacitors are connected in series and grounded, and then connected in parallel with capacitor C4 to form the Cz capacitor network. The boost circuit is inductively coupled to the main PFC circuit and is controlled by a control chip. The main PFC circuit includes an inductor LPFC:B, two diodes DPFC2 and DPFC3, and a capacitor C5. One end of the inductor LPFC:B is connected to the anode of DPFC2, and the other end is connected to any series capacitor in the Cz capacitor network. The cathode of DPFC2 is connected to the upper end of capacitor C5. The anode of DPFC3 is connected to the boost circuit, and the cathode is also connected to the upper end of capacitor C5. The upper end of C4 is connected between the boost circuit and the anode of DPFC3, and the lower end is connected to the lower end of C5 and outputs voltage to the next stage circuit. It also includes an output voltage monitoring module and an output power monitoring module to monitor the signals output from the cathodes of DPFC2 and DPFC3, and input the monitoring signals to the control chip; It also includes an input power monitoring module, which monitors the AC input signal and inputs the monitoring signal to the control chip.

2. The single-control, dual-stage boost PFC circuit according to claim 1, characterized in that: The boost circuit includes an inductor LPFC:A, a diode DPFC1, a switching transistor QPFC, and a driving circuit for the switching transistor QPFC. The inductor LPFC:A is coupled to an inductor LPFC:B. One end of the inductor LPFC:A is connected to the AC input signal rectified by the rectifier circuit, and the other end is connected to the anode of the diode DPFC1. The cathode of the diode DPFC1 is connected to the anode of the DPFC3. The positive terminal of the switching transistor QPFC is connected to the AC input signal rectified by the rectifier circuit, and the negative terminal is connected to the anode of the diode DPFC1. The control chip controls the driving of QPFC through the driving circuit.

3. The single-control, two-stage boost PFC circuit according to claim 1, characterized in that: C4 is a high-voltage electrolytic capacitor.

4. The single-control, two-stage boost PFC circuit according to any one of claims 1-3, characterized in that: It also includes a second output power monitoring module, which monitors the output power of the next stage circuit and inputs the monitoring signal into the control chip.

5. A surge suppression circuit, used in conjunction with the single-controlled dual-stage boost PFC circuit according to any one of claims 1-4, characterized in that... The circuit includes a switching transistor Qr, a control and drive circuit for Qr, a diode Din, and a surge suppression resistor RT. The negative terminal of Qr is connected to the lower end of C5, the positive terminal of Qr is connected to the positive terminal of QPFC and outputs voltage to the next stage circuit. The control and drive circuit is connected to Qr to control and drive Qr. RT is connected in parallel between the positive and negative terminals of Qr. The output terminal of the rectifier circuit is connected to the anode of Din, and the cathode of Din is connected to the upper end of C5.

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