A reconfigurable frequency conversion circuit and a wireless communication device

Abstract

The embodiment of the application provides a reconfigurable frequency conversion circuit and a wireless communication device, and relates to the technical field of frequency multiplication amplification circuit. Wherein, the front-stage driving amplification stage (1), the frequency multiplication stage (2), the filter (3) and the final-stage power amplification stage (4) are electrically connected in sequence. The frequency multiplication stage (2) comprises a DC bias control circuit (201) and a reverse-parallel diode pair (202). The first end of the reverse-parallel diode pair (202) is connected with the first end of the DC bias control circuit (201), the front-stage driving amplification stage (1) and the filter (3); and the second end of the reverse-parallel diode pair (202) is grounded. Whether the second end of the DC bias control circuit is connected with the first DC control voltage is controlled, that is, different frequency multiplication switching is realized, a plurality of sets of circuits are not needed, each set of circuit corresponds to one frequency multiplication, which is helpful to reduce the equipment cost and improve the integration, that is, the beneficial effects of the application.

Description

Technical Field

[0001] This application relates to the field of frequency multiplier amplifier circuit technology, and more particularly to a reconfigurable frequency converter circuit and a wireless communication device. Background Technology

[0002] Frequency multipliers are widely used in radar systems, electronic devices, and other wireless communication systems to process low-frequency signals to obtain high-frequency signals.

[0003] The core unit inside the frequency multiplier is the frequency multiplier amplifier circuit. Its working mode is to change the frequency of the input fundamental signal by an integer multiple and then amplify the power before transmitting it to the output.

[0004] Current communication technology cannot meet this need: frequency multiplier circuits can perform adjustable frequency conversion times, or reconfigurable frequency conversion, and the frequency conversion method is simple and reliable.

[0005] Therefore, researching reconfigurable frequency multiplier amplifier circuit structures is of great significance, as it helps to reduce equipment costs and improve integration. Summary of the Invention

[0006] The purpose of this application is to provide a reconfigurable frequency conversion circuit and a wireless communication device to solve the problem of how to realize a frequency multiplier circuit with adjustable frequency conversion times in the prior art.

[0007] To achieve the above objectives, the embodiments of this application adopt the following technical solutions.

[0008] In a first aspect, embodiments of this application provide a reconfigurable frequency converter circuit, including: a pre-stage driver amplifier, a frequency multiplier, a filter, and a final stage power amplifier. The pre-stage driver amplifier, the frequency multiplier, the filter, and the final stage power amplifier are electrically connected in sequence.

[0009] The frequency multiplier stage includes a DC bias control circuit and a pair of reverse parallel diodes.

[0010] The first terminal of the anti-parallel diode pair is connected to the first terminal of the DC bias control circuit, the pre-stage driver amplifier stage, and the filter; the second terminal of the anti-parallel diode pair is grounded or RF grounded through a capacitor.

[0011] When the second terminal of the DC bias control circuit is connected to the first DC control voltage, one of the diodes in the anti-parallel diode pair is in the forward conduction state, and the reconfigurable frequency converter circuit is in the double frequency operation state.

[0012] When the second terminal of the DC bias control circuit is not connected to the first DC control voltage, the reverse parallel diode pair is in a symmetrical state, and the reconfigurable frequency converter is in a triple frequency operation state.

[0013] Optionally, the frequency multiplication stage further includes a first matching network;

[0014] The first end of the reverse parallel diode pair is connected to the pre-amplifier stage through the first matching network.

[0015] Optionally, the pre-amplifier stage includes an input matching network, a first DC bias circuit, a second DC bias circuit, and a transistor;

[0016] The control electrode of the transistor is connected to the first terminal of the first DC bias circuit and the input matching network, the first electrode of the transistor is grounded, and the second electrode of the transistor is connected to the first terminal of the second DC bias circuit and the first terminal of the anti-parallel diode pair.

[0017] The second terminal of the first DC bias circuit is connected to the second DC control voltage, and the second terminal of the second DC bias circuit is connected to the third DC control voltage.

[0018] Optionally, the pre-amplifier stage further includes an RLC negative feedback circuit, which is connected between the control electrode and the second electrode of the transistor.

[0019] Optionally, the RLC negative feedback circuit includes an inductor, a resistor, and a capacitor. One end of the series connection of the inductor, the resistor, and the capacitor is connected to the control electrode of the transistor, and the other end is connected to the second electrode of the transistor.

[0020] Optionally, the final power amplifier stage includes at least one amplifier stage circuit; the amplifier stage circuit includes: an input matching network, an output matching network, a MOSFET, a gate DC bias circuit, and a drain DC bias circuit;

[0021] The gate of the MOS transistor is connected to the previous stage circuit through the input matching network, the gate of the MOS transistor is connected to the gate DC bias circuit, and the drain of the MOS transistor is connected to the drain DC bias circuit and the output matching network.

[0022] When an amplifier circuit consists of multiple stages, the output matching network of the previous stage amplifier circuit serves as the input matching network of the next stage.

[0023] Optionally, the transistor is a field-effect transistor based on III-V compound semiconductor technology, wherein the control electrode of the transistor is the gate, the first electrode is the source, and the second electrode is the drain.

[0024] Optionally, the filter is a high-pass absorption filter.

[0025] Optionally, the reverse parallel diode pair includes a first diode and a second diode, with one end of the first diode and the second diode connected in reverse parallel to the first terminal of the DC bias control circuit, and the other end grounded.

[0026] Secondly, embodiments of this application provide a wireless communication device, which includes the reconfigurable frequency converter circuit described in the first aspect.

[0027] Compared with the prior art, the reconfigurable frequency converter circuit and wireless communication device provided in this application have the following advantages:

[0028] When the second terminal of the DC bias control circuit is not connected to the first DC control voltage, the reverse parallel diode pair is in a symmetrical state. When the input power is sufficient to achieve nonlinear operation, the even harmonic frequency multiplication signal generated by the reverse parallel diode pair will be canceled, and only the odd harmonic frequency multiplication signal will be output to the next stage, thereby achieving triple frequency multiplication.

[0029] When the second terminal of the DC bias control circuit is connected to the first DC control voltage, one of the diodes in the anti-parallel diode pair is in the forward conduction state, thus losing symmetry with the other diode; when the input power is sufficient to achieve nonlinear operation, the anti-parallel diode pair will generate several harmonic frequency multipliers relative to the fundamental frequency, and the output frequency conversion signal will be transmitted to the next stage, wherein the generated second harmonic is filtered and output to the subsequent stage, thereby achieving frequency doubling.

[0030] Based on the principles of triplet and doublet frequencies, controlling whether the second terminal of the DC bias control circuit is connected to the first DC control voltage enables different frequency multiplication switching. This eliminates the need for each circuit to correspond to a specific frequency multiplication, which helps reduce equipment costs and improve integration. Attached Figure Description

[0031] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 A structural block diagram of a reconfigurable frequency multiplier circuit provided in this application embodiment;

[0033] Figure 2 A circuit diagram of a reconfigurable frequency multiplier circuit provided for an embodiment of this application;

[0034] Figure 3A schematic diagram of a reverse parallel diode connected to radio frequency ground is provided in an embodiment of this application;

[0035] Figure 4 A schematic diagram of a pre-amplifier stage provided in this application embodiment includes an input matching network, a first DC bias circuit, a second DC bias circuit, and transistors;

[0036] Figure 5 A schematic diagram of a negative feedback circuit with the gate and drain of a transistor in a pre-stage driver amplifier provided in an embodiment of this application;

[0037] Figure 6 A schematic diagram of a reconfigurable frequency multiplier circuit that processes 7-13.5GHz to 21-27GHz, provided for an embodiment of this application;

[0038] Figure 7 This is a schematic diagram of the second harmonic frequency doubling output power curve for an implementation example of this application;

[0039] Figure 8 This is a schematic diagram of the third harmonic frequency multiplication output power curve for an implementation example of this application.

[0040] Explanation of reference numerals in the attached figures:

[0041] 1-Preamplifier stage

[0042] 2-Hyperfrequency

[0043] 3-Filter

[0044] 4-Final power amplifier stage

[0045] 101-Input Matching Network

[0046] 102-First DC Bias Circuit

[0047] 103-Second DC Bias Circuit

[0048] 201-DC Bias Control Circuit

[0049] 202-Reverse Parallel Diode Pair

[0050] 203-First Matching Network Detailed Implementation

[0051] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. The described embodiments are only some embodiments of this application, not all embodiments. The components of the embodiments of this application described in the accompanying drawings can generally be arranged and designed in various different configurations.

[0052] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0053] In the description of this application, it should be noted that relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. The term "connection" should be interpreted broadly, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection or an indirect connection through an intermediate medium.

[0054] With the development of communication technology, there is a need for frequency multiplier circuits with adjustable frequency conversion times. Therefore, embodiments of this application provide a reconfigurable frequency conversion circuit, which can be referred to in the following sections. Figure 1 The reconfigurable frequency converter circuit includes: a pre-amplifier stage 1, a frequency multiplier stage 2, a filter stage 3, and a final power amplifier stage 4. These stages are electrically connected in sequence. The fundamental signal is input from the pre-amplifier stage 1, passes through the frequency multiplier stage 2, filter stage 3, and final power amplifier stage 4, and is then output as a multiplied signal.

[0055] like Figure 2 The frequency multiplier 2 includes a DC bias control circuit 201 and a pair of reverse parallel diodes 202.

[0056] To describe the connection relationships, the following definitions are made for each end in the diagram. :

[0057] The lower end of the reverse parallel diode pair 202 in the figure is defined as the first end, and the upper end is defined as the second end; the upper end of the DC bias control circuit 201 is defined as the first end, and the lower end is defined as the second end.

[0058] Then The connection relationship is described as follows: :

[0059] The first terminal of the anti-parallel diode pair 202 is connected to the first terminal of the DC bias control circuit 201, the pre-stage driver amplifier stage 1, and the filter 3; the second terminal of the anti-parallel diode pair 202 is grounded.

[0060] The following is an introduction The principle of this reconfigurable frequency converter circuit :

[0061] 1. When the second terminal of the DC bias control circuit is not connected to the first DC control voltage, the reverse parallel diode pair is in a symmetrical state. When the input power is sufficient to achieve nonlinear operation, the even harmonic frequency multiplication signal generated by the reverse parallel diode pair will be canceled. Only the odd harmonic frequency multiplication signal is output to the next stage, and the third harmonic is output to the subsequent stage after passing through the filter, thereby achieving the third harmonic multiplication.

[0062] 2. When the second terminal of the DC bias control circuit is connected to the first DC control voltage, one of the diodes in the anti-parallel diode pair is in the forward conduction state. The DC bias control circuit makes the diode work at the turn-on voltage, thus losing symmetry with the other diode. When the input power is sufficient to achieve nonlinear operation, the anti-parallel diode pair will generate several harmonic frequency multipliers relative to the fundamental frequency. The output frequency conversion signal will be transmitted to the next stage. The generated second harmonic is filtered and output to the subsequent stage, thereby achieving frequency doubling.

[0063] Based on the principles described in points 1 and 2 above, controlling whether the second terminal of the DC bias control circuit is connected to the first DC control voltage achieves different frequency multiplication switching. This eliminates the need for multiple circuits, each corresponding to a specific frequency multiplication. Furthermore, the solution presented in this application has a simple structure, is easy to design, and helps reduce equipment costs and improve integration. The beneficial effects of this application are .

[0064] The DC bias control circuit 201 can be composed of components such as resistors. The DC bias control circuit 201 can be a constant voltage circuit, which plays the role of current limiting and voltage stabilization.

[0065] If the reverse parallel diode pair 202 is a diode made using III-V GaAs technology, the voltage provided by the DC bias control circuit 201 can be set to 1V, so that the diode just turns on.

[0066] like Figure 3 The second terminal of the reverse parallel diode 202 can also be connected to a constant voltage, but it must be grounded via a capacitor at least.

[0067] The preamplifier stage 1 can be implemented by a power amplifier with ultra-wideband characteristics, covering a wider fundamental frequency band.

[0068] like Figure 4 The pre-amplifier stage 1 may include an input matching network 101, a first DC bias circuit 102, a second DC bias circuit 103, and a transistor FET 1.

[0069] The connection relationships are described as follows: The control electrode of transistor FET1 is connected to the first terminal of the first DC bias circuit 102 and the input matching network 101. The first terminal of transistor FET1 is grounded. The second terminal of transistor FET1 is connected to the first terminal of the second DC bias circuit 103 and the first terminal of the anti-parallel diode pair 202. The second terminal of the first DC bias circuit 102 is connected to the second DC control voltage Vcc2, and the second terminal of the second DC bias circuit 103 is connected to the third DC control voltage Vcc3.

[0070] The first DC bias circuit 102 and the second DC bias circuit 103 can block and isolate the radio frequency signal, while allowing DC to pass through.

[0071] Specifically, to achieve ultra-wideband power amplification, a negative feedback circuit can be connected in parallel between the gate and drain of transistor FET1, such as... Figure 5 The negative feedback circuit consists of a resistor R1, a capacitor C1, and an inductor L1 connected in series.

[0072] The input matching network 101 is placed before the gate of the first transistor, as follows: Figure 5 The first matching network 203 can be placed after the drain of the first transistor. The input fundamental signal is transmitted to the first transistor through the input matching network 101 for power amplification, and then transmitted to the next stage through the first matching network 203.

[0073] The subsequent filter 3 can be a high-pass absorption filter, composed of resistors, inductors, and capacitors. The resistors are used to absorb the low-frequency fundamental radio frequency signal in the stopband, while the useful frequency conversion signal generated by the frequency multiplier stage can be transmitted to the next stage through the high-pass absorption filter. A band-pass absorption filter can also be used, but band-pass filters have higher losses and more complex circuit structures. This invention prefers a high-pass structure.

[0074] In particular, the purpose of a high-pass absorption filter is to transmit harmonic signals with low loss and to absorb low-frequency stopband signals without reflection, so as to prevent low-frequency reflected signals from intermodulating the harmonic stage and affecting efficiency.

[0075] The final power amplifier stage 4 can be composed of multiple amplifier stages, including: an input matching network, an output matching network, a MOSFET, a gate DC bias circuit, and a drain DC bias circuit. The connections are as follows: the MOSFET's gate is connected to the previous stage via the input matching network; the MOSFET's gate is connected to the gate DC bias circuit; and the MOSFET's drain is connected to the drain DC bias circuit and the output matching network. When the amplifier stage includes multiple stages, the output matching network of the previous stage serves as the input matching network of the next stage.

[0076] All the aforementioned transistors, including MOSFETs, can be manufactured using III-V compound semiconductor technology, offering advantages such as high gain, high output power, and high efficiency.

[0077] Figure 6 In the example, the input signal of the frequency multiplier circuit needs to be amplified to two frequency bands. The operating frequency band of the pre-stage driver amplifier circuit is 7–13.5 GHz. After the input signal passes through transistor FTE1, it is amplified and output to the next stage. To achieve high-efficiency transmission, the first matching network needs to be strictly designed to ensure that the output power meets the input power requirements of the frequency multiplier stage. The passband of the high-pass absorption filter can be 21 GHz and above, and the stopband can be 13.5 GHz and below. For the final power amplifier stage composed of FET2 and FET3, the 21–27 GHz frequency multiplier signal input from the previous stage is amplified by two stages and then output to the output port. Figure 7 The output power curve of the second harmonic frequency multiplication in this implementation case is shown. The horizontal axis represents the input signal frequency. It can be seen that the second harmonic output power reaches more than 20dBm, while the power of other harmonic frequencies and the fundamental frequency is relatively small. Figure 8 This is the output power curve of the third harmonic overlay in this implementation case. The horizontal axis represents the input signal frequency. It can be seen that the third harmonic output power reaches more than 21dBm, while the power of other harmonic frequencies and the fundamental frequency is relatively small.

[0078] Based on the above embodiments, this application also provides a wireless communication device, which includes the above-described reconfigurable frequency conversion circuit.

[0079] The apparatus and system embodiments described above are merely illustrative. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement these embodiments without any creative effort.

[0080] The above are merely preferred embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A reconfigurable frequency converter circuit, characterized in that, include: The pre-stage driver amplifier (1), frequency multiplier (2), filter (3), and final stage power amplifier (4) are connected in sequence. The frequency multiplier (2) includes a DC bias control circuit (201) and a pair of reverse parallel diodes (202); The first end of the anti-parallel diode pair (202) is connected to the first end of the DC bias control circuit (201), the pre-stage driver amplifier stage (1), and the filter (3); the second end of the anti-parallel diode pair (202) is grounded or grounded via a capacitor. When the second terminal of the DC bias control circuit (201) is connected to the first DC control voltage (Vcc1), one of the diodes in the reverse parallel diode pair (202) is in the forward conduction state, and the reconfigurable frequency converter is in the double frequency operation state. When the second terminal of the DC bias control circuit (201) is not connected to the first DC control voltage (Vcc1), the reverse parallel diode pair (202) is in a symmetrical state, and the reconfigurable frequency converter is in a triple frequency operation state.

2. The reconfigurable frequency converter circuit as described in claim 1, characterized in that, The frequency multiplication stage (2) also includes a first matching network (203); The first end of the reverse parallel diode pair (202) is connected to the pre-stage driver amplifier stage (1) through the first matching network (203).

3. The reconfigurable frequency converter circuit as described in claim 1, characterized in that, The pre-amplifier stage (1) includes an input matching network (101), a first DC bias circuit (102), a second DC bias circuit (103), and a transistor (FET1); The control terminal of the transistor (FET1) is connected to the first terminal of the first DC bias circuit (102) and the input matching network (101), the first terminal of the transistor (FET1) is grounded, and the second terminal of the transistor (FET1) is connected to the first terminal of the second DC bias circuit (103) and the first terminal of the anti-parallel diode pair (202); The second terminal of the first DC bias circuit (102) is connected to the second DC control voltage (Vcc2), and the second terminal of the second DC bias circuit (103) is connected to the third DC control voltage (Vcc3).

4. The reconfigurable frequency converter circuit as described in claim 3, characterized in that, The pre-stage drive amplifier (1) also includes an RLC negative feedback circuit, which is connected between the control electrode and the second electrode of the transistor (FET1).

5. The reconfigurable frequency converter circuit as described in claim 4, characterized in that, The RLC negative feedback circuit includes an inductor (L1), a resistor (R1), and a capacitor (C1). One end of the series connection of the inductor (L1), the resistor (R1), and the capacitor (C1) is connected to the control electrode of the transistor (FET1), and the other end is connected to the second electrode of the transistor (FET1).

6. The reconfigurable frequency converter circuit as described in claim 1, characterized in that, The final power amplifier stage (4) includes at least one amplifier stage circuit; the amplifier stage circuit includes: an input matching network, an output matching network, a MOS transistor, a gate DC bias circuit, and a drain DC bias circuit; The gate of the MOS transistor is connected to the previous stage circuit through the input matching network, the gate of the MOS transistor is connected to the gate DC bias circuit, and the drain of the MOS transistor is connected to the drain DC bias circuit and the output matching network. When an amplifier circuit consists of multiple stages, the output matching network of the previous stage amplifier circuit serves as the input matching network of the next stage.

7. The reconfigurable frequency converter circuit as described in claim 3, characterized in that, The transistor (FET1) is a field-effect transistor based on III-V compound semiconductor technology. The control electrode of the transistor (FET1) is the gate, the first electrode is the source, and the second electrode is the drain.

8. The reconfigurable frequency converter circuit as described in claim 1, characterized in that, The filter (3) is a high-pass absorption filter.

9. The reconfigurable frequency converter circuit as described in claim 1, characterized in that, The reverse parallel diode pair (202) includes a first diode and a second diode. One end of the first diode and the second diode are connected in reverse parallel to the first terminal of the DC bias control circuit (201), and the other end is grounded.

10. A wireless communication device, characterized in that, The wireless communication device includes the reconfigurable frequency converter circuit as described in any one of claims 1-9.

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