Digital time-to-digital converter circuit structure with gain adjustment and integral nonlinearity calibration

Abstract

The application discloses a digital time converter circuit structure with gain adjustment and integral nonlinearity calibration, which comprises a first D flip-flop, a second D flip-flop, a phase interpolator composed of a first inverter array and a second inverter array, a rear-stage inverter, an XOR gate, an integral nonlinearity detection module and an integral nonlinearity calibration module. In the application, the frequency of an input clock CKgain determines the gain of the digital time converter. The phase interpolator controls the number of the gating of the two inverter arrays by digital control words X and Y, so as to change the output phase and perform shaping by the rear-stage inverter. The integral nonlinearity detection module and the integral nonlinearity calibration module in the application realize the calibration of the integral nonlinearity of the digital time converter by adjusting the digital control words X and Y of the two inverter arrays.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuits, and more specifically to a digital time converter circuit structure with gain adjustment and integral nonlinear calibration. Background Technology

[0002] In many systems, time delay or phase shift functionality is crucial. In such systems, a digital time converter (DTC) is used to implement programmable delays on the input clock based on digital input codes. The two most important applications of DTCs are clock data recovery circuits (CDRs) and phase-locked loops (PLLs) in high-speed serial ports. CDR is a classic application of DTCs. When a high-speed serial port receiver receives a string of "0"s and "1"s from the transmitter, it needs to know when to sample this level. Ideally, sampling should occur after the symbol code has stabilized, so a DTC is needed to control the clock delay, thus flexibly controlling the sampling time. In PLLs, this is a more recent development, used to implement fractional-number phase-locked loop functionality. In all DTC-based applications, a high-performance DTC is critical to the overall system performance. For example, in fully digital PLLs, the nonlinearity of the DTC leads to high spurious emissions.

[0003] The most important metrics for DTC are gain and linearity. Gain refers to the maximum controllable delay of the DTC. Linearity of the DTC includes integral nonlinearity (INL) and differential nonlinearity (DNL). Linearity measures whether the delay generated by the DTC changes linearly with the digital control signal. Therefore, achieving variable delay while maintaining high performance is the most critical problem to be solved in DTC.

[0004] Delay line timing regulation (DTC) uses a chain of delay stages to achieve variable time delays. While simple, this method suffers from limited resolution and high power consumption, especially when a wide dynamic range is required. Another way to implement DTC is by controlling the values ​​of a capacitor bank to achieve different delays. This method still involves a trade-off between dynamic range and power consumption. Furthermore, mismatch between capacitors increases the nonlinearity of the DTC. A common method for calibrating nonlinearity is the least mean square (LMS) calibration method; however, this calibration can only be performed within the loop and is slow, on the order of hundreds of microseconds or even milliseconds.

[0005] In addition, most architectures do not focus on the adjustable gain of the DTC. However, since the full-scale range of the DTC may not remain constant under process deviations and temperature changes, the DTC needs gain calibration, which involves changing the correspondence between the input control codeword and the DTC delay. Summary of the Invention

[0006] Objective: This invention addresses the problems of unadjustable gain and poor integral nonlinearity in existing technologies by providing a digital time converter circuit with variable gain adjustment and integral nonlinearity calibration. Compared to traditional digital time converter circuits, this invention offers the advantages of adjustable gain and higher linearity.

[0007] Technical Solution: To achieve the above-mentioned objectives, the present invention provides a digital time converter circuit structure with gain adjustment and integral nonlinear calibration, employing the following technical solution:

[0008] A digital time converter circuit structure with gain adjustment and integral nonlinearity calibration is provided. The circuit structure includes a first D flip-flop, a second D flip-flop, a first inverter array, a second inverter array, a capacitor C1, a subsequent inverter, an XOR gate, an integral nonlinearity detection module, an integral nonlinearity calibration module, and control word A and B generation modules. The circuit structure generates different degrees of delay based on control words A and B.

[0009] Preferred,

[0010] The input terminal of the first D flip-flop is connected to the clock signal CKin, and the clock control terminal of the first D flip-flop is connected to the clock signal CKgain, generating the clock signal CK1;

[0011] The input terminal of the second D flip-flop is connected to the clock signal CK1, and the clock control terminal of the second D flip-flop is connected to the clock signal CKgain to generate the clock signal CK2;

[0012] The input terminal of the first inverter array is the clock signal CK1, which is controlled by the digital control word X;

[0013] The input of the second inverter array is the clock signal CK2, which is controlled by the digital control word Y;

[0014] The outputs of the first inverter array and the second inverter array are shorted and connected to capacitor C1. Capacitor C1 is connected to the input of the subsequent inverter. The output of the subsequent inverter outputs the delayed signal CKout.

[0015] The first input terminal of the XOR gate is connected to the clock signal CK1, the second input terminal is connected to the clock signal CKout, and the output terminal of the XOR gate is connected to the integral nonlinearity detection module.

[0016] The output of the integral nonlinearity detection module is connected to the integral nonlinearity calibration module. The control word A and B generation module generates control words A and B and sends them to the integral nonlinearity calibration module. The integral nonlinearity calibration module adjusts the control words A and B to generate new control words X and Y to control the first inverter array and the second inverter array.

[0017] Preferably, the XOR gate generates a pulse CKpulse, the pulse width of which represents the phase difference between the clock signal CK1 and the clock signal CKout, i.e., the delay generated by the digital time converter.

[0018] The workflow of the integral nonlinearity detection module includes steps one and two, wherein:

[0019] Step 1: Sample the delay (Delay) under different control words A and B;

[0020] Step 2: Determine if the current delay equals the ideal delay;

[0021] The workflow of the integral nonlinear calibration module includes steps a and b, wherein:

[0022] Step a: Fit the relationship curves between control words A and B and the delay under integral nonlinearity;

[0023] Step b: Calculate the new control words X and Y required now.

[0024] Preferably, both the first inverter array and the second inverter array include N inverters connected in parallel. The number of inverters selected in the first inverter array is controlled by a digital control word X, and the number of inverters selected in the second inverter array is controlled by a digital word Y.

[0025] Beneficial effects: Compared with the prior art, the beneficial effects of this invention are:

[0026] 1. The gain of the digital time converter can be changed simply by changing the period T of the input clock CKgain, thus achieving adjustable gain.

[0027] 2. The output delay can be changed by altering the number of selected inverters in the first and second inverter arrays through the control word. This eliminates the need for large adjustable capacitors, reducing area while improving linearity.

[0028] 3. By utilizing the integral nonlinearity detection module and the integral nonlinearity calibration module, the linearity is further improved digitally. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of the circuit structure of the digital time converter with gain adjustment and integral nonlinear calibration of the present invention;

[0030] Figure 2 This is a schematic diagram of the output clock timing of the two D flip-flops of the present invention;

[0031] Figure 3 The output waveforms of two inverter arrays with different numbers of selected inverters according to the present invention are shown.

[0032] Figure 4 The output signal CKout waveforms under different control words of this invention are shown below.

[0033] Figure 5 This is a flowchart illustrating the operation of the integral nonlinearity detection module and the integral nonlinearity calibration module of the present invention. Detailed Implementation

[0034] The technical solution of the present invention will be described in detail below with reference to specific embodiments and accompanying drawings.

[0035] like Figure 1 As shown, the present invention discloses a digital time converter circuit structure with gain adjustment and integral nonlinear calibration. The circuit structure delays the input signal CKin to different degrees based on digital control words X and Y. It includes a first D flip-flop, a second D flip-flop, a first inverter array, a second inverter array, a capacitor C1, a subsequent inverter, an integral nonlinearity detection module, an integral nonlinearity calibration module, and a control word A / B generation module.

[0036] Specifically, when this circuit starts working, its operation includes the following processes:

[0037] The first D flip-flop has its input connected to clock signal CKin and its clock control terminal connected to clock signal CKgain, generating clock signal CK1. The output clock signal CK1 of the first D flip-flop is synchronized with the rising edge of clock signal CKgain. The second D flip-flop has its input connected to clock signal CK1 and its clock control terminal connected to clock signal CKgain, generating clock signal CK2. The output clock signal CK2 of the second D flip-flop is delayed by one clock period T (CKgain) compared to clock signal CK1. That is, the phase difference between the output clock signals CK1 and CK2 of the two D flip-flops is equal to one clock period T (CKgain). Figure 2 The timing diagram is shown in the figure.

[0038] The inputs of the first and second inverter arrays are connected to clock signals CK1 and CK2, respectively, and their outputs are directly shorted together. Before the rising edges of clock signals CK1 and CK2 arrive, the PMOS transistors of the selected inverters in the first and second inverter arrays are turned on, and the NMOS transistors are turned off, resulting in a high-level output. Next, the rising edge of clock signal CK1 arrives first, turning on the NMOS transistors of the selected inverters in the first inverter array, which begin discharging the capacitor at the output node. The output level gradually decreases, and the discharge rate is determined by the number of selected inverters in the first inverter array. This continues until the rising edge of clock signal CK2 arrives, at which point the NMOS transistors of the selected inverters in the second inverter array also turn on, discharging the capacitor at the output node together until the output level becomes low. Similarly, before the falling edges of clock signals CK1 and CK2 arrive, the NMOS transistors of the selected inverters in the first and second inverter arrays are turned on, and the PMOS transistors are turned off, maintaining a low-level output. Next, the falling edge of clock signal CK1 arrives first, turning on the PMOS transistors of the selected inverters in the first inverter array, and starting to charge the capacitor at the output node. The output level gradually increases, and the charging speed is determined by the number of selected inverters in the first inverter array. This continues until the falling edge of clock signal CK2 arrives, at which point the PMOS transistors of the selected inverters in the second inverter array also turn on, charging the capacitor at the output node together until the output level becomes high. The final output voltage waveform can be approximated using a piecewise straight line.

[0039] The output phase can be changed by altering the number of inverters selected in the two inverter arrays. When the first inverter array selects more inverters, more charge is discharged in the first discharge stage, resulting in an earlier phase in the final output waveform; conversely, when the first inverter array selects fewer inverters, less charge is discharged in the first discharge stage, resulting in a later phase in the final output waveform. The charging on the falling edge is similar to the discharging on the rising edge. The resulting different output waveforms are shown below. Figure 3 As shown.

[0040] The subsequent inverter shapes the output of the phase interpolator, which consists of the first and second inverter arrays. The waveform of the output signal CKout is as follows: Figure 4 As shown. The maximum adjustment range of the phase interpolator output phase is equal to the phase difference between the two input clocks CK1 and CK2, that is, the gain of the digital time converter is equal to the period T of the input clock CKgain. Changing the period T of the input clock CKgain changes the gain of the digital time converter.

[0041] Both the first and second inverter arrays include N inverters connected in parallel. The number of inverters selected in the two sets of inverter arrays is controlled by digital control words A and B, respectively, without integral nonlinearity calibration. Given the gain of the digital time converter, if the digital time converter has no integral nonlinearity, the ideal delay Delay_ideal = k × (A / B) can be obtained. However, integral nonlinearity may exist in actual circuits. Therefore, the XOR gate, the integral nonlinearity detection module, and the integral nonlinearity calibration module are used to calibrate any potential integral nonlinearity, ensuring that there is no integral nonlinearity between the newly generated control word X / Y and the actual delay, i.e., Delay_real = k × (X / Y).

[0042] The XOR gate XORs the output signal CKout with the input clock CK1, generating a pulse CKpulse. The pulse width of CKpulse represents the phase difference between clock signals CK1 and CKout, i.e., the actual delay Delay_real generated by the digital time converter. The workflow of the integral nonlinearity detection module includes: Step 1: Sampling the delay Delay_real under different control words A / B; Step 2: Determining whether the current delay Delay_real is equal to the ideal delay Delay_ideal. If yes, the circuit does not have integral nonlinearity, and the integral nonlinearity calibration module outputs a new control word X / Y = A / B. If no, the workflow of the integral nonlinearity calibration module includes: Step 1: Fitting the relationship curve between control word A / B and delay under integral nonlinearity Delay_real = f(A / B); Step 2: Calculating the required new control word X / Y, X / Y = k-1 × Delay_real = k -1 ×f(A / B). The specific workflow is as follows: Figure 5 As shown.

[0043] As described above, although the invention has been shown and described with reference to specific preferred embodiments, it should not be construed as limiting the invention itself. Various changes in form and detail may be made without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A digital time converter circuit structure with gain adjustment and integral nonlinear calibration, characterized in that: The circuit structure includes a first D flip-flop, a second D flip-flop, a first inverter array, a second inverter array, a capacitor C1, a subsequent inverter, an XOR gate, an integral nonlinearity detection module, an integral nonlinearity calibration module, and a control word A and B generation module. The circuit structure generates different degrees of delay based on control words A and B. The input terminal of the first D flip-flop is connected to the clock signal CKin, and the clock control terminal of the first D flip-flop is connected to the clock signal CKgain, generating the clock signal CK1; The input terminal of the second D flip-flop is connected to the clock signal CK1, and the clock control terminal of the second D flip-flop is connected to the clock signal CKgain to generate the clock signal CK2; The input terminal of the first inverter array is the clock signal CK1, which is controlled by the digital control word X; The input of the second inverter array is the clock signal CK2, which is controlled by the digital control word Y; The outputs of the first inverter array and the second inverter array are shorted and connected to capacitor C1. Capacitor C1 is connected to the input of the subsequent inverter. The output of the subsequent inverter outputs the delayed signal CKout. The first input terminal of the XOR gate is connected to the clock signal CK1, the second input terminal is connected to the clock signal CKout, and the output terminal of the XOR gate is connected to the integral nonlinearity detection module. The output of the integral nonlinearity detection module is connected to the integral nonlinearity calibration module. The control word A and B generation module generates control words A and B and sends them to the integral nonlinearity calibration module. The integral nonlinearity calibration module adjusts control words A and B to generate new control words X and Y to control the first inverter array and the second inverter array.

2. The digital time converter circuit structure with gain adjustment and integral nonlinear calibration according to claim 1, characterized in that: The XOR gate generates a pulse CKpulse, and the pulse width of the pulse CKpulse represents the phase difference between the clock signal CK1 and the clock signal CKout, which is the delay generated by the digital time converter. The workflow of the integral nonlinearity detection module includes steps one and two, wherein: Step 1: Sample the delay (Delay) under different control words A and B; Step 2: Determine if the current delay equals the ideal delay; The workflow of the integral nonlinear calibration module includes steps a and b, wherein: Step a: Fit the relationship curves between control words A and B and the delay under integral nonlinearity; Step b: Calculate the new control words X and Y required now.

3. The digital time converter circuit structure with gain adjustment and integral nonlinear calibration according to claim 2, characterized in that: Both the first inverter array and the second inverter array include N inverters connected in parallel. The number of inverters selected in the first inverter array is controlled by a digital control word X, and the number of inverters selected in the second inverter array is controlled by a digital word Y.

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