Control methods and implementation circuits for a wide output current range

Abstract

This invention relates to the field of LED driver power supply technology. The wide output current range control method disclosed in this invention employs two-stage control of the peak output inductor current IL. PEAK Adjust the current reference level V REF From the maximum value to zero, while the blanking time is a fixed maximum value during this period; when the current reference level V REF After reaching zero, maintain the current reference level V. REF The blanking time is adjusted from a fixed maximum value to a minimum value to make the peak current IL of the output inductor zero. PEAK The value is further reduced. This method also provides an implementation circuit, where the N-bit reversible up / down counter and the N-bit analog-to-digital converter (DAC) are connected to the output current reference level VREF, and the M-bit reversible up / down counter and the M-bit DAC are connected to output an analog voltage to control the blanking time. This invention adjusts the peak current IL of the output inductor in two stages. PEAK This value enables a wide range of current output for the drive power supply.

Description

Technical Field

[0001] This invention relates to the field of LED driver power supply technology, specifically to a control method and implementation circuit for a wide output current range. Background Technology

[0002] In LED dimming lighting applications, it is desirable for the output current Io of the LED driver power supply to have a wide range of variation to ensure a wide range of LED output light. Typically, for an LED driver switching power supply, the output current is determined by the time average of the output inductor current within the LED driver switching power supply. For the minimum output current Io... MIN At that time, the output inductor current IL(t) in the LED driver switching power supply has entered discontinuous mode. When the minimum output current Io... MIN At this time, the time average of the output inductor current IL(t) in the LED driver switching power supply is determined by the peak output inductor current IL. PEAK The switching period Ts of the output inductor is determined. This is based on the minimum peak current IL of the output inductor. PEAK Minimum output current Io MIN It is inversely proportional to the repeated switching period Ts of the output inductor. To expand the range of output current variation, i.e., to reduce the output current Io... MIN This further increases the repetitive switching cycle Ts. To avoid audible noise in the LED driver power supply, the repetitive switching cycle Ts of the LED driver switching power supply must be less than 50µs, i.e., the switching frequency must be greater than 20kHz. Clearly, to ensure that the repetitive switching cycle Ts of the LED driver switching power supply is less than 50µs, i.e., the switching frequency must be greater than 20kHz, while the output current Io... MIN The direction for further reduction is to further reduce the minimum peak current IL of the output inductor. PEAK However, this leads to the problem that the minimum resolution of the current comparator, the delay response time of the current comparator, and the limitations of the blanking circuit prevent further reduction of the minimum peak output inductor current IL. PEAK Therefore, it is necessary to propose a method to further reduce the peak current IL of the output inductor. PEAK A feasible method. Summary of the Invention

[0003] The technical problem to be solved by this invention is to provide a wide output current range control method and implementation circuit, so that the LED driver power supply can reduce the peak current IL of the minimum output inductor. PEAK This allows the output current Io to vary over a wide range, and enables the switching frequency to always be higher than the audio frequency.

[0004] To address the aforementioned technical problems, this invention provides a wide output current range control method, specifically comprising: the time averaging of the output inductor current of the LED driver power supply is determined by the peak output inductor current IL. PEAK The peak current IL of the output inductor is determined by the repetitive switching period Ts of the output inductor. PEAK By adjusting the current reference level V REF This is achieved by using the method described above to increase the peak current IL of the output inductor. PEAK The value is controlled in two stages: the first is to adjust the current reference level V. REF From the maximum value to zero, and during this period the blanking time is a fixed maximum value; secondly, when the current reference level V REF After reaching zero, maintain the current reference level V. REF The blanking time is adjusted from its fixed maximum value to its minimum value to make the peak current IL of the output inductor zero. PEAK The value decreased further.

[0005] As an improvement to the wide output current range control method of the present invention:

[0006] The current reference level V REF The blanking time adjustment is based on the output dimming current and whether the switching frequency is greater than the audio frequency; when the output dimming current is greater than the predetermined current, if the current reference level V... REF When the value is greater than zero, the current reference level V is reduced. REF ; or if the current reference level V REF If the current is already zero, reduce the blanking time to reduce the actual output dimming current; when the corresponding switching frequency is less than the audio frequency, if the current reference level V... REF If the value is greater than zero, then the current reference level V is further reduced. REF ; or if the current reference level V REF If it is already zero, then further reduce the blanking time to ensure that the switching frequency is greater than the audio frequency.

[0007] This invention also provides a circuit for implementing a control method with a wide output current range, comprising:

[0008] The N-bit reversible up / down counter outputs an N-bit digital value, which is connected to the N-bit digital input signal of the N-bit analog-to-digital converter (DAC). The M-bit reversible up / down counter outputs an M-bit digital value, which is connected to the M-bit digital input signal of the M-bit DAC. The N-bit DAC outputs the current reference level V. REF The M-bit analog-to-digital converter (DAC) outputs an analog voltage to control the blanking time.

[0009] The logic level UPDN is connected to the addition / subtraction logic control terminals UPDN of the N-bit reversible up / down counter and UPDN of the M-bit reversible up / down counter, respectively. The clock signal Ck is connected to the clock input terminal ck of the N-bit reversible up / down counter and one input terminal of the AND gate, respectively. The all-zero output logic terminal of the N-bit reversible up / down counter is connected to the other input terminal of the AND gate, and the output terminal Ck1 of the AND gate is connected to the clock input terminal ck of the M-bit reversible up / down counter. The all-"1" output logic terminal of the M-bit reversible up / down counter is connected to the clear / set terminal of the N-bit reversible up / down counter via a logic inverter.

[0010] As an improvement to the implementation circuit of the present invention:

[0011] When the logic level UPDN is high, the current reference level V increases with the number of corresponding clock cycles Ck. REF Analog quantity and blanking time: As the analog quantity increases, when the logic level UPDN is zero, the current reference level V increases with the number of corresponding clock cycles Ck. REF The analog quantity and blanking time are reduced.

[0012] As a further improvement to the implementation circuit of the present invention:

[0013] When the reset / reset pin of the N-bit reversible up / down counter outputs a high level, the current reference level V is guaranteed. REF Reaching zero;

[0014] When the N-bit digital reversible up-and-down counter is all zero, the all-zero output logic terminal outputs a high level, the logic AND gate is turned on, and the clock signal Ck enters the M-bit digital reversible up-and-down counter through the logic AND gate.

[0015] As a further improvement to the implementation circuit of the present invention:

[0016] When the M-bit reversible up-and-down counter is all "1", the all "1" output logic terminal is high, and the blanking time reaches a fixed maximum value. When the M-bit reversible up-and-down counter is not all "1", the all "1" output logic terminal is zero. After passing through a logic inverter, it becomes a high level input to the clear and set terminal of the N-bit reversible up-and-down counter. Even with a clock Ck, the N-bit reversible up-and-down counter is in a cleared state until the M-bit reversible up-and-down counter is all "1". Then, the N-bit reversible up-and-down counter performs reversible up-and-down counting according to the UPDN logic level.

[0017] As a further improvement to the implementation circuit of the present invention:

[0018] The logic level UPDN is zero. If the initial state of an N-bit reversible up / down counter or an M-bit reversible up / down counter is all "1", the blanking time remains at a fixed maximum time, while the current reference level V... REF The maximum value decreases as the number of clock cycles Ck increases; when the digital value of the N-bit reversible up / down counter decreases from all "1"s to zero, the current reference level V... REF The analog quantity is zero. Since the all-zero output logic terminal of the N-bit digital reversible up-down counter outputs a high level, the M-bit digital reversible up-down counter has an input clock Ck1.

[0019] The corresponding logic level UPDN remains zero. As the clock Ck1 increments, the digital value of the M-bit reversible up / down counter decreases from all "1"s to zero, and the blanking time analog value reaches its minimum. When the digital value of the M-bit reversible up / down counter decreases from all "1"s, the all "1" output logic terminal of the M-bit reversible up / down counter outputs a zero level. This, via a logic inverter, continuously clears the N-bit reversible up / down counter to zero, corresponding to the output current reference level V. REF The analog quantity remains at zero.

[0020] As a further improvement to the implementation circuit of the present invention:

[0021] When the logic level UPDN is high, if the initial state of an N-bit reversible up / down counter or an M-bit reversible up / down counter is all "0", the blanking time is the minimum blanking time, and the current reference level V... REF It is also zero; the all-zero output logic terminal of the N-bit reversible up / down counter outputs a high level, and the M-bit reversible up / down counter has an input clock Ck1; it increases with the number of clocks Ck1. When the digital quantity of the M-bit reversible up / down counter increases from all "0"s to all "1"s, the blanking time analog quantity increases from its minimum value to a fixed maximum value; during the period when the blanking time analog quantity increases from its minimum value to its fixed maximum value, the all-"1" output logic terminal of the M-bit reversible up / down counter outputs a high level, which, through a logic inverter, makes the reset input of the N-bit reversible up / down counter zero level, and the N-bit reversible up / down counter is cleared, corresponding to the output current reference level V. REF The analog quantity remains zero;

[0022] The corresponding logic level UPDN remains high. As the number of clock cycles Ck increases, the digital value of the N-bit reversible up / down counter increases from all "0"s to all "1"s. The current reference level V... REF The analog quantity increases from zero to its maximum value. When the digital quantity of the N-bit reversible up-down counter is not all "0", the all-zero output logic terminal of the N-bit reversible up-down counter outputs a zero level, causing the clock Ck1 of the M-bit reversible up-down counter to disappear, and the corresponding blanking time of the analog quantity remains at a fixed maximum time.

[0023] The beneficial effects of this invention are mainly reflected in:

[0024] 1. This invention adjusts the peak current IL of the output inductor in two stages. PEAK This allows the power supply to achieve a wide range of current output, enabling the switching frequency to always be higher than the audio frequency.

[0025] 2. This invention adjusts the peak current IL of the output inductor in two stages. PEAK The value-based method, which controls the reference current level and blanking time separately, can significantly reduce the resolution and delay time requirements of the current comparator; in blanking time control, the current comparator no longer participates in controlling the peak output inductor current IL. PEAK The value is not controlled by the blanking time control circuit, but is entirely controlled by the blanking time control circuit. Attached Figure Description

[0026] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0027] Figure 1 This is a schematic diagram of the circuit for implementing the wide output current range control method of the present invention. Detailed Implementation

[0028] The present invention will be further described below with reference to specific embodiments, but the scope of protection of the present invention is not limited thereto:

[0029] Example 1

[0030] Typically, the peak current IL of the output inductor is... PEAK The control is achieved by the voltage V across the current sensing resistor Rs connected in series with the source of the main power MOSFET and ground. SENSE With the corresponding current reference level V REF The peak current IL of the output inductor is controlled by the pulse output from the current comparator to determine when the gate voltage of the main power MOSFET drops to zero. PEAK Yes. When the gate voltage of the main power MOSFET jumps from zero to high, a spike voltage V is often generated across the sensing resistor Rs. SENSE This causes the current comparator to trigger erroneously, and the output pulse to mistakenly turn off the main power MOSFET, resulting in a peak current IL in the output inductor. PEAK It cannot be established. To overcome this problem, current control chips all have a blanking circuit with a blanking time of several hundred ns. That is, when the gate voltage of the main power MOS jumps from zero voltage to high level, the voltage V generated on the sensing resistor Rs is detected. SENSE This blanking circuit, with a blanking time of several hundred ns, is then applied to the current comparator; that is, when the gate voltage of the main power MOS jumps from zero to high level, the voltage V generated across the sensing resistor Rs is... SENSENo current comparator is applied during the blanking time of several hundred ns; the voltage V generated across the detection resistor Rs is only detected after the blanking time of several hundred ns has ended. SENSE This is then added to the current comparator. This generates a spike voltage V across the sensing resistor Rs. SENSE This will prevent the current comparator from triggering incorrectly, and the output pulse from mistakenly turning off the main power MOSFET, thus causing the peak current IL of the output inductor to rise. PEAK It cannot be established; in other words, the output inductor current is out of control from the moment the gate voltage of the main power MOS jumps from zero to high level until the end of the blanking time of several hundred ns; at the end of the blanking time of several hundred ns, the output inductor current increases with the increase of the input voltage, and vice versa.

[0031] Typically, the peak current IL of the output inductor is controlled. PEAK A simple method is to adjust the corresponding current reference level V. REF To achieve this. However, due to the existence of a blanking circuit with a blanking time of several hundred ns, even if the current reference level V... REF The peak current IL of the output inductor is zero. PEAK The value is always greater than zero, and due to the fixed blanking time of several hundred ns, this minimum output inductor peak current IL PEAK The value changes with the input and output voltages.

[0032] This invention proposes to further extend the minimum output inductor peak current IL PEAK The value method, that is, at the current reference level V REF Once the value is zero, the blanking time will be controlled to achieve the desired result; that is, the peak current IL of the output inductor will be adjusted over a wide range. PEAK The value method is divided into two stages of control. The first stage involves adjusting the current reference level V. REF From the maximum value to zero, and during this period the blanking time is a fixed maximum value; secondly, when the current reference level V REF After reaching zero, maintain the current reference level V. REF The blanking time is adjusted from its fixed maximum value to its minimum value to make the peak current IL of the output inductor zero. PEAK The value decreased further.

[0033] Specifically, regarding the adjustment of the peak current IL of the output inductor... PEAK Regarding the value from the maximum to the minimum: firstly, by adjusting the current reference level V... REF The current decreases from its maximum value to zero, while the blanking time remains at a fixed maximum value during this period; when the current reference level V... REF After decreasing to zero, the current reference level V REF Keep it at zero, then adjust the blanking time, decreasing it from its fixed maximum value to its minimum value.

[0034] Specifically, regarding the adjustment of the peak current IL of the output inductor... PEAK Regarding the value from minimum to maximum: first, adjust the blanking time, that is, increase the blanking time from its minimum value to a fixed maximum value, while the current reference level V... REF Keep it at zero; after the blanking time reaches a fixed maximum value, adjust the current reference level V. REF The time increases from zero to the maximum value, while the blanking time remains at a fixed maximum value.

[0035] Current reference level V REF The blanking time can be adjusted based on the output dimming current and whether the switching frequency is greater than the audio frequency; when the output dimming current is greater than the predetermined current, if the current reference level V... REF When it is greater than zero, the current reference level V can be reduced. REF ; or if the current reference level V REF The current is already zero, which can reduce the blanking time and thus the actual output dimming current; when the corresponding switching frequency is less than the audio frequency, if the current reference level V... REF When it is greater than zero, the current reference level V can be further reduced. REF ; or if the current reference level V REF Since it's already zero, the blanking time can be further reduced to ensure the switching frequency is greater than the audio frequency.

[0036] The further extended minimum output inductor peak current IL given by the present invention PEAK The value method, i.e., the two-stage control method, can have multiple implementation circuit structures. In this specific embodiment, a two-stage control method using an N-bit digital reversible up / down counter and an N-bit analog-to-digital converter (DAC), or an M-bit digital reversible up / down counter and an M-bit analog-to-digital converter (DAC), is employed. The wide output current range control circuit is as follows: Figure 1 As shown.

[0037] The output of an N-bit reversible up / down counter is connected to the N-bit digital input of an N-bit analog-to-digital converter (DAC), and the output of an M-bit reversible up / down counter is connected to the M-bit digital input of an M-bit DAC. The output current reference level V of both the N-bit and M-bit DACs is also connected. REF Analog voltages are used to control the blanking time.

[0038] The N-bit reversible up / down counter and the M-bit reversible up / down counter each have their own up / down logic control terminal UPDN; that is, when UPDN is high, the N-bit and M-bit reversible up / down counters perform up counting in response to clock ck; when UPDN is low, the N-bit and M-bit reversible up / down counters perform down counting in response to clock ck.

[0039] Both N-bit and M-bit reversible up / down counters have their own clear and set terminals for setting their initial state. They also have all-zero or all-"1" output logic terminals to indicate whether the current counting state is all zeros or all "1s." N-bit and M-bit reversible up / down counters are common products on the market. Similarly, N-bit and M-bit analog-to-digital converters (DACs) are also common products on the market.

[0040] like Figure 1 As shown, the logic level UPDN is connected to the addition / subtraction logic control terminals UPDN of the N-bit reversible up / down counter and the M-bit reversible up / down counter, respectively; the clock signal Ck is connected to the clock input terminal ck of the N-bit reversible up / down counter and one input terminal of the AND gate, the all-zero output logic terminal of the N-bit reversible up / down counter is connected to the other input terminal of the AND gate, and the output terminal Ck1 of the AND gate is connected to the clock input terminal ck of the M-bit reversible up / down counter; the all-"1" output logic terminal of the M-bit reversible up / down counter is connected to the clear / set terminal of the N-bit reversible up / down counter via a logic inverter.

[0041] An N-bit reversible up / down counter outputs an analog voltage via an N-bit analog-to-digital converter (DAC) to generate a current reference level V. REF The M-bit digital reversible up-down counter outputs an analog voltage via an M-bit analog-to-digital converter (DAC) to adjust the blanking time.

[0042] Since N-bit or M-bit reversible up / down counters require a suitable clock frequency Ck for digital addition and subtraction, both have up / down logic control terminals UPDN to control whether the digital value increases or decreases. A corresponding N-bit analog-to-digital converter (DAC) is used to convert the digital output of the N-bit reversible up / down counter into a current reference level V. REF The analog quantity; the corresponding M-bit analog-to-digital converter (DAC) is used to convert the digital output of the M-bit reversible digital up / down counter into an analog quantity with blanking time. Clearly, when the logic level UPDN is high, as time progresses, i.e., the corresponding clock Ck count increases, the current reference level V... REF Analog quantity and blanking time: Analog quantity increases; similarly, when logic level UPDN is zero, as time progresses, i.e., the number of clock cycles Ck increases, the current reference level V... REFThe analog quantity and blanking time are reduced.

[0043] The reset / set input of an N-bit reversible up / down counter is used to reset the counter. When the reset / set input is high, the current reference level V is guaranteed. REF The N-bit reversible up-and-down counter also has an all-zero output logic terminal, which is used to make the all-zero output logic terminal high when the N-bit reversible up-and-down counter is all zero. The all-zero output logic terminal of the N-bit reversible up-and-down counter controls the AND gate. That is to say, when the N-bit reversible up-and-down counter is all zero and the all-zero output logic terminal is high, the M-bit reversible up-and-down counter will have the corresponding clock Ck1 enter the clock ck input terminal of the M-bit reversible up-and-down counter, and the M-bit reversible up-and-down counter can perform the corresponding reversible up-and-down counting according to the logic level UPDN.

[0044] For an M-bit reversible up / down counter, when the M-bit reversible up / down counter is all "1", the all "1" output logic terminal of the M-bit reversible up / down counter is at a high level, and the blanking time reaches a fixed maximum value; when the M-bit reversible up / down counter is not all "1", the all "1" output logic terminal is at a zero level; the all "1" output logic terminal of the M-bit reversible up / down counter is connected to the clear and set terminal of the N-bit reversible up / down counter via a logic inverter. That is to say, when the M-bit reversible up / down counter is not all "1", even if there is a clock Ck, the N-bit reversible up / down counter is in a cleared state; only when the M-bit reversible up / down counter is all "1" can the N-bit reversible up / down counter possibly perform the corresponding reversible up / down counting according to the UPDN logic level.

[0045] exist Figure 1 In the circuit shown, the corresponding logic level UPDN is zero. If the initial state of an N-bit reversible up / down counter or an M-bit reversible up / down counter is all "1", the blanking time remains at a fixed maximum time, while the current reference level V... REF Its maximum value decreases over time, that is, as the number of clock cycles Ck increases. When the digital value of the N-bit reversible up / down counter decreases from all "1"s to zero, that is, the current reference level V... REF When the analog quantity is zero, the output logic level is high due to all zeros, and the M-bit reversible up / down counter has a corresponding clock Ck1. The corresponding logic level UPDN remains zero. As time progresses, i.e., as the number of clock cycles Ck1 increases, the digital quantity of the M-bit reversible up / down counter decreases from all "1"s to zero, meaning the analog quantity reaches its minimum during the blanking time. When the digital quantity of the M-bit reversible up / down counter decreases from all "1"s, the output logic level is zero, which, via a logic inverter, continuously clears the N-bit reversible up / down counter to zero, corresponding to the output current reference level V.REF The analog quantity remains zero. Similarly, the logic level UPDN is at a "1" level. If the initial state of an N-bit reversible up / down counter or an M-bit reversible up / down counter is all "0", that is, the blanking time is the minimum blanking time, and the current reference level V... REF The output of the N-bit reversible up / down counter is all zero, resulting in a high logic level. The M-bit reversible up / down counter has a corresponding clock Ck1; this increases over time, i.e., as the number of clock cycles Ck1 increases. When the digital value of the M-bit reversible up / down counter increases from all "0"s to all "1", i.e., the blanking time analog value increases from its minimum value to a fixed maximum value; during this period, because the output is all "1"s, the logic level is high. This, via a logic inverter, sets the reset (clear) input of the N-bit reversible up / down counter to zero, ending the clearing process of the N-bit reversible up / down counter. The corresponding output current reference level V... REF The analog quantity remains zero. The corresponding logic level UPDN remains high. As time progresses, that is, as the number of clock cycles Ck increases, the digital quantity of the N-bit reversible up / down counter increases from all "0"s to all "1"s, i.e., the current reference level V... REF The analog quantity increases from zero to its maximum value. When the digital quantity of the N-bit reversible up / down counter is not all "0", the N-bit reversible up / down counter outputs a logic level of all zeros, causing the clock Ck1 of the M-bit reversible up / down counter to disappear, and the corresponding blanking time for the analog quantity remains at a fixed maximum time.

[0046] Obviously Figure 1 The circuit shown can achieve the control requirements of this invention: the logic control signal UPDN can control the current reference level V. REF The increase or decrease of the blanking time analog quantity. The frequency of the clock Ck only affects the current reference level V. REF And the slope of the analog quantity change during blanking time. The number of bits in an N-bit or M-bit reversible up / down counter only affects the reference level V. REF The size of the step size for the change in the analog quantity of the blanking time. The logic control signal UPDN can be generated through closed-loop adjustment; this closed-loop adjustment can generate the corresponding logic control signal UPDN based on the difference between the output dimming current and the predetermined output dimming current, and whether the switching frequency is greater than the audio frequency. How the logic control signal UPDN is generated is not discussed in this invention.

[0047] Finally, it should be noted that the above examples are merely some specific embodiments of the present invention. Obviously, the present invention is not limited to the above embodiments and many variations are possible. All variations that can be directly derived or conceived by those skilled in the art from the disclosure of the present invention should be considered within the scope of protection of the present invention.

Claims

1. A control method with a wide output current range: the time average value of the output inductor current of the LED driver power supply is determined by the peak output inductor current IL. PEAK The peak current IL of the output inductor is determined together with the switching period Ts of the output inductor. PEAK By adjusting the current reference level V REF The method is to achieve this, characterized by: The output inductor peak current IL PEAK The value is divided into two segments control: one is to adjust the current reference level V REF From the maximum to zero, and during this period of blanking time is fixed maximum; Secondly, when the current reference level V REF After reaching zero, maintain the current reference level V. REF The blanking time is adjusted from its fixed maximum value to its minimum value to make the peak current IL of the output inductor zero. PEAK The value decreased further.

2. The control method for a wide output current range according to claim 1, characterized in that: The current reference level V REF The adjustment of the blanking time is based on the magnitude of the output dimming current and whether the switching frequency is required to be higher than the audio frequency; when the output dimming current is greater than the predetermined current, if the current reference level V... REF When the value is greater than zero, the current reference level V is reduced. REF ; or if the current reference level V REF If the current is already zero, reduce the blanking time to reduce the actual output dimming current; when the corresponding switching frequency is less than the audio frequency, if the current reference level V... REF If the value is greater than zero, then the current reference level V is further reduced. REF ; or if the current reference level V REF If it is already zero, then further reduce the blanking time to ensure that the switching frequency is greater than the audio frequency.

3. The implementation circuit of the wide output current range control method as described in any one of claims 1-2, characterized in that: The output terminal of the N-bit reversible up / down counter is connected to the N-bit digital input terminal of the N-bit analog-to-digital converter (DAC), and the output terminal of the M-bit reversible up / down counter is connected to the M-bit digital input terminal of the M-bit DAC; the N-bit DAC outputs the current reference level V. REF The M-bit analog-to-digital converter (DAC) outputs an analog voltage to control the blanking time. The logic level UPDN is connected to the addition / subtraction logic control terminals UPDN of the N-bit reversible up / down counter and UPDN of the M-bit reversible up / down counter, respectively. The clock signal Ck is connected to the clock input terminal ck of the N-bit reversible up / down counter and one input terminal of the AND gate, respectively. The all-zero output logic terminal of the N-bit reversible up / down counter is connected to the other input terminal of the AND gate, and the output terminal Ck1 of the AND gate is connected to the clock input terminal ck of the M-bit reversible up / down counter. The all-"1" output logic terminal of the M-bit reversible up / down counter is connected to the clear / set terminal of the N-bit reversible up / down counter via a logic inverter.

4. The implementation circuit according to claim 3, characterized in that: When the logic level UPDN is high, the current reference level V increases with the number of corresponding clock cycles Ck. REF Analog quantity and blanking time: As the analog quantity increases, when the logic level UPDN is zero, the current reference level V increases with the number of corresponding clock cycles Ck. REF The analog quantity and blanking time are reduced.

5. The implementation circuit according to claim 4, characterized in that: When the reset / reset pin of the N-bit reversible up / down counter outputs a high level, the current reference level V is guaranteed. REF Reaching zero; When the N-bit digital reversible up-and-down counter is all zero, the all-zero output logic terminal outputs a high level, the logic AND gate is turned on, and the clock signal Ck enters the M-bit digital reversible up-and-down counter through the logic AND gate.

6. The implementation circuit according to claim 5, characterized in that: When the M-bit reversible up-and-down counter is all "1", the all "1" output logic terminal is high, and the blanking time reaches a fixed maximum value. When the M-bit reversible up-and-down counter is not all "1", the all "1" output logic terminal is zero. After passing through a logic inverter, it becomes a high level input to the clear and set terminal of the N-bit reversible up-and-down counter. Even with a clock Ck, the N-bit reversible up-and-down counter is in a cleared state until the M-bit reversible up-and-down counter is all "1". Then, the N-bit reversible up-and-down counter performs reversible up-and-down counting according to the UPDN logic level.

7. The implementation circuit according to claim 6, characterized in that: The logic level UPDN is zero. If the initial state of an N-bit reversible up / down counter or an M-bit reversible up / down counter is all "1", the blanking time remains at a fixed maximum time, while the current reference level V... REF The maximum value decreases as the number of clock cycles Ck increases; when the digital value of the N-bit reversible up / down counter decreases from all "1"s to zero, the current reference level V... REF The analog quantity is zero. Since the all-zero output logic terminal of the N-bit digital reversible up-down counter outputs a high level, the M-bit digital reversible up-down counter has an input clock Ck1. The corresponding logic level UPDN remains zero. As the clock Ck1 increments, the digital value of the M-bit reversible up / down counter decreases from all "1"s to zero, and the blanking time analog value reaches its minimum. When the digital value of the M-bit reversible up / down counter decreases from all "1"s, the all "1" output logic terminal of the M-bit reversible up / down counter outputs a zero level. This, via a logic inverter, continuously clears the N-bit reversible up / down counter to zero, corresponding to the output current reference level V. REF The analog quantity remains at zero.

8. The implementation circuit according to claim 7, characterized in that: When the logic level UPDN is high, if the initial state of an N-bit reversible up / down counter or an M-bit reversible up / down counter is all "0", the blanking time is the minimum blanking time, and the current reference level V... REF It is also zero; the all-zero output logic terminal of the N-bit reversible up / down counter outputs a high level, and the M-bit reversible up / down counter has an input clock Ck1; it increases with the number of clock cycles Ck1. When the digital value of the M-bit reversible up / down counter increases from all "0"s to all "1"s, the blanking time analog value increases from its minimum value to its fixed maximum value; during the period when the blanking time analog value increases from its minimum value to its fixed maximum value, the all-"1" output logic terminal of the M-bit reversible up / down counter outputs a high level, which, through a logic inverter, makes the reset input of the N-bit reversible up / down counter zero, ending the clearing of the N-bit reversible up / down counter, and the corresponding output current reference level V. REF The analog quantity remains zero; The corresponding logic level UPDN remains high. As the clock Ck count increases, the digital value of the N-bit reversible up / down counter increases from all "0"s to all "1"s. The current reference level V... REF The analog quantity increases from zero to the maximum value; when the digital quantity of the N-bit reversible up-down counter is not all "0", the all-zero output logic terminal of the N-bit reversible up-down counter outputs a zero level, causing the clock Ck1 of the M-bit reversible up-down counter to disappear, and the corresponding blanking time of the analog quantity remains at a fixed maximum time.

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