Memory, memory testing method, and electronic device

Abstract

The application discloses a memory, a memory testing method and an electronic device, and relates to the technical field of computer storage. The memory comprises a storage circuit and a testing circuit. The storage circuit is internally provided with a storage unit for storing data. The testing circuit is used for testing the storage unit in the storage circuit. The testing circuit can write first test data into a target storage unit in the storage circuit and read first data from the target storage unit in response to a start test instruction. The first data is compared with the first test data to obtain a first comparison result. The first comparison result is used for indicating whether the target storage unit is invalid. Since the testing circuit is internally arranged in the memory, when testing is performed, the memory can start the internal testing circuit to test the storage circuit as long as the start test instruction of the testing device is received, resource occupation of the testing device is reduced, and it is beneficial to simultaneously perform batch testing on multiple memories, and the testing efficiency is improved.

Description

Technical Field

[0001] This application relates to the field of computer storage technology, and in particular to a memory, a memory testing method, and an electronic device. Background Technology

[0002] Memory refers to storage devices used to store computer programs or data. Dynamic random access memory (DRAM) is a commonly used semiconductor memory device in computers. To meet the ever-increasing demands for capacity and other aspects, the size of memory cells in DRAM is becoming smaller and smaller. However, this also leads to an increase in the failure rate of these memory cells. Therefore, failure testing of the memory is necessary.

[0003] Currently, the method of executing test programs through the central processing unit (CPU) to issue read and write operations to the memory in order to locate the failed memory cells can only test multiple memory cells one by one, which is not conducive to batch testing and has very low testing efficiency. Summary of the Invention

[0004] This application provides a memory, a memory testing method, and an electronic device that can improve testing efficiency.

[0005] In a first aspect, embodiments of this application provide a memory that includes a storage circuit and a test circuit. The storage circuit contains storage units for storing data, and the test circuit is used to test the storage units within the storage circuit. Exemplarily, the test circuit, in response to a test start command, writes first test data to a target storage unit within the storage circuit. The target storage unit is contained within the storage unit. After writing the first test data, it reads first data from the target storage unit and compares the first data with the first test data to obtain a first comparison result. The first comparison result is used to indicate whether the target storage unit has failed.

[0006] By incorporating test circuitry within the memory, during testing, the memory only needs to receive a start test command from the test device to activate the internal test circuitry to test the memory cells, eliminating the need for the test device's CPU to execute the test program, thus reducing CPU resource consumption. The test device's CPU only needs to send the start test command, which facilitates simultaneous batch testing of multiple memory modules, improving testing efficiency.

[0007] In one possible implementation, the test circuit may include a packet sender and a comparator; the start test instruction may include a test address and first test data, the test address indicating the target memory cell. For example, the start test instruction may include multiple addresses, including the test address. The packet sender is used to determine the test address based on the multiple addresses in the start test instruction, and sends a write data command to the controller of the memory circuit based on the test address, wherein the write data command includes the first test data and the test address. The controller of the memory circuit is used to write the first test data to the target memory cell according to the write data command. The packet sender is also used to send a read data command to the controller of the memory circuit after completing the writing of the first test data, the read data command including the test address. The controller of the memory circuit is also used to read the first data from the target memory cell according to the test address. The comparator is used to compare the first data with the first test data to obtain a first comparison result.

[0008] Optionally, the data read command sent by the packet sender to the controller of the storage circuit may include the first test data in addition to the test address. The controller of the storage circuit is also used to send the first test data to the comparator, so that the comparator compares the first data with the first test data to obtain a first comparison result, so that the user can know the failure status of the storage cell in the storage circuit based on the first comparison result.

[0009] In one possible implementation, the packet sender stores multiple test templates for simulating different business scenarios. Upon receiving a test start command, the packet sender can sequentially invoke each test template and send write or read data commands to the controller of the storage circuit based on the invoked test template. By setting multiple test templates to simulate different business scenarios, the failure status of storage units within the storage circuit during the actual operation of various businesses can be obtained.

[0010] In one possible implementation, the memory further includes a test configuration interface, which is connected to both the packet sender and the comparator. The packet sender can receive a test start command through the test configuration interface, and the comparator can output a first comparison result through the test configuration interface. By providing an exposed test configuration interface on the memory, users can easily connect the memory to external test equipment for testing.

[0011] In one possible implementation, the memory may further include logic circuitry, which is stacked and electrically connected to the storage circuitry. The logic circuitry may include a data transmission interface for data transmission between the storage circuitry and an external device. Test circuitry may be located within the logic circuitry or within the storage circuitry. Optionally, if the storage circuitry includes multiple storage regions, multiple test circuitry may be provided in the logic circuitry. Each test circuitry corresponds to testing one storage region, and multiple test circuitry can simultaneously test different storage regions, further improving testing efficiency.

[0012] In one possible implementation, the aforementioned memory can also perform mutual testing with another memory. For ease of understanding, the aforementioned memory can be referred to as the first memory, and the other memory as the second memory. The first memory can transmit data with the second memory through a data transmission interface. The packet sender of the first memory is also used to respond to a mutual test command by sending a mutual test write command to the second memory through the data transmission interface. The mutual test write command is used to write second test data to a specified memory cell in the second memory. After completing the writing of the second test data, a mutual test read command is sent to the second memory through the data transmission interface. The mutual test read command is used to instruct the second memory to read the second data from the specified memory cell and transmit it to the comparator of the first memory through the data transmission interface. The comparator of the first memory is also used to compare the second data with the second test data to obtain a second comparison result. The second comparison result is used to indicate whether the data transmission interface of the memory has failed. Through mutual testing between the two memories, it is helpful to detect whether the data transmission interface of the memory has failed.

[0013] Secondly, embodiments of this application provide a memory testing method, wherein the memory includes a storage circuit and a test circuit, and the storage circuit includes a storage unit for storing data. The memory testing method may include: receiving a start test command; in response to the received start test command, writing first test data to a target storage unit in the storage circuit through the test circuit; wherein the target storage unit is contained within a storage unit of the storage circuit. After completing the writing of the test data, reading the first data from the target storage unit through the test circuit, and comparing the first data with the first test data through the test circuit to obtain a first comparison result; the first comparison result is used to indicate whether the target storage unit has failed.

[0014] In one possible implementation, the test initiation command includes a test address and first test data, the test address indicating the target storage cell. The test circuit includes a packet sender that, in response to the received test initiation command, can send a write data command to the controller of the storage circuit. The write data command includes the first test data and the test address, causing the controller of the storage circuit to write the first test data to the target storage cell according to the write data command.

[0015] In one possible implementation, the test circuit further includes a comparator; when reading first data from the target storage unit through the test circuit, a data read command can be sent to the controller of the storage circuit through a packet sender. The data read command includes a test address and first test data, so that the controller of the storage circuit sends the first test data and the first data read from the target storage unit according to the test address to the comparator; the first data and the first test data are compared by the comparator to obtain a first comparison result.

[0016] In one possible implementation, the aforementioned memory can also perform mutual testing with another memory. For ease of understanding, the aforementioned memory can be referred to as the first memory, and the other memory can be referred to as the second memory. The first memory transmits data with the second memory through a data transmission interface. In response to a mutual test command, the first memory sends a mutual test write command to the second memory through a test circuit and a data transmission interface. The mutual test write command is used to write second test data to a specified memory cell of the second memory. After completing the writing of the second test data, the first memory sends a mutual test read command to the second memory through a test circuit and a data transmission interface. The mutual test read command is used to instruct the second memory to read the second data from the specified memory cell. The first memory receives the second data sent by the second memory through the data transmission interface and compares the second data with the second test data through the test circuit to obtain a second comparison result. The second comparison result is used to indicate whether the data transmission interface has failed.

[0017] Thirdly, embodiments of this application provide an electronic device that may include a memory according to any of the embodiments of the first aspect.

[0018] The technical effects that can be achieved by the embodiments of the second aspect and the third aspect described above can be referred to the description of the beneficial effects of the embodiments of the first aspect described above, and will not be repeated here. Attached Figure Description

[0019] Figure 1 A schematic diagram of the structure of a memory provided in an embodiment of this application;

[0020] Figure 2 This is a schematic diagram of another memory structure provided in an embodiment of this application;

[0021] Figure 3 This is a schematic diagram of another memory structure provided in an embodiment of this application;

[0022] Figure 4 This is a schematic diagram of a connection structure between two memories provided in an embodiment of this application;

[0023] Figure 5 This is a schematic diagram illustrating another connection structure between two memories provided in an embodiment of this application;

[0024] Figure 6 This is a schematic diagram of another memory structure provided in an embodiment of this application;

[0025] Figure 7 This is a schematic diagram of another memory structure provided in an embodiment of this application;

[0026] Figure 8 This is a schematic diagram of another memory structure provided in an embodiment of this application;

[0027] Figure 9 This is a schematic diagram of the structure of a packet generator in a test circuit provided in an embodiment of this application;

[0028] Figure 10 A flowchart of a memory testing method provided in an embodiment of this application. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the embodiments of this application will be described in detail below with reference to the accompanying drawings. The terminology used in the implementation section of this application is only used to explain specific embodiments of this application and is not intended to limit this application. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0030] In this application embodiment, "multiple" refers to two or more. Therefore, in this application embodiment, "multiple" can also be understood as "at least two". "At least one" can be understood as one or more, such as one, two, or more. For example, "including at least one" means including one, two, or more, and it does not limit which ones are included. For example, including at least one of A, B, and C, then it could include A, B, C, A and B, A and C, B and C, or A and B and C. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / ", unless otherwise specified, generally indicates that the preceding and following related objects have an "or" relationship.

[0031] Unless otherwise stated, the ordinal numbers such as "first" and "second" mentioned in the embodiments of this application are used to distinguish multiple objects, and are not used to limit the order, sequence, priority or importance of multiple objects.

[0032] To facilitate batch testing and improve testing efficiency, this application provides a memory, which may be DRAM, a memory containing DRAM, or other types of memory. This application does not limit the specific type of memory.

[0033] The memory provided in this application embodiment can be applied to electronic devices, such as computer systems, servers, desktop computers, and laptops. Specifically, the memory in this application embodiment can be used as a cache in the aforementioned computer systems. Furthermore, the aforementioned electronic devices can also be mobile terminal products such as mobile phones; this application does not specifically limit the type of electronic device. The memory provided in this application embodiment can be specifically used to store data, and can perform data writing and reading.

[0034] Figure 1 The diagram shows a schematic representation of a memory provided in an embodiment of this application. Figure 1 As shown, the memory 100 in this embodiment includes a storage circuit 110 and a test circuit 120. The storage circuit 110 includes storage cells for storing data, and the test circuit 120 is used to test the storage cells in the storage circuit 110. The storage circuit 110 may be a DRAM chip, and the test circuit 120 may be located outside or inside the storage circuit 110.

[0035] In some embodiments, such as Figure 2As shown, the internal storage circuit 110 may include a storage cell array 111, which can be arranged in rows and columns, allowing storage cells to be addressed by specifying rows and columns. The storage cell array 111 can be connected to the controller 112 via word lines (WL) and bit lines (BL). A word line is a signal line required to select a row of storage cells in the storage cell array; working together with the bit lines, it can select one or more storage cells. The storage cell array 111 can be connected to a row address decoder via the word lines, and then connected to the controller 112 via the row address decoder. A bit line is a signal line required to select a column of storage cells in the storage array; working together with the word lines, it can select one or more storage cells. The storage cell array 111 can be connected to a column address decoder via the bit lines, and then connected to the controller 112 via the column address decoder. The controller 112 can be located inside or outside the storage circuit 110.

[0036] Each memory cell in the memory cell array 111 may include a capacitor and a transistor. The gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor. The voltage signal on the word line can control the transistor to turn on or off, thereby reading the data information stored in the capacitor through the bit line, or writing the data information into the capacitor for storage through the bit line.

[0037] The memory 100 may also include a data transmission interface 130. The memory 100 can be connected to an external computer or other electronic device through the data transmission interface 130. During use, the memory 100 receives a data storage instruction from the computer or other electronic device through the data transmission interface 130 and saves the data to be stored into the storage unit of the storage circuit 110. Alternatively, the memory 100 receives a data read instruction from the computer or other electronic device through the data transmission interface 130, reads the required data from the storage unit of the storage circuit 110, and returns the read data to the computer or other electronic device through the data transmission interface 130.

[0038] The test circuit 120 can respond to a test start command by writing first test data to the target storage cell in the storage circuit 110. After completing the writing of the first test data, it reads the first data from the target storage cell and compares the first data with the first test data to obtain a first comparison result. The first comparison result is used to indicate whether the target storage cell has failed. The target storage cell can be any storage cell in the storage circuit 110.

[0039] Because the memory has internal testing circuitry, during testing, the memory only needs to receive a start test command from the testing device to activate the internal testing circuitry to test the memory cells, without requiring the testing device's CPU to execute the test program, thus reducing CPU resource consumption. The testing device's CPU only needs to send the start test command, which facilitates parallel and batch testing of multiple memories simultaneously, improving testing efficiency.

[0040] In some embodiments, such as Figure 2 As shown, the test circuit 120 may include a packet sender 121 and a comparator 122. The test start command may include a test address and first test data, which can be input by the user through the test interface of the test device. For example, the user can set the range of test addresses, or the user can set the start address and test length of the test. The user can also input the first test data corresponding to each target storage unit to be tested. The packet sender 121 is used to send a write data command to the controller 112 of the storage circuit according to the test address and first test data in the test start command. The write data command instructs the controller of the storage circuit to write the first test data to the target storage unit. The target storage unit is determined according to the test address in the test start command. The controller 112 of the storage circuit can write the first test data to the target storage unit according to the write data command. The packet sender 121 can also be used to send a read data command to the controller 112 of the storage circuit after completing the writing of the first test data. The read data command instructs the controller 112 of the storage circuit to send the data read from the target storage unit to the comparator 122. The controller 112 of the storage circuit can also read first data from the target storage cell according to a read data command and send it to the comparator 122. Optionally, the read data command may also carry first test data to be written to the target storage cell, and the controller 112 of the storage circuit can also be used to send the first test data in the read data command to the comparator 122. The comparator 122 can also be used to compare the first data read from the target storage cell with the first test data to be written to the target storage cell to obtain a first comparison result.

[0041] In some embodiments, the user may not set a test address, that is, the test start command may not include a test address. After receiving the test start command, the test circuit 120 can test the entire space of the storage circuit, that is, the entire storage space. The user may also not set test data, that is, the test start command may not include test data. After receiving the test start command, the test circuit 120 can randomly generate corresponding test data for the target storage unit.

[0042] Optionally, the memory 100 may further include a test configuration interface 123, which is connected to the packet sender 121 and comparator 122 of the test circuit, respectively. Before testing the memory, the user can connect the test configuration interface 123 to an external test device, so that the packet sender 121 and comparator 122 can connect to the test device through the test configuration interface 123. The user can input configuration information such as the test address and first test data through the test interface of the test device, and send a start test command to the memory 100 through the test device. The packet sender 121 can receive the start test command sent by the test device through the test configuration interface 121, and the comparator 122 can output a first comparison result to the test device through the test configuration interface 123. The first comparison result is used to indicate whether the corresponding memory cell is faulty. The test device may include a display, which can be used to display the faulty memory cell. Exemplarily, the test configuration interface 123 may adopt an inter-integrated circuit (I2C) interface.

[0043] In other embodiments, such as Figure 3 As shown, the internal structure of the storage circuit 110 can be divided into multiple storage regions 113. Each storage region can be understood as a storage cell array with independent command and data interface buses. A storage region can also be called a channel. Each storage region corresponds to its own independent controller 112. Multiple test circuits 120 can be provided in the memory 100. Each test circuit 120 is connected to a controller 112 and is used to test the storage region 113 corresponding to that controller 112; that is, each test circuit 120 tests one storage region 113.

[0044] Multiple test circuits 120 may have their own corresponding test configuration interfaces, or they may share the same test configuration interface. When multiple test circuits 120 share the same test configuration interface, the test configuration interface receives a start test command from the test device and transmits the start test command to each test circuit 120. Each test circuit 120 compares the test address in the start test command with the storage address of its corresponding storage area. For any test circuit, if the test address in the start test command contains its corresponding storage address, it means that the test needs to test its corresponding storage area, and the test circuit executes the above test process to determine whether its corresponding storage area contains a failed storage cell; if the test address in the start test command does not contain its corresponding storage address, it means that the test does not need to test its corresponding storage area, and the test circuit does not need to execute the above test process.

[0045] During use, the controller 112 can receive access commands from external devices to the storage circuit 110 through the data transmission interface 130. During testing, the packet sender can simulate external devices to generate access commands to the storage circuit 110, namely the aforementioned write data command and read data command, thereby simulating the process of accessing the storage circuit in actual use scenarios.

[0046] Optionally, the memory provided in this application embodiment can also perform mutual testing with another memory. Exemplarily, in some optional embodiments, such as... Figure 4 As shown, memory 100 can be referred to as the first memory, and memory 200 can be referred to as the second memory. The first memory transmits data to the second memory through a data transmission interface. Memory 100 includes a data transmission interface 130, and memory 200 includes a data transmission interface 230. Both data transmission interfaces 130 and 230 can be Sonic Input / Output (SIO) interfaces. In one embodiment, the data transmission interface 130 of memory 100 is connected to the data transmission interface 230 of memory 200, enabling memory 100 and memory 200 to be interconnected and transmit data. In another embodiment, the data transmission interface 130 of memory 100 and the data transmission interface 230 of memory 200 can be connected via a data cable or a data bus, enabling memory 100 and memory 200 to be interconnected and transmit data.

[0047] After the data transmission interface 130 is connected to the data transmission interface 230 of the memory 200, the packet sender 121 in the test circuit 120 can be connected to the storage circuit 210 in the memory 200 through the data transmission interface to access the storage cells in the storage circuit 210. The comparator 122 in the test circuit 120 can be connected to the storage circuit 210 in the memory 200 through the data transmission interface to receive the data returned by the storage circuit 210, thereby completing the test of the storage circuit 210. Similarly, the packet sender 221 in the test circuit 220 can be connected to the storage circuit 110 in the memory 100 through the data transmission interface to access the storage cells in the storage circuit 110. The comparator 222 in the test circuit 220 can be connected to the storage circuit 110 in the memory 100 through the data transmission interface to receive the data returned by the storage circuit 110, thereby completing the test of the storage circuit 110.

[0048] After the memory 100 and the memory 200 are connected, the packet sender 121 can also be used to respond to the mutual test command by sending a mutual test write command to the memory 200 through the data transmission interface. The mutual test write command is used to write second test data to a specified storage cell in the memory 200. After the second test data is written, a mutual test read command is sent to the memory 200 through the data transmission interface. The mutual test read command is used to instruct the memory 200 to read the second data from the specified storage cell and transmit it to the comparator 122 through the data transmission interface. The comparator 122 can also be used to compare the second data with the second test data to obtain a second comparison result. The second comparison result is used to indicate whether the data transmission interface has failed.

[0049] Taking the execution of test instructions by the test circuit 120 of memory 100 as an example, the test circuit 120 includes a packet sender 121 and a comparator 122. The packet sender 121 can receive test instructions through the test configuration interface 123. The test instructions may include test identification information, which may occupy one or more flag bits. For example, in one embodiment, the test identification information may occupy one flag bit. If the flag bit is "0", it indicates that the test instruction is a start test instruction, and the packet sender 121 performs self-test based on the start test instruction; if the flag bit is "1", it indicates that the test instruction is a mutual test instruction, and the packet sender 121 tests the storage circuit 210 in memory 200 based on the mutual test instruction. In another embodiment, the test identification information can be the identification information of the memory. If the test identification information is the identification information of the memory 100, it indicates that the test instruction is a start test instruction, and the packet sender 121 performs self-test based on the start test instruction. If the test identification information is the identification information of the memory 200, it indicates that the test instruction is a mutual test instruction, and the packet sender 121 tests the storage circuit 210 in the memory 200 based on the mutual test instruction.

[0050] If the test command received by packet sender 121 through test configuration interface 123 is a test start command, packet sender 121 writes first test data to the target storage cell in storage circuit 110 via the connection line between packet sender 121 and storage circuit 110. After completing the writing of the first test data, packet sender 121 sends a read data command to storage circuit 110, instructing storage circuit 110 to read the first data from the target storage cell. Storage circuit 110 may be equipped with a controller, which can execute the read data command to read the first data from the target storage cell. Storage circuit 110 sends the first test data carried in the read data command and the first data read from the target storage cell to comparator 122 via the connection line between storage circuit 110 and comparator 122. Comparator 122 compares the first data with the first test data to obtain a first comparison result.

[0051] If the test command received by packet sender 121 through test configuration interface 123 is a mutual test command, packet sender 121 writes second test data to a designated storage cell in storage circuit 210 via the connection line between packet sender 121 and storage circuit 210. After completing the writing of the second test data, packet sender 121 a read data command to storage circuit 210, instructing storage circuit 210 to read the second data from the designated storage cell. Storage circuit 210 may be equipped with a controller, which can execute the read data command to read the second data from the designated storage cell. Storage circuit 210 sends the second test data carried in the read data command and the second data read from the designated storage cell to comparator 122 via the connection line between storage circuit 210 and comparator 122. Comparator 122 compares the second data with the second test data to obtain a second comparison result.

[0052] In some other alternative embodiments, such as Figure 5 As shown, the test circuit 120 within the memory 100 may further include a first connector 124 and a second connector 125. The first input port of the first connector 124 is connected to the packet sender 121, and the second input port of the first connector 124 is connected to the packet sender 221 within the memory 200 via a data transmission interface. The output port of the first connector 124 is connected to the storage circuit 110 within the memory 100; both the first and second input ports of the first connector 124 are connected to the output port. The first input port of the second connector 125 is connected to the storage circuit 110 within the memory 100, and the second input port of the second connector 125 is connected to the storage circuit 210 within the memory 200 via a data transmission interface. The output port of the second connector 125 is connected to the comparator 122 within the memory 100; both the first and second input ports of the second connector 125 are connected to the output port.

[0053] The test circuit 220 within the memory 200 may further include a first connector 224 and a second connector 225. The first input port of the first connector 224 is connected to the packet sender 221, and the second input port of the first connector 224 is connected to the packet sender 121 within the memory 100 via a data transmission interface. The output port of the first connector 224 is connected to the storage circuit 210 within the memory 200; both the first and second input ports of the first connector 224 are connected to the output port. The first input port of the second connector 225 is connected to the storage circuit 210 within the memory 200, and the second input port of the second connector 225 is connected to the storage circuit 110 within the memory 100 via a data transmission interface. The output port of the second connector 225 is connected to the comparator 222 within the memory 200; both the first and second input ports of the second connector 225 are connected to the output port.

[0054] If the test command received by packet sender 121 through test configuration interface 123 is a test start command, packet sender 121 writes first test data to the target storage cell in storage circuit 110 through the first input port and output port of first connector 124. After completing the writing of the first test data, packet sender 121 sends a read data command to storage circuit 110 through the first input port and output port of first connector 124, instructing storage circuit 110 to read the first data from the target storage cell. Storage circuit 110 may be equipped with a controller, which can execute the read data command to read the first data from the target storage cell. Storage circuit 110 sends the first test data carried in the read data command and the first data read from the target storage cell to comparator 122 through the first input port and output port of second connector 125. Comparator 122 compares the first data with the first test data to obtain a first comparison result.

[0055] If the test command received by packet sender 121 through test configuration interface 123 is a mutual test command, packet sender 121 writes second test data to a designated storage unit in storage circuit 210 through data transmission interface and the second input and output ports of first connector 224. After completing the writing of the second test data, packet sender 121 sends a read data command to storage circuit 210 through data transmission interface and the second input and output ports of first connector 224, instructing storage circuit 210 to read the second data from the designated storage unit. Storage circuit 210 may be equipped with a controller, which can execute the read data command to read the second data from the designated storage unit. Storage circuit 210 sends the second test data carried in the read data command and the second data read from the designated storage unit to comparator 122 through data transmission interface and the first input and output ports of second connector 225. Comparator 122 compares the second data with the second test data to obtain a second comparison result.

[0056] Similarly, the test circuit 220 of memory 200 can be used to test the storage circuit 210 of memory 200, and can also be used to test the storage circuit 110 of memory 100. The process by which the test circuit 220 of memory 200 executes the test instructions received through the test configuration interface 223 is similar to the process by which the test circuit 120 executes the test instructions, and will not be described again here.

[0057] If the storage circuit 210 of the memory 200 is tested using test circuit 220, and the test result shows that all storage cells in storage circuit 210 are normal, but when the storage circuit 210 of the memory 200 is tested using test circuit 120, the test result shows that there are failed storage cells in storage circuit 210. In this case, it can be inferred that the data transmission interface 130 may be faulty. Therefore, the cross-test result, i.e., the second comparison result, can be used to indicate whether the data transmission interface is faulty. To further determine whether the data transmission interface 130 is indeed faulty, it can be verified through multiple cross-tests with multiple different memories.

[0058] Figure 6 and Figure 7 A schematic diagram of another memory structure provided in an embodiment of this application is shown, as follows: Figure 6 and Figure 7 As shown, the memory 300 in this embodiment may include a plurality of storage circuits 310 and logic circuits 330. Figure 6 The memory 300 shown includes four memory circuits 310. In other embodiments, the number of memory circuits may be more or less, and this application does not limit this.

[0059] exist Figure 6 In the memory 300 shown, the logic circuit 330 is located at the bottom layer, and four storage circuits 310 are arranged layer by layer above the logic circuit 330, which can be referred to as a stacked storage circuit 310 and logic circuit 330. Each layer of storage circuit 310 is electrically connected to the logic circuit 330, and the circuits in each layer can be interconnected vertically through through-silicon vias (TSVs). The storage circuit 310 can be referred to as a DRAM die, and the logic circuit 330 can be referred to as a logic base die or a base die. The DRAM die includes storage cells for storing data. The base die contains a controller and a data transmission interface for connecting external devices. The data transmission interface is used for data transmission between the storage circuit 310 and external devices. When the data transmission interface receives an access request from an external device to access a storage cell in the DRAM die, the base die can write data to or read data from the storage cell in the DRAM die through the controller. The memory formed by the stacked base die and multiple DRAM dies can be called high bandwidth memory (HBM).

[0060] The memory provided in this application embodiment may be an HBM. In some embodiments, the test circuit 320 may be disposed in the logic circuit 330 for testing the memory cells in the memory circuit 310 to locate and analyze failed memory cells; this process can be called self-testing. When the memory 300 is connected to another memory through a data transmission interface, the test circuit 320 can also test the memory cells in the other memory; this process can be called mutual testing. The process of mutual testing between two memories has been described above and will not be repeated here. In other embodiments, the test circuit 320 may also be disposed in any one of the memory circuits 310.

[0061] It should be noted that, in order to distinguish the test data used during self-testing and mutual testing of the memory, this embodiment refers to the test data used during self-testing as first test data and the test data used during mutual testing as second test data. The first test data and the second test data may be the same or different. Similarly, this embodiment refers to the data read from the memory cell during self-testing as first data and the data read from the memory cell during mutual testing as second data.

[0062] The internal structure of test circuit 320 is the same as that of test circuit 120, both of which can include a packet sender and a comparator. For example... Figure 8 As shown, the test circuit 320 is housed within the logic circuit 330. The logic circuit 330 also includes a test configuration interface 323, a controller 312, and a data transmission interface 330. The test configuration interface 323 is connected to the packet sender 321 and comparator 322 of the test circuit 320, respectively. The packet sender 321 and comparator 322 are connected to the controller 312. The controller 312 can be connected to each layer of storage circuits 310 via a TSV interface, and it can also be connected to the data transmission interface 330.

[0063] For example, when the memory 300 includes four memory circuits 310, the logic circuit 330 can be equipped with four controllers 312, each controller 312 being used to access one memory circuit. A test circuit 320 can be provided, or it can be provided independently for each memory circuit, i.e., four test circuits 320 can be provided. When each memory circuit 310 includes multiple memory regions, the logic circuit 330 can be equipped with one controller 312 and one test circuit 320 corresponding to one memory region, i.e., the logic circuit 330 can have multiple test circuits 320, each test circuit 320 corresponding to one memory region.

[0064] The packet sender 321 can receive a start test command through the test configuration interface 323, write the first test data to the storage circuit 310 through the controller 312, or read the first data from the storage circuit 310. The comparator 322 is used to compare the first data with the first test data to obtain the first comparison result, and output the first comparison result through the test configuration interface 323.

[0065] Optionally, to test the failure status of storage units within the storage circuit under different business scenarios, multiple test templates can be set up to simulate different business scenarios. For example, the packet sender stores multiple test templates. After receiving a test start command, the packet sender sequentially calls each test template, generating corresponding write or read data commands based on the test templates to simulate different business scenarios and test the storage units in the storage circuit. By setting up multiple test modules to simulate different business scenarios, failure scenarios can be easily reproduced, helping to detect the failure status of storage units within the storage circuit during actual business operation under different business scenarios.

[0066] In some embodiments, such as Figure 9 As shown, the structure of the packet sender 321 may include an arbitration unit 3211, an address generation unit 3212, and a command generation unit 3213. The arbitration unit 3211 may have multiple registers, each storing a test template. For example, each test template may include the following contents as shown in Table 1:

[0067] Table 1

[0068] Bit width 1 3 5 3 1 13 6 19 1

[0069] In this context, the field segment represents the meaning or function of different bits in the test template, and the bit width represents the number of bits occupied by the corresponding field segment.

[0070] vld indicates whether the test template is valid, with 1 indicating valid and 0 indicating invalid;

[0071] req_size indicates the length of read and write data supported by this test template. The value is an integer multiple of 32B, with a maximum of 128B.

[0072] cmd_type indicates the type of test command issued, which can support read data commands, write data commands, specified number summation commands, and matrix calculation commands. Among them, specified number summation commands and matrix calculation commands are special commands, which are set for memory with on-chip computing capabilities that can perform summation and matrix calculations. For memory that cannot perform summation and matrix calculations, specified number summation commands and matrix calculation commands can be omitted.

[0073] pri indicates the priority of supported configuration commands, with 0 being the highest priority and 7 being the lowest priority;

[0074] rdex, ra, ca: correspond to the redundant row address, row address, and column address respectively. The combination of the three constitutes the starting address of the test.

[0075] inb_addr represents the range of supported configuration address changes. Combined with the starting address of the test, the maximum access address can be obtained, that is, the ending address of the test is: {rdex,ra,ca}+inb_addr;

[0076] ad_inc represents the address increment, also known as the step size, and is used to calculate the test address corresponding to each command.

[0077] When testing the memory, the user can configure the contents of each test template. For example, the user can set some test templates to be valid while others are invalid. The user can also set the test address range for each valid test template, such as the start address and address variation range, or the start and end addresses, and whether to perform tests according to a set step size or random testing. If the test step size `ad_inc` is not configured, or if `ad_inc` is set to a specified value, the test circuit can perform random testing within the test address range. The test device sends a start test command to the memory based on the information configured by the user for each test template.

[0078] In some embodiments, the packet sender 321 receives a test start instruction through the test configuration interface 323. The test start instruction may include validity information of each test template, test address information corresponding to each test template, and first test data. The test address information may be represented by a test address range. The arbitration unit 3211 is used to enable the registers corresponding to each valid test template sequentially through an enable signal according to the validity information of each test template and the corresponding test address information in the test start instruction, and then sequentially call the valid test templates. Based on the called test template, the type of command to be sent is determined. The command type may include a write data command or a read data command. The arbitration unit 3211 is also used to send the test address information corresponding to the test template to the address generation unit 3212, and to send the command type and first test data to the command generation unit 3213. The command type indicates whether a write data command or a read data command is to be generated. The address generation unit 3212 is used to determine the address of the target storage unit according to the received test address information, generate a test address, and send the generated test address to the command generation unit 3213. The command generation unit 3213 is used to send a write data command or a read data command to the controller 312 of the storage circuit 310 based on the received test address, command type and first test data.

[0079] In other embodiments, after receiving the start test command through the test configuration interface 323, the packet sender 321 assumes that all test templates are valid and can call each test template in sequence, and send a write data command or a read data command to the controller 312 of the storage circuit 310 based on the called test template.

[0080] Because the test template supports random testing within a test address range, it can simulate the operation of memory during business execution, identify memory failures during business execution, and help determine the causes of memory failures. Furthermore, the test template also supports testing commands such as specified number addition and matrix calculation commands, enabling more comprehensive testing of memory with on-chip computing capabilities.

[0081] In some embodiments, when configuring test information such as the test address, the user can also configure bandwidth information. That is, the start test command can include bandwidth information. The packet sender can control the frequency of generating write or read data commands based on the bandwidth information in the start test command to perform read / write stress tests on the storage circuit. The higher the read / write frequency per unit time and the larger the bandwidth, the more likely it is that the storage cells in the storage circuit will fail. Through read / write stress testing, the maximum access bandwidth that the memory can withstand during actual use can be determined.

[0082] In other embodiments, assuming that the arbitration unit 3211 has only one test template, the packet sender 321 receives a test start instruction through the test configuration interface 323. The test start instruction may include test address information and first test data. The test address information may include multiple test addresses, or it may include the start address of the test and the address length or end address of the test. The arbitration unit 3211 is used to determine the type of command to be sent based on the test template according to the test address information in the test start instruction. The command type may include a write data command or a read data command. The arbitration unit 3211 is also used to send the test address information to the address generation unit 3212 and to send the command type and first test data to the command generation unit 3213, wherein the command type indicates whether a write data command or a read data command is to be generated. The address generation unit 3212 is used to determine the address of the target storage unit according to the received test address information, generate a test address, and send the generated test address to the command generation unit 3213. The command generation unit 3213 is used to send a write data command or a read data command to the controller 312 of the storage circuit 310 based on the received test address, command type and first test data.

[0083] In other embodiments, the packet sender 321 may also be implemented using a field-programmable gate array (FPGA) chip or a micro control unit (MCU) chip. The FPGA chip or MCU chip can send a write data command or a read data command to the controller 312 of the storage circuit 310 according to the test address and the first test data in the received start test instruction.

[0084] In some embodiments, after the packet sender 321 sends a read data command to the controller 312 of the storage circuit 310, the controller 312 reads the first data from the target storage unit according to the test address in the read data command, and sends the first test data carried in the read data command and the first data read from the target storage unit to the comparator 322. The comparator 322 compares the first data read from the target storage unit with the first test data written to the target storage unit to obtain a first comparison result, and outputs the first comparison result through the test configuration interface 323.

[0085] In other embodiments, the comparator 322 may also include a calculation unit. When the packet sender 321 sends a specified number summation command or a matrix calculation command to the controller 312 of the storage circuit 310, the comparator 322 receives the first data, performs the opposite calculation to the specified number summation command or matrix calculation command through the calculation unit, restores the first data, compares it with the first test data, obtains the first comparison result, and outputs the first comparison result through the test configuration interface 323 to determine whether the on-chip calculation function of the storage circuit has failed.

[0086] Figures 6 to 8 The test circuit in the memory shown can also be used Figure 4 or Figure 5 The connection shown connects to another memory and executes mutual test instructions. The process of executing mutual test instructions is the same as the process described above, and will not be repeated here.

[0087] The memory provided in this application embodiment can also be used in storage-intensive application systems, such as supercomputer systems for scientific computing (including high-energy physics and aerospace technology), precision control, and information management. Since existing memory systems do not provide testing functions to users, in storage-intensive application systems, if a memory fails, users cannot test the memory in a timely manner to determine the cause of the failure, which may seriously affect the normal operation of the application system. However, using the memory provided in this application embodiment, users can connect multiple memory systems in the application system to a testing device in a timely manner. The testing device can then send start test commands to each memory separately. Through batch testing, the failure location and cause of the failure can be quickly located. Compared with testing each memory individually, the testing efficiency and convenience are greatly improved.

[0088] Based on the same inventive concept as the above embodiments, this application also provides an electronic device that includes the memory provided in any of the above embodiments. This electronic device can be a computer system, such as a server, desktop computer, laptop computer, or the supercomputer system described above. The electronic device can also be a mobile terminal product such as a mobile phone.

[0089] Based on the same inventive concept as the above embodiments, this application also provides a memory testing method. For example... Figure 10 As shown, the memory testing method may include the following steps:

[0090] S1001, Receive the start test command.

[0091] S1002, in response to the received start test command, writes the first test data to the target storage cell in the storage circuit through the test circuit.

[0092] The memory includes a storage circuit, a test circuit, and a test configuration interface. The storage circuit includes storage cells for storing data. Before testing the memory, the user can connect the test configuration interface to an external test device and send a start test command to the memory through the test device. In response to the received start test command, the memory writes first test data to the target storage cell in the storage circuit through the test circuit, wherein the target storage cell is contained within the storage cells of the storage circuit.

[0093] In some optional embodiments, the user can input configuration information such as the test address and first test data through the test interface of the test device, and send a start test command to the memory through the test device. The start test command includes the test address and the first test data, and the test address is used to indicate the target storage unit.

[0094] The test circuit may include a packet sender. In response to a received start test command, the memory can send a write data command to the controller of the memory circuit through the packet sender. The write data command includes first test data and a test address, so that the controller of the memory circuit writes the first test data to the target memory cell according to the write data command.

[0095] S1003: After completing the writing of test data, the first data is read from the target storage unit through the test circuit.

[0096] The test circuit may also include a comparator. After the test data is written, a read data command can be sent to the controller of the storage circuit through the packet sender in the test circuit. The read data command may include a test address and first test data, so that the controller of the storage circuit sends the first test data and the first data read from the target storage cell according to the test address to the comparator.

[0097] In some embodiments, the packet sender stores multiple test templates for simulating different business scenarios. Upon receiving a test start command, the packet sender can sequentially invoke each test template and send write data commands or read data commands to the controller of the storage circuit based on the invoked test template.

[0098] S1004, the first comparison result is obtained by comparing the first data with the first test data through the test circuit.

[0099] A comparator can be used to compare the first data with the first test data to obtain a first comparison result. This first comparison result indicates whether the target memory cell has failed.

[0100] In one possible implementation, the aforementioned memory can also perform mutual testing with another memory. For ease of understanding, the aforementioned memory can be referred to as the first memory, and the other memory as the second memory. The first memory transmits data with the second memory through a data transmission interface. In response to a mutual test command, the first memory sends a mutual test write command to the second memory through a test circuit and a data transmission interface. The mutual test write command is used to write second test data to a specified memory cell in the second memory. After completing the writing of the second test data, the first memory sends a mutual test read command to the second memory through the test circuit and the data transmission interface. The mutual test read command is used to instruct the second memory to read the second data from the specified memory cell. The first memory receives the second data sent by the second memory through the data transmission interface and compares the second data with the second test data through the test circuit to obtain a second comparison result. The second comparison result is used to indicate whether the data transmission interface has failed. Mutual testing between the two memories can help detect whether the memory's data transmission interface has failed.

[0101] Those skilled in the art will understand that the embodiments of this application may take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. In the various embodiments of this application, unless otherwise specified or logically conflicting, the terminology and / or descriptions between different embodiments are consistent and can be referenced mutually. Technical features in different embodiments can be combined to form new embodiments based on their inherent logical relationships. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, such as including a series of steps or units. A method, system, product, or device is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or devices.

[0102] Although this application has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made therein without departing from the spirit and scope of this application. Accordingly, this specification and drawings are merely illustrative examples of the solutions defined by the appended claims and are to be considered as covering any and all modifications, variations, combinations, or equivalents within the scope of this application.

[0103] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the scope of this application. Therefore, if these modifications and variations of the embodiments of this application fall within the scope of the claims of this application and their equivalents, this application also intends to include these modifications and variations.

Claims

1. A memory, characterized in that, The memory includes a storage circuit and a test circuit; the storage circuit includes a storage unit for storing data. The test circuit is used for: In response to a test start command, first test data is written to a target storage cell in the storage circuit; the target storage cell is contained within the storage cell. After writing the first test data, the first data is read from the target storage unit; The first data is compared with the first test data to obtain a first comparison result; the first comparison result is used to indicate whether the target storage unit has failed. The memory is a first memory; the first memory transmits data with the second memory through a data transmission interface; the test circuit is also used for: In response to a mutual test command, a mutual test write command is sent to the second memory through the data transmission interface. The mutual test write command is used to write second test data to a specified storage cell of the second memory. After the second test data is written, a mutual test read command is sent to the second memory through the data transmission interface. The mutual test read command is used to instruct the second memory to read the second data from the specified storage cell. The second data sent by the second memory is received through the data transmission interface, and the second data is compared with the second test data to obtain a second comparison result. The second comparison result is used to indicate whether the data transmission interface has failed.

2. The memory according to claim 1, characterized in that, The test start instruction includes a test address and the first test data, wherein the test address is used to indicate the target storage unit; the test circuit includes a packet sender and a comparator. The packet sender is used to send a write data command to the controller of the storage circuit, the write data command including the first test data and the test address; The controller of the storage circuit is used to write the first test data into the target storage unit according to the write data command; The packet sender is also used to send a read data command to the controller of the storage circuit after completing the writing of the first test data, the read data command including the test address; The controller of the storage circuit is also configured to read the first data from the target storage unit according to the test address; The comparator is used to compare the first data with the first test data to obtain the first comparison result.

3. The memory according to claim 2, characterized in that, The data reading command also carries the first test data; The controller of the storage circuit is also used to send the first test data to the comparator.

4. The memory according to claim 2 or 3, characterized in that, The packet sender contains multiple test templates for simulating different business scenarios; The packet sender is specifically used to sequentially call each test template and send the write data command or the read data command to the controller of the storage circuit based on the called test template.

5. The memory according to claim 2 or 3, characterized in that, The memory also includes a test configuration interface, which is connected to the packet sender and the comparator respectively. The packet sender is specifically used to receive a test start command through the test configuration interface; The comparator is also used to output the first comparison result through the test configuration interface.

6. The memory according to any one of claims 1 to 3, characterized in that, The memory also includes logic circuitry, which is stacked and electrically connected to the memory circuitry. The logic circuitry includes a data transmission interface for data transmission between the memory circuitry and an external device. The test circuitry is located within the logic circuitry.

7. The memory according to claim 6, characterized in that, The storage circuit includes multiple storage areas, and the logic circuit is equipped with multiple test circuits, each test circuit corresponding to test one storage area.

8. A memory testing method, characterized in that, The memory includes a storage circuit and a test circuit; The storage circuit includes a storage unit for storing data; the method includes: Receive the command to start the test; In response to a received start test command, first test data is written to a target storage unit in the storage circuit through the test circuit; the target storage unit is contained within the storage unit. After the test data is written, the first data is read from the target storage unit through the test circuit; The test circuit compares the first data with the first test data to obtain a first comparison result; the first comparison result is used to indicate whether the target storage unit has failed. The memory is a first memory; the first memory transmits data with the second memory through a data transmission interface; the method further includes: In response to a mutual test command, a mutual test write command is sent to the second memory through the test circuit and the data transmission interface. The mutual test write command is used to write second test data to a specified storage cell of the second memory. After the second test data is written, a mutual test read command is sent to the second memory through the test circuit and the data transmission interface. The mutual test read command is used to instruct the second memory to read the second data from the specified storage unit. The second data sent by the second memory is received through the data transmission interface, and the second data is compared with the second test data through the test circuit to obtain a second comparison result. The second comparison result is used to indicate whether the data transmission interface is faulty.

9. The method according to claim 8, characterized in that, The start test instruction includes a test address and the first test data, wherein the test address is used to indicate the target storage unit; the test circuit includes a packet sender; the step of writing the first test data to the target storage unit in the storage circuit through the test circuit in response to the received start test instruction includes: The packet sender sends a write data command to the controller of the storage circuit. The write data command includes the first test data and the test address, so that the controller of the storage circuit writes the first test data to the target storage cell according to the write data command.

10. The method according to claim 9, characterized in that, The test circuit further includes a comparator; reading the first data from the target storage unit through the test circuit includes: The packet sender sends a read data command to the controller of the storage circuit. The read data command includes the test address and the first test data, so that the controller of the storage circuit sends the first test data to the comparator, as well as the first data read from the target storage cell according to the test address. The step of comparing the first data with the first test data through the test circuit to obtain the first comparison result includes: The first data is compared with the first test data by the comparator to obtain the first comparison result.

11. An electronic device, characterized in that, Includes the memory as described in any one of claims 1 to 7.

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