Tsv formation method for advanced packaging

Abstract

The present disclosure relates to via structures with interconnect dielectric shields for advanced wafer-level semiconductor packages. The methods described herein enable the formation of high thickness dielectric shield layers within low aspect ratio via structures, thereby facilitating thin and small form factor package structures with high 1I / O density and improved bandwidth and power.

Description

[0001] background

[0002] field

[0003] The embodiments described herein generally relate to shielded through-via structures and methods for forming them for advanced wafer-level semiconductor packaging. Background Technology

[0004] The ongoing trend in semiconductor device technology has led to the integration of semiconductor components into circuits with reduced size and increased density. Driven by the need for continuously miniaturizing semiconductor devices while simultaneously improving performance and functionality, these integrated circuits are fabricated into sophisticated 3D semiconductor packages. These packages facilitate a significant reduction in overall device footprint and enable shorter, faster connections between components. Such packages can integrate, for example, semiconductor chips and multiple other electronic components for mounting onto the circuit boards of electronic devices.

[0005] Therefore, the aforementioned trends and demands have driven the need for improved interconnect dielectric shielding (i.e., interconnect components or interconnect structures) that enables the assembly of semiconductor components and integrated circuits into such complex 3D packages. Vertical interconnect vias (or "vias") are well-known examples of interconnects. However, as circuit density increases and via sizes decrease, the thickness of the dielectric shielding layer formed around the vias also decreases, largely due to limitations associated with depositing dielectric material within the vias vias through chemical vapor deposition (CVD) or atomic layer deposition (ALD). Reduced dielectric shielding thickness can lead to increased leakage current, which in turn reduces the performance capabilities of the packaged device.

[0006] Therefore, there is a need in the art for improved methods of forming shielded via structures for advanced wafer-level semiconductor packaging. Summary of the Invention

[0007] This disclosure generally relates to shielded via structures for advanced wafer-level semiconductor packaging and methods for forming the same.

[0008] In some embodiments, a method for forming a through-silicon via (TSV) structure is provided. The method includes: forming a trench in a first side of a silicon substrate such that the trench surrounds a portion of the silicon substrate; filling the trench with a dielectric material; removing the portion of the silicon substrate surrounded by the trench to expose an inner surface of the dielectric material; depositing a conductive material on the inner surface of the dielectric material; and grinding or polishing the silicon substrate on the first side and a second side opposite to the first side. Grinding or polishing exposes the conductive and dielectric materials on the first and second sides.

[0009] In some embodiments, a method for forming a through-silicon via (TSV) structure is provided. The method includes: forming a trench in a first side of a silicon substrate such that the trench surrounds a portion of the silicon substrate; laminating a dielectric film on the first side of the silicon substrate such that the dielectric material of the dielectric film fills the trench; grinding or polishing the first side of the silicon substrate to remove the dielectric film outside the trench; removing the portion of the silicon substrate surrounded by the trench to form an aperture exposing an inner surface of the dielectric material; depositing a conductive material on the first side of the silicon substrate such that the conductive material extends through the aperture; and grinding or polishing the silicon substrate on the first side and a second side opposite to the first side. The grinding or polishing removes the conductive material disposed outside the aperture and exposes the conductive and dielectric materials on the first and second sides.

[0010] In some embodiments, a method for forming a through-silicon via (TSV) structure is provided. The method includes: forming a trench in a first side of a silicon substrate such that the trench surrounds a portion of the silicon substrate; laminating a dielectric film on the first side of the silicon substrate such that the dielectric material of the dielectric film fills the trench; laser-drilling a pit in the dielectric film and over the trench such that the external dimensions of the pit are at least approximately the same as or larger than the external dimensions of the portion of the silicon substrate or the trench; removing the portion of the silicon substrate surrounded by the trench to form a hole through the dielectric material in the trench, thereby exposing an inner surface of the dielectric material; depositing a conductive material on the first side of the silicon substrate and the dielectric film such that the conductive material extends through the hole; and grinding or polishing the silicon substrate on the first side and a second side opposite to the first side. Grinding or polishing removes the conductive material disposed outside the hole and the dielectric film disposed outside the trench, and further exposes the conductive and dielectric materials on the first and second sides.

[0011] In some embodiments, a method for forming a through-silicon via (TSV) structure is provided. The method includes: forming a trench in a first side of a silicon substrate such that the trench surrounds a portion of the silicon substrate; laminating a dielectric film on the first side of the silicon substrate such that the dielectric material of the dielectric film fills the trench; laser-drilling a recess in the dielectric film and over the portion of the silicon substrate such that the portion is exposed through the dielectric material; removing the portion of the silicon substrate surrounded by the trench to form a hole through the dielectric material in the trench, thereby exposing the inner surface of the dielectric material; depositing a conductive material on the first side of the silicon substrate and the dielectric film such that the conductive material extends through the hole; and grinding or polishing the silicon substrate on the first side and a second side opposite to the first side. Grinding or polishing removes the conductive material disposed outside the hole and the dielectric film disposed outside the trench, and further exposes the conductive and dielectric materials on the first and second sides. Attached Figure Description

[0012] To gain a detailed understanding of the features described above, a more specific description of the present disclosure can be obtained by referring to the embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings illustrate only typical embodiments of the present disclosure and should therefore not be considered as limiting the scope of the disclosure, as the present disclosure may allow for other equally effective embodiments.

[0013] Figure 1 The illustration shows a flowchart of a process for forming through-silicon vias in a substrate according to embodiments described herein.

[0014] Figures 2A to 2E A schematic diagram illustrates the situation in Figure 1 Cross-sectional views of the substrate at different stages of the process depicted.

[0015] Figure 3 The illustration shows a flowchart of a process for forming through-silicon vias in a substrate according to embodiments described herein.

[0016] Figures 4A to 4E A schematic diagram illustrates the situation in Figure 3 Cross-sectional views of the substrate at different stages of the process depicted.

[0017] Figure 5 The illustration shows a flowchart of a process for forming through-silicon vias in a substrate according to embodiments described herein.

[0018] Figures 6A to 6E A schematic diagram illustrates the situation in Figure 5 Cross-sectional views of the substrate at different stages of the process depicted.

[0019] Figure 7 The illustration shows a flowchart of a process for forming through-silicon vias in a substrate according to embodiments described herein.

[0020] Figures 8A to 8D A schematic diagram illustrates the situation in Figure 7 Cross-sectional views of the substrate at different stages of the process depicted.

[0021] Figure 9 The illustration shows a flowchart of a process for forming through-silicon vias in a substrate according to embodiments described herein.

[0022] Figures 10A to 10H A schematic diagram illustrates the situation in Figure 5 Cross-sectional views of the substrate at different stages of the process depicted. Detailed Implementation

[0023] Embodiments of this disclosure relate to shielded via structures for advanced wafer-level semiconductor packaging and methods for forming the same. The ongoing demand for smaller overall size and higher density advanced packaging structures has driven the need for improved dielectric shielding of interconnects disposed therein. However, as circuit density increases and via sizes decrease, the deposition of dielectric material within and around the interconnects becomes increasingly difficult, largely due to limitations associated with dielectric material deposition within narrow via structures. Consequently, thin and suboptimal dielectric shielding layers are formed, which can lead to increased leakage current and degraded system performance. The methods described herein provide an improved approach to forming dielectrically shielded via structures, enabling the formation of thick dielectric shielding layers while maintaining a low aspect ratio of the via structure.

[0024] Figure 1 The illustration shows a flowchart of a representative method 100 for structuring and subsequently laminating a substrate to form a through-silicon via. Figures 2A to 2E schematically illustrated Figure 1 Cross-sectional views of the substrate 200 at different stages of the structuring and lamination process 100 are shown. Therefore, for clarity, Figure 1 and Figures 2A to 2E They are described together in this document. It should be noted that although the formation of a single through-silicon via (TSV) is described, the methods disclosed herein can be used to form multiple TSVs or TSV arrays simultaneously.

[0025] Typically, method 100 begins with the corresponding Figure 2A Operation 110 involves applying a spin-coated / spray-coated or dry resist film 210 (such as photoresist) to a surface 202 on the top side 205 of a substrate 200, followed by patterning and development. The substrate 200 is formed of any suitable substrate material, including but not limited to Group III to Group V compound semiconductor materials, silicon (e.g., having a resistivity between about 1 Ohm-cm and about 10 Ohm-cm or a conductivity of about 100 W / mK), crystalline silicon (e.g., Si...). <100> or Si <111> The substrate can be made of materials such as silicon oxide, silicon germanium, doped or undoped silicon, undoped high-resistivity silicon (e.g., floating-zone silicon with low dissolved oxygen content and resistivity between about 5000 Ohm-cm and about 10000 Ohm-cm), doped or undoped polycrystalline silicon, silicon nitride, silicon carbide (e.g., with a conductivity of about 500 W / mK), quartz, glass (e.g., borosilicate glass), sapphire, alumina, and / or ceramic materials. In one embodiment, the substrate 200 is a monocrystalline p-type or n-type silicon substrate. In another embodiment, the substrate 200 is a p-type or n-type silicon solar cell substrate.

[0026] The substrate 200 may also have any suitable shape and / or size. For example, the substrate 200 may have a polygonal or circular shape. In some embodiments, the substrate 200 comprises a substantially square silicon substrate with a lateral dimension between about 120 mm and about 180 mm, such as about 150 mm, or between about 156 mm and about 166 mm, with or without chamfered edges. In some other embodiments, the substrate 200 comprises a circular silicon wafer with a diameter between about 20 mm and about 700 mm, such as between about 100 mm and about 500 mm, for example about 200 mm or about 300 mm.

[0027] Unless otherwise stated, the embodiments and examples described herein are for substrates with a thickness between about 50 μm and about 1500 μm, such as between about 90 μm and about 780 μm. For example, substrate 200 has a thickness between about 100 μm and about 300 μm, such as between about 110 μm and about 200 μm. In another example, substrate 200 has a thickness between about 60 μm and about 160 μm, such as between about 80 μm and about 120 μm.

[0028] In some embodiments, at operation 110, the resist film 210 is patterned by selectively exposing it to ultraviolet radiation and subsequently developing it. In some embodiments, the developing process is a wet process, such as a wet process that includes exposing the resist film 210 to a solvent. For example, the developing process may be a wet etching process utilizing an aqueous etching process. In other examples, the film developing process may be a wet etching process utilizing a buffered etching process that is selective to the desired material. However, any suitable combination of wet solvents or wet etchants can be used in the resist film developing process.

[0029] In a further embodiment, an adhesion promoter layer (not shown) may be applied to the surface 202 of the substrate 200 before the resist film 210 is applied to improve the adhesion of the resist film 210 to the substrate 200. For example, the adhesion promoter layer may be formed of bis(trimethylsilyl)amine, hexamethyldisilazane (HMDS), propylene glycol monomethyl ether acetate (PGMEA), etc.

[0030] like Figure 2A The depiction shows that the resist film 210 is patterned and developed according to the desired morphology of the dielectric shielding layer subsequently formed for the through-silicon vias (TSVs). Typically, the interconnects subsequently formed within the TSV have a cylindrical or tubular shape, and therefore, the surrounding dielectric shielding layer has a tubular shape. Thus, in some embodiments, the resist film 210 is patterned and developed to form annular trenches 212 in the resist film 210, thereby enabling the subsequent formation of a circular tubular dielectric shielding layer. Figure 2D A top view of the annular trench 212 is depicted for reference. However, in some other embodiments, non-cylindrical or non-annular interconnects and / or non-annular dielectric shielding layers are required, and thus non-annular trenches 212 are formed. For example, the shape of the trench 212 formed in the resist film 210 at operation 110 can be oval, elliptical, or polygonal. Figure 2E A top view of the polygonal groove 212 is depicted for reference.

[0031] At operation 120, the substrate 200, on which the patterned and developed resist film 210 is now formed, is exposed to a silicon etching process to transfer the pattern of the resist film 210 to the substrate 200, and thereafter the resist film 210 is removed. In some embodiments, the silicon etching process is a wet etching process, including a buffered etching process selectively removing silicon. In some embodiments, the etching process is a wet etching process utilizing an isotropic aqueous etching process. Any suitable wet etchant or combination of wet etchants can be used in a wet etching process. For example, in some embodiments, the substrate 200 is immersed in an aqueous HF etching solution or an aqueous KOH etching solution for etching. During the etching process, the etching solution can be heated to a temperature between about 30°C and about 100°C, such as between about 40°C and about 90°C, to accelerate the etching process. For example, the etching solution is heated to a temperature of about 70°C during the etching process. In yet other embodiments, the etching process at operation 120 is a dry etching process. An example of a dry etching process that can be performed at Operation 120 is a plasma-based dry etching process.

[0032] As a result of the etching process, a portion of the substrate 200 exposed through the trench 212 (e.g., surface 202) is etched away, thereby forming a feature 214 (e.g., a trench) that substantially corresponds to the trench 212 in its lateral morphology and thus corresponds to the subsequently formed dielectric shielding layer. For example, in some embodiments, the feature 214 may be substantially annular in shape, having dimensions (e.g., width) similar to those of the trench 212. Figure 2B As depicted, feature 214 is formed around a portion 204 of substrate 200, which is subsequently etched away to form a via. Typically, the depth of feature 214 can be adjusted by controlling the duration of substrate 200 exposure to the etchant (e.g., etching solution) used during the etching process. For example, the final depth of feature 214 can increase with increasing exposure to the etchant. Alternatively, feature 214 can have a reduced (e.g., shallower) final depth with decreasing exposure to the etchant.

[0033] After removing the resist film 210, at operation 130 and as follows Figure 2CAs shown, a dielectric film 220 is placed on the surface 202 of a patterned substrate 200 and laminated to flow into and fill newly formed features 214. During lamination, the substrate 200 and the dielectric film 220 are exposed to high temperatures, causing the dielectric film 220 to soften and flow into the features 214. In some embodiments, the lamination process is a vacuum lamination process that can be performed in a laminator or other suitable apparatus. In some embodiments, the lamination process is performed using a hot pressing process.

[0034] In one embodiment, the lamination process is performed at a temperature between about 80°C and about 200°C for a period between about 5 seconds and about 90 seconds, such as between about 30 seconds and about 60 seconds. In some embodiments, the lamination process includes applying a pressure between about 1 psi and about 50 psi while exposing the substrate 200 and the dielectric film 220 to a temperature between about 80°C and about 140°C for a period between about 5 seconds and about 90 seconds. For example, the lamination process is performed at a pressure between about 5 psi and about 40 psi and a temperature between about 100°C and about 120°C for a period between about 10 seconds and about 1 minute. For example, the lamination process is performed at a temperature of about 110°C for a period of about 20 seconds.

[0035] Typically, the dielectric film 220 is formed of epoxy resin. For example, the dielectric film 220 may be formed of an epoxy resin containing ceramic filler, such as an epoxy resin filled with (e.g., containing) substantially spherical silica (SiO2) particles. As used herein, the term "spherical" refers to any circular, ellipsoidal, or spherical shape. For example, in some embodiments, the ceramic filler may have an elliptical, elongated elliptical, or other similar circular shape. However, other morphologies are also contemplated. Other examples of ceramic fillers that can be used to form the dielectric film 220 include aluminum nitride (AlN), alumina (Al2O3), silicon carbide (SiC), silicon nitride (Si3N4), and Sr2Ce2Ti5O. 16 Ceramics, zirconium silicate (ZrSiO4), wollastonite (CaSiO3), beryllium oxide (BeO), cerium dioxide (CeO2), boron nitride (BN), calcium copper titanium oxide (CaCu3Ti4O) 12 ), magnesium oxide (MgO), titanium dioxide (TiO2), zinc oxide (zinc oxide), etc.

[0036] In some examples, the ceramic filler used to form the dielectric film 220 has particle sizes between about 40 nm and about 1.5 μm, such as between about 80 nm and about 1 μm. For example, the ceramic filler used to form the dielectric film 220 has particle sizes between about 200 nm and about 800 nm, such as between about 300 nm and about 600 nm. In some embodiments, the ceramic filler includes particles smaller than about 25% of the width or diameter of the feature 214 formed in the substrate 200, such as less than about 15% of the width or diameter of the desired feature.

[0037] After laminating dielectric film 220, the following reference can be used. Figure 3 and Figures 4A to 4E , Figure 5 and Figures 6A to 6E or alternative Figure 7 and Figures 8A to 8D The described method forms a shielded through-silicon via in substrate 200.

[0038] Figure 3 The illustration shows a flowchart of a first representative method 300 for forming through-silicon vias in the structured and laminated substrate 200 described above. Figures 4A to 4E A schematic diagram illustrates the situation in Figure 3 Cross-sectional views of the substrate 200 at different stages of the through-silicon via (TSV) formation process 300 are shown. Therefore, for clarity, Figure 3 and Figures 4A to 4E They are described together in this article.

[0039] In operation 310 and Figure 4A At operation 310, the top side 205 of the substrate 200 to which the dielectric film 220 is laminated is exposed to a grinding or polishing process to remove a portion of the dielectric film 220 disposed outside the feature 214. In some embodiments, the substrate 200 is exposed to a chemical mechanical polishing (CMP) process using a polishing slurry containing abrasive particles. Typically, the grinding or polishing process at operation 310 removes only the dielectric film 220 disposed outside the feature 214 and stops at the surface 202 of the substrate 200, resulting in the dielectric shielding layer 222 within the feature 214 having a top surface 216 flush with the surface 202. However, in some embodiments, the grinding or polishing process at operation 310 may also remove a portion of the substrate 200 as needed to reduce the thickness of the substrate 200 (e.g., to thin the substrate 200).

[0040] After grinding or polishing, a resist film 410 is applied to the surface 202 of the substrate 200 at operation 320 and subsequently patterned and developed. The resist film 410 may be substantially similar to the resist film 210 and may be patterned by selective exposure to UV radiation and subsequently developed via a wet process. In a further embodiment, an adhesion promoter layer (not shown) may be applied to the surface 202 of the substrate 200 prior to the application of the resist film 410. This adhesion promoter layer may be, for example, an adhesion promoter layer formed from bis(trimethylsilyl)amine, hexamethyldisilazane (HMDS), propylene glycol monomethyl ether acetate (PGMEA), etc.

[0041] like Figure 4B As depicted, the resist film 410 is patterned and developed to form trenches 412, the trenches 412 exposing the surface 202 above the portion 204, which is surrounded by a dielectric shielding layer 222. Therefore, the lateral dimensions (e.g., width) of the patterned trenches 412 correspond to the lateral dimensions of the portion 204, falling within a range between about 10 μm and about 50 μm, such as between about 20 μm and about 40 μm.

[0042] In operation 330 and Figure 4C At point 330, the substrate 200 is exposed to a second silicon etching process to form a hole 418 within the dielectric shielding layer 222, after which the resist film 410 is removed. In some embodiments, the silicon etching process at operation 330 is substantially similar to the etching process at operation 120. For example, the etching process may be a wet etching process, including a buffered etching process selectively removing silicon, or an isotropic aqueous etching process. As a result of the silicon etching process, a portion 204 of the substrate 200 is etched away, thereby forming a hole 418 (e.g., surrounded by the dielectric shielding layer 222) within the dielectric shielding layer 222 for subsequent deposition of a conductive material (e.g., interconnects). As described above, the hole 418 can have any desired shape, such as cylindrical or polygonal. However, in some examples, the hole 418 is oval or elliptical in shape.

[0043] In operation 340 and Figure 4D At this location, a conductive layer 430 is formed on the exposed surface of the dielectric shielding layer 222 and on the surface 202 of the substrate 200. For example... Figure 4DAs shown, conductive layer 430 extends over surfaces 202, 216, and dielectric shielding layer 222 surrounding via 418. Conductive layer 430 will subsequently serve as an interconnect through substrate 200. Conductive layer 430 is deposited on substrate 200 by any suitable method, including electroless deposition or a combination of physical vapor deposition (PVD) and electrochemical deposition (ECD). In some embodiments, conductive layer 430 is deposited to fill or “plug” via 418, thereby forming a solid or filled conductive body within via 418. However, in some other embodiments, conductive layer 430 is deposited only onto the line surface of dielectric shielding layer 222 surrounding via 418. In such embodiments, the thickness of conductive layer 430 is between about 5 μm and about 20 μm, such as between about 10 μm and about 15 μm.

[0044] The conductive layer 430 is typically formed of one or more layers of any suitable conductive material, including but not limited to copper, aluminum, gold, nickel, silver, palladium, tin, etc. In a further embodiment, an adhesion layer (not shown) and / or a seed layer (not shown) are formed on the surfaces of the substrate 200 and the dielectric shielding layer 222 before depositing the conductive layer 430. For example, in some embodiments, a molybdenum, titanium, tantalum, or titanium-tungsten adhesion layer and / or a copper seed layer are deposited on the substrate 200 and the dielectric shielding layer 222 before depositing the conductive layer 430 to improve the adhesion between the substrate 200 and the dielectric shielding layer 222 and to block the diffusion of the conductive material.

[0045] After depositing the conductive layer 430, during operation 350 and Figure 4E A second grinding or polishing process (e.g., CMP) is performed on substrate 200 to remove at least a portion of the conductive layer 430 disposed outside the via 418, as well as a portion of substrate 200 on its back side 207. Similar to the grinding or polishing process at operation 310, grinding or polishing on the top side 205 may stop at the surface 202 of substrate 200. However, grinding or polishing on the back side 207 continues until the dielectric shielding layer 222 and the conductive layer 430 formed therein are exposed on the back side 207, resulting in a through-silicon via 440 having conductive layers 430 (e.g., interconnects) shielded by the dielectric shielding layer 222.

[0046] Figure 5 The diagram illustrates an alternative method 500 for forming through-silicon vias in a substrate 200 when performing the method 100 described above. Figures 6A to 6E A schematic diagram illustrates the situation in Figure 5 Cross-sectional views of substrate 200 at different stages of the through-silicon via (TSV) formation process 500 are shown. Therefore, for clarity, Figure 5 and Figures 6A to 6E They are described together in this article.

[0047] In operating 510 and Figure 6A At operation 510, a single region of the laminated dielectric film 220 above feature 214 is removed from substrate 200 by laser ablation, thereby separating the dielectric shielding layer 222 disposed within feature 214 from the remainder of the dielectric film 220 and forming a top surface 216 of the dielectric shielding layer 222. The laser ablation of the dielectric film 220 further creates a pit 602 above feature 214, the outer lateral dimension of which is at least approximately the same as or larger than that of portion 204 or feature 214. The laser system used for ablation or drilling of the dielectric film 220 at operation 510 may include any suitable type of laser source, such as an infrared (IR) laser, a picosecond UV laser, a femtosecond UV laser, or a femtosecond green laser, and may generate continuous and / or pulsed laser beams.

[0048] Following laser ablation, a resist film 610 is placed on the top side 205 of the substrate 200 at operation 520, and subsequently patterned and developed. The resist film 610 may be substantially similar to resist films 210 and 410, and may be patterned by selective exposure to UV radiation and subsequently developed via a wet process. In a further embodiment, an adhesion promoter layer (not shown) may be used to promote adhesion of the resist film 610 to the dielectric film 220 and / or the substrate 200.

[0049] like Figure 6B As depicted, prior to patterning and development, a resist film 610 is applied over the dielectric film 220 and within the pits 602. Patterning and / or development of the resist film 610 forms trenches 612 that expose the surface 202 of a portion 204 of the substrate 200, which is surrounded by a dielectric shielding layer 222. Therefore, the lateral dimensions (e.g., width) of the patterned trenches 612 correspond to the lateral dimensions of the portion 204, falling within a range between about 10 μm and about 50 μm, such as between about 20 μm and about 40 μm.

[0050] In operation 530 and Figure 6C At point 530, the substrate 200 is exposed to a silicon etching process to form a hole 418 within the dielectric shielding layer 222, and thereafter the resist film 610 is removed. In some embodiments, the silicon etching process at operation 530 is substantially similar to the etching processes at operations 120 and 330. For example, the etching process can be a wet etching process, including a buffered etching process selectively removing silicon, or an isotropic aqueous etching process. As a result of the silicon etching process, a portion 204 of the substrate 200 is etched away, thereby forming a hole 418 within the dielectric shielding layer 222. As described above, the hole 418 can have any desired shape, such as a cylindrical or polygonal shape. However, in some examples, the hole 418 is oval or elliptical in shape.

[0051] In operation 540 and Figure 6D At this location, a conductive layer 430 is deposited on the exposed surfaces of the dielectric shielding layer 222, the dielectric film 220, and the surface 202 of the substrate 200. For example... Figure 6D As shown, a portion of the conductive layer 430 extends into the via 418, and this portion of the conductive layer 430 will subsequently serve as an interconnect through the substrate 200. As described above, the conductive layer 430 is deposited on the substrate 200 by any suitable method, including electroless deposition, or a combination of physical vapor deposition (PVD) and electrochemical deposition (ECD). In some embodiments, the conductive layer 430 is deposited to fill or “plug” the via 418, thereby forming a solid or filled conductive body within the via 418. However, in some other embodiments, the conductive layer 430 is deposited only onto the line surface of the dielectric shielding layer 222 surrounding the via 418.

[0052] After depositing the conductive layer 430, during operation 550 and Figure 6E At the location, a grinding or polishing process (e.g., CMP) is performed on the substrate 200. The grinding or polishing process removes the remaining dielectric film 220 and conductive layer 430 disposed outside the hole 418, as well as a portion of the substrate 200 on the back side 207, to expose the dielectric shielding layer 222 and conductive layer 430 on the back side 207. Thus, a through-silicon via 440 is formed having the conductive layer 430 shielded by the dielectric shielding layer 222.

[0053] Figure 7 The diagram illustrates an alternative method 700 for forming a through-silicon via in a substrate 200 when performing method 100 described above. Figures 8A to 8D A schematic diagram illustrates the situation in Figure 7 Cross-sectional views of substrate 200 at different stages of the through-silicon via (TSV) formation process 700 are shown. Therefore, for clarity, Figure 7 and Figures 8A to 8D They are described together in this article.

[0054] In operating 710 and Figure 8A At operation 710, a region of the laminated dielectric film 220 disposed above and corresponding to portion 204 of substrate 200 is removed by laser ablation, thereby forming a pit 802. Typically, the pit 802 is ablated to have an external lateral dimension at least about the same as or larger than that of portion 204, so that a hole 418 can be formed by subsequently removing portion 204 by etching. The laser system used to ablate the dielectric film 220 at operation 710 may include any suitable type of laser source, such as an infrared (IR) laser, a picosecond UV laser, a femtosecond UV laser, or a femtosecond green laser, and may generate a continuous and / or pulsed laser beam.

[0055] Following laser ablation, at operation 720, substrate 200 is exposed to a silicon etching process to etch away portion 204 and form a hole 418 through the dielectric material disposed within feature 214. In some embodiments, the silicon etching process at operation 720 is substantially similar to the etching processes at operations 120, 330, and / or 530. For example, the etching process can be a wet etching process, including a buffered etching process selectively removing silicon, or an isotropic aqueous etching process. As mentioned above, the hole 418 can have any desired shape, such as cylindrical or polygonal. However, in some examples, the hole 418 is oval or elliptical in shape. Figure 8B The etching process at operation 720 is performed without the use of a resist film. Instead, the dielectric layer 220 itself acts as a resist during the process, thereby preventing undesirable etching of the substrate 200 at locations other than portion 204.

[0056] In operating 730 and Figure 8C At this location, a conductive layer 430 is deposited on the exposed surface of the dielectric film 220, including the portion extending into the via 418, for subsequent use as an interconnect. The conductive layer 430 can be deposited on the substrate 200 by any suitable method, including electroless deposition or a combination of physical vapor deposition (PVD) and electrochemical deposition (ECD). In some embodiments, the conductive layer 430 is deposited to fill or “plug” the via 418, thereby forming a solid or filled conductive body within the via 418. However, in some other embodiments, the conductive layer 430 is deposited only onto the line surface of the dielectric material surrounding the via 418.

[0057] After depositing the conductive layer 430, in operation 740 and Figure 8D At the location, a grinding or polishing process (e.g., CMP) is performed on the substrate 200. The grinding or polishing process removes the dielectric film 220 and conductive layer 430 disposed outside the hole 418, as well as a portion of the substrate 200 on the back side 207, to expose the conductive layer 430 on the back side 207. Thus, a through-silicon via 440 having a conductive layer 430 shielded by a dielectric shielding layer 222 is formed through the substrate 200.

[0058] Figure 9 The diagram illustrates a flowchart of another representative method 900 for forming through-silicon vias in substrate 200, independent of methods 100, 300, 500, and 700 described above. Figures 10A to 10H A schematic diagram illustrates the situation in Figure 9 The diagram shows cross-sectional views of the substrate 1000 at different stages of the through-silicon via (TSV) formation process 900. Therefore, for clarity, Figure 9 and Figures 10A to 10H They are described together in this article.

[0059] Typically, method 900 begins with the corresponding Figure 10A Operation 910 involves applying a resist film 1010 to surface 202 on the top side 205 of substrate 200, followed by patterning and development. The resist film 1010 may be substantially similar to resist films 210, 410, and 610, and may be patterned via selective exposure to UV radiation and subsequently developed via a wet process. In a further embodiment, an adhesion promoter layer (not shown) may be used to promote adhesion of the resist film 1010 to the substrate 200.

[0060] like Figure 10A The depiction shows that the resist film 1010 is patterned and developed according to the desired morphology of the interconnects subsequently formed for through-silicon vias. Typically, the subsequently formed interconnects have a cylindrical or tubular shape, and therefore, the resist film 1010 is patterned and developed to form cylindrical trenches 1012, thereby enabling the subsequent formation of tubular or cylindrical interconnects. However, in some embodiments, non-cylindrical or non-annular interconnects are required, and therefore, non-circular or non-cylindrical trenches 1012 are formed.

[0061] At operation 920, the substrate 200, on which the patterned and developed resist film 1010 is now formed, is exposed to a silicon etching process to transfer the pattern of the resist film 1010 to the substrate 200, and thereafter the resist film 1010 is removed. In some embodiments, the silicon etching process at operation 920 is substantially similar to the etching processes at operations 120, 330, 530, and / or 720. For example, the etching process may be a wet etching process, including a buffered etching process selectively removing silicon, or an isotropic aqueous etching process.

[0062] As a result of the etching process, the portion of the substrate 200 exposed through the trench 1012 is etched away, thereby forming a hole 1018. The hole 1018 substantially corresponds to the trench 1012 in lateral morphology and therefore corresponds to the interconnect subsequently formed. For example, in some embodiments, the hole 1018 may be substantially cylindrical in shape, having a diameter similar to that of the trench 1012. Typically, the depth of the hole 1018 can be adjusted by controlling the time the substrate 200 is exposed to the etchant (e.g., etching solution) used during the etching process. For example, the final depth of the hole 1018 may increase with increasing exposure to the etchant. Alternatively, the hole 1018 may have a reduced (e.g., shallower) final depth with decreasing exposure to the etchant.

[0063] In operating 930 and Figure 10CAt this location, a conductive layer 1030 is deposited on the top side 205 of the substrate 200, including surface 202 and the surface extending into the via 1018, for subsequent use as an interconnect. The conductive layer 1030 is substantially similar to the conductive layer 430 and can be deposited on the substrate 200 by any suitable method, including electroless deposition or a combination of physical vapor deposition (PVD) and electrochemical deposition (ECD). In some embodiments, the conductive layer 1030 is deposited to fill or “plug” the via 1018, thereby forming a solid or filled conductive body within the via 1018. However, in some other embodiments, the conductive layer 1030 is deposited only on the line surface of the substrate 200 surrounding the via 1018.

[0064] After depositing the conductive layer 1030, in operation 940 and Figure 10D At the location, a grinding or polishing process (e.g., CMP) is performed on the substrate 200. The grinding or polishing process removes the conductive layer 1030 disposed outside the hole 1018, thereby forming a top surface 1026 of the conductive layer 1030 flush with the surface 202 of the substrate 200.

[0065] In operating 950 and Figure 10E A second resist film 1050 is applied to the surface 202 of the substrate 200, and then patterned and developed. The resist film 1050 may be substantially similar to the resist film 1010 and may be patterned by selective exposure to UV radiation and subsequently developed via a wet process. In a further embodiment, an adhesion promoter layer (not shown) may be applied to the surface 202 of the substrate 200 prior to the application of the resist film 1050. The adhesion promoter layer may be an adhesion promoter layer such as that formed from bis(trimethylsilyl)amine, hexamethyldisilazane (HMDS), propylene glycol monomethyl ether acetate (PGMEA), etc.

[0066] like Figure 10E As shown, the resist film 1050 is patterned and developed to form trenches 1052, which correspond to the desired shape of the dielectric shielding layer subsequently formed for the conductive layer 1030. Therefore, the formation of trenches 1052 exposes the surface 202 of the substrate 200 surrounding the via 1018. Typically, the subsequently formed dielectric shielding layer has a tubular shape, and thus trenches 1052 are patterned as annular. However, in some embodiments, non-cylindrical or non-annular interconnects and / or non-annular dielectric shielding layers are required, and thus non-annular trenches 1052 are formed. For example, the shape of the trenches 1052 formed in the resist film 1050 can be oval, elliptical, or polygonal.

[0067] After patterning and developing the resist film 1050, at operation 960, the substrate 200 is exposed to a second silicon etching process to transfer the pattern of the resist film 1050 to the substrate 200, and then the resist film 1050 is removed. Similar to the etching process described above, the etching process at operation 960 can be a wet etching process, including a buffer etching process selectively removing silicon, or an isotropic aqueous etching process. Figure 10F As shown, at operation 960, the portion of the substrate 200 exposed through trench 1052 is etched away, thereby forming feature 1014, which substantially corresponds to trench 1052 in lateral morphology and thus corresponds to the dielectric shielding layer subsequently formed. For example, in some embodiments, feature 1014 may be substantially annular in shape and circumferentially surrounds conductive layer 1030.

[0068] In operating 970 and Figure 10G At the point where a dielectric film 1020 is placed on the surface 202 of a patterned substrate 200, lamination is performed to allow the newly formed feature 1014 to flow in and fill. During lamination, the substrate 200 and the dielectric film 1020 are exposed to high temperatures, causing the dielectric film 1020 to soften and flow into the feature 1014. In some embodiments, the lamination process is a vacuum lamination process that can be performed in an autoclave or other suitable apparatus. In some embodiments, the lamination process is performed using a hot pressing process.

[0069] Finally, in operating 980 and Figure 10H At this location, a second grinding or polishing process (e.g., CMP) is performed on the substrate 200 to remove the dielectric film 1020 disposed outside feature 1014, as well as a portion of the substrate 200 on its back side 207. Similar to the grinding or polishing process described above, grinding or polishing on the top side 205 can stop at the surface 202 of the substrate 200 while grinding or polishing is performed on the back side 207 until the conductive layer 1030 is exposed on the back side 207. Thus, a through-silicon via 1040 is formed having a conductive layer 1030 (e.g., interconnect) shielded by the dielectric shielding layer 1022.

[0070] The methods and via structures described above offer numerous advantages over conventional dielectric deposition techniques used for shielded package interconnects. These benefits include the ability to form a thick dielectric shielding layer while maintaining a low aspect ratio for the via structure. Furthermore, in addition to the thin form factor and high via-to-substrate volume ratio of the resulting package structure, these features advantageously provide a package architecture for advanced integrated semiconductor devices that offers improved performance and flexibility compared to conventional packaging techniques, along with relatively lower manufacturing costs. The thin and small form factor package structures described herein not only provide the benefits of high I / O density and improved bandwidth and power but also maximize shielding against unwanted leakage currents or interference.

[0071] Although the foregoing embodiments are directed to this disclosure, other and further embodiments of this disclosure may be devised without departing from the basic scope of this disclosure, the scope of which is defined by the appended claims.

Claims

1. A method for forming a through-silicon via (TSV) structure, comprising the following steps: A trench is formed on a first side of a silicon substrate, the trench surrounding a portion of the silicon substrate; A dielectric film is laminated onto the first side of the silicon substrate, and the lamination of the dielectric film causes the dielectric material of the dielectric film to fill the trench; A recess is laser-drilled in the dielectric film and above the trench, wherein the external dimensions of the recess are larger than the portion of the silicon substrate or the external dimensions of the trench; A photoresist film is applied and patterned over the first side of the silicon substrate, the pattern of the photoresist film corresponding to the portion of the silicon substrate; Remove the portion of the silicon substrate surrounded by the trench to form a hole in the trench through the dielectric material, the hole exposing the inner surface of the dielectric material; Remove the resist film; A conductive material is deposited on the first side of the silicon substrate, the conductive material extending through the hole; as well as Grinding or polishing the first side and the second side opposite to the first side of the silicon substrate, wherein the grinding or polishing removes the conductive material disposed outside the hole and the dielectric film disposed outside the trench, and wherein the grinding or polishing further exposes the remaining conductive material and the dielectric material on the first side and the second side.

2. The method of claim 1, wherein the trench is formed via a silicon etching process.

3. The method of claim 2, wherein the trench has an annular shape.

4. The method of claim 1, wherein the dielectric material comprises an epoxy resin having ceramic filler.

5. The method of claim 1, wherein the portion of the silicon substrate is removed via a silicon etching process.

6. The method of claim 1, wherein the conductive material is deposited via electroless plating, or by physical vapor deposition (PVD) and electrochemical deposition (ECD).

7. A method for forming a through-silicon via (TSV) structure, comprising the following steps: A trench is formed on a first side of a silicon substrate, the trench surrounding a portion of the silicon substrate; A dielectric film is laminated onto the first side of the silicon substrate, and the lamination of the dielectric film causes the dielectric material of the dielectric film to fill the trench; A recess is laser-drilled in the dielectric film and above the trench, wherein the external dimensions of the recess are at least the same as the external dimensions of the portion of the silicon substrate; Remove the portion of the silicon substrate surrounded by the trench to form a hole in the trench through the dielectric material, the hole exposing the inner surface of the dielectric material; A conductive material is deposited on the first side of the silicon substrate, the conductive material extending through the hole; as well as Grinding or polishing the first side of the silicon substrate, wherein the grinding or polishing removes the conductive material disposed outside the hole and the dielectric film disposed outside the trench.

8. The method of claim 7, wherein the trench is formed via a silicon etching process utilizing a resist film.

9. The method of claim 8, wherein the trench has an annular shape.

10. The method of claim 7, wherein the dielectric material comprises an epoxy resin having ceramic filler.

11. The method of claim 7, wherein the lamination is performed at a temperature below 200°C.

12. The method of claim 8, wherein after removing the dielectric film disposed outside the trench, the portion of the silicon substrate is removed via a second silicon etching process utilizing a resist film applied to the silicon substrate.

13. The method of claim 7, wherein the conductive material is deposited via electroless plating, or by physical vapor deposition (PVD) and electrochemical deposition (ECD).

14. A method for forming a through-silicon via (TSV) structure, comprising the following steps: A trench is formed on a first side of a silicon substrate, the trench surrounding a portion of the silicon substrate; A dielectric film is laminated onto the first side of the silicon substrate, and the lamination of the dielectric film causes the dielectric material of the dielectric film to fill the trench; A recess is laser-drilled in the dielectric film and above the trench, wherein the external dimensions of the recess are the same as or larger than the portion of the silicon substrate or the external dimensions of the trench; Remove the portion of the silicon substrate surrounded by the trench to form a hole in the trench through the dielectric material, the hole exposing the inner surface of the dielectric material; A conductive material is deposited on the first side of the silicon substrate and on the dielectric film, the conductive material extending through the hole; as well as Grinding or polishing the first side and the second side opposite to the first side of the silicon substrate, wherein the grinding or polishing removes the conductive material disposed outside the hole and the dielectric film disposed outside the trench, and wherein the grinding or polishing further exposes the remaining conductive material and the dielectric material on the first side and the second side.

15. The method of claim 14, wherein the trench is formed via a silicon etching process utilizing a resist film.

16. The method of claim 14, wherein the trench has an annular shape.

17. The method of claim 14, wherein the dielectric material comprises an epoxy resin having ceramic filler.

18. The method of claim 15, wherein the portion of the silicon substrate is removed via a second silicon etching process utilizing a resist film applied over the silicon substrate and the dielectric film.

19. The method of claim 14, wherein the conductive material is deposited via electroless plating, or by physical vapor deposition (PVD) and electrochemical deposition (ECD).

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