Using random threshold voltage variations in field effect transistor structures as physically unclonable function security chip identification

Abstract

A semiconductor structure can include one or more metal gates, one or more channels below the one or more metal gates, a gate dielectric layer separating the one or more metal gates from the one or more channels, and a high-k material embedded in the gate dielectric layer. Both the high-k material and the gate dielectric layer can be in direct contact with the one or more channels. The high-k material can provide a threshold voltage shift in the one or more metal gates. The high-k material is a first high-k material or a second high-k material. The semiconductor structure can include only the first high-k material embedded in the gate dielectric layer. The semiconductor structure can include only the second high-k material embedded in the gate dielectric layer. The semiconductor structure can include both the first high-k material and the second high-k material embedded in the gate dielectric layer.

Description

Background Technology

[0001] This invention generally relates to semiconductor structures and methods of forming them. More specifically, this invention relates to using random threshold voltage (Vth) variations in a field-effect transistor (FET) structure as a security chip identifier for a physically unclonable function (PUF).

[0002] A PUF (Physically Defined Digital Fingerprint) serves as a unique identifier for semiconductor devices, such as microprocessors. A PUF is a physical entity embodied in the physical structure. PUFs are based on unique physical changes that occur naturally during semiconductor manufacturing. PUFs can be implemented in integrated circuits. PUFs can also be used in applications with high security requirements, such as cryptography. Summary of the Invention

[0003] According to one embodiment of the present invention, a semiconductor structure is provided. The semiconductor structure may include one or more metal gates, one or more channels beneath the one or more metal gates, a gate dielectric layer separating the one or more metal gates from the one or more channels, and a high-k material embedded in the gate dielectric layer. Both the high-k material and the gate dielectric layer may be in direct contact with the one or more channels. The high-k material may provide a threshold voltage variation in the one or more metal gates. The high-k material may be a first high-k material or a second high-k material. The semiconductor structure may include only the first high-k material embedded in the gate dielectric layer. The semiconductor structure may include only the second high-k material embedded in the gate dielectric layer. The semiconductor structure may include both the first high-k material and the second high-k material embedded in the gate dielectric layer.

[0004] According to another embodiment of the present invention, a semiconductor structure is provided. The semiconductor structure may include one or more gate regions of one or more field-effect transistors. The one or more gate regions may be over one or more channels. The semiconductor structure may include a metal gate separated from the one or more channels by a gate dielectric layer, a high-k material embedded in the gate dielectric layer, and an interlayer dielectric. Both the high-k material and the gate dielectric layer may be in direct contact with the one or more channels. The interlayer dielectric may surround the one or more gate regions. The high-k material may be a first high-k material or a second high-k material. The semiconductor structure may include only the first high-k material embedded in the gate dielectric layer. The semiconductor structure may include only the second high-k material embedded in the gate dielectric layer. The semiconductor structure may include both the first high-k material and the second high-k material embedded in the gate dielectric layer. The high-k material may provide a threshold voltage variation in the one or more metal gates.

[0005] According to another embodiment of the present invention, a method is provided. The method may include forming one or more gate regions over a channel, randomly nucleating a high-k material in the one or more gate regions, and depositing a gate dielectric layer in each of the one or more gate regions. Random nucleation of the high-k material in the one or more gate regions facilitates a random threshold voltage within the one or more gate regions. The random threshold voltage within the one or more gate regions can be used as a physically non-clonable function. The one or more gate regions may be surrounded by gate spacers. The gate dielectric layer may cover the entire surface of the channel. A second high-k material may partially cover the surface of the channel. The high-k material may be a first high-k material or a second high-k material. The method may include embedding only the first high-k material in the gate dielectric layer. The method may include embedding only the second high-k material in the gate dielectric layer. The method may include embedding both the first high-k material and the second high-k material in the gate dielectric layer. The method may include forming a first source / drain and a second source / drain, depositing a metal gate on top of the gate dielectric layer, depositing an interlayer dielectric around the one or more gate regions, and forming a first source / drain contact and a second source / drain contact. The first and second source drains can be separated from one or more gate regions by gate spacers. An interlayer dielectric can be placed on top of the first and second source drains. Attached Figure Description

[0006] The following detailed description will be best understood in conjunction with the accompanying drawings, which are given by way of example and are not intended to limit the invention thereto, in which: Figure 1 This is a cross-sectional view showing fins and buried oxides arranged on a substrate according to an exemplary embodiment; Figure 2 This is a cross-sectional view showing a dummy gate and gate spacer arranged on a fin according to an exemplary embodiment; Figure 3 This is a cross-sectional view showing the first and second source / drain electrodes and the interlayer dielectric according to an exemplary embodiment; Figure 4 This is a cross-sectional view showing a plurality of gate regions having trenches formed as exposed fins on the top surface, according to an exemplary embodiment; Figure 5 This is a cross-sectional view showing a plurality of gate regions having a first high-k material according to an exemplary embodiment; Figure 6 This is a cross-sectional view showing a plurality of gate regions having a second high-k material according to an exemplary embodiment; Figure 7 This is a cross-sectional view showing a plurality of gate regions having a gate dielectric layer according to an exemplary embodiment; Figure 8This is a cross-sectional view showing a plurality of gate regions having gate metal and contacts according to an exemplary embodiment; and Figure 9 This is a top view showing the gate regions of the first and second high-k materials with random nucleation according to an exemplary embodiment.

[0007] The accompanying drawings are not necessarily to scale. They are merely schematic representations and not intended to depict specific parameters of the invention. The drawings are intended to illustrate only typical embodiments of the invention. In the drawings, similar reference numerals denote similar elements. Detailed Implementation

[0008] This document discloses detailed embodiments of the claimed structures and methods; however, it is to be understood that the disclosed embodiments are merely illustrative of the claimed structures and methods that can be implemented in various forms. The invention can be implemented in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Details of well-known features and techniques may be omitted in the description to avoid unnecessarily obscuring the presented embodiments.

[0009] For the purposes described below, the terms “upper,” “lower,” “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” and their derivatives shall apply to the disclosed structures and methods, as oriented as shown in the accompanying drawings. The terms “cover,” “on top,” “on top,” or “on top” indicate that a first element (e.g., a first structure) is present on a second element (e.g., a second structure), wherein an intermediate element, such as an interface structure, may be present between the first and second elements. The term “direct contact” refers to the connection of the first element (e.g., the first structure) and the second element (e.g., the second structure) at the interface between the two elements without any intermediate conductive, insulating, or semiconductor layer.

[0010] To avoid obscuring the presentation of embodiments of the invention, some processing steps or operations known in the art may be combined for presentation and illustrative purposes in the following detailed description, and may not be described in detail in some instances. In other cases, some processing steps or operations known in the art may not be described at all. It should be understood that the following description focuses more on the distinguishing features or elements of various embodiments of the invention.

[0011] Embodiments of the present invention generally relate to semiconductor structures and methods of forming the same. More specifically, the present invention relates to ensuring chip identification by using random threshold voltage (Vth) variations in a field-effect transistor (FET) structure as a physically unclonable function (PUF).

[0012] For example, if a dummy component replaces a real component, it may contain malicious circuitry that could cause the device to lose functionality or be used for eavesdropping. Therefore, there is a need to manufacture a semiconductor device that can be identified as secure.

[0013] Many semiconductor devices use PUFs (Physically Defined Fingerprints) as a security measure. A PUF is a physically defined "digital fingerprint" that serves as a unique identifier for a semiconductor device, such as a microprocessor. A PUF is a physical object that, for a given input and condition (query), provides a physically defined "digital fingerprint" output (response), which serves as a unique identifier. PUFs are based on unique physical changes that occur naturally during semiconductor manufacturing. PUFs can be implemented in integrated circuits. PUFs can also be used in applications with high security requirements, such as cryptography.

[0014] Silicon push-form elements (PUFs) are increasingly being used as hardware roots of trust and entropy sources for cryptographic applications. In these applications, the reliability of the PUF output is critical to successful implementation. Both weak and strong PUFs obtain their outputs by amplifying analog signals derived from physical properties on the integrated circuit block. These analog signals can be propagation delays, ring oscillators, time-controlled oxide breakdown, or the Vth of an SRAM transistor. These physical measurements are inherently sensitive to environmental conditions such as temperature, operating voltage, transistor thermal / interface noise, process corner, and aging. Consequently, achieving stable PUF outputs is difficult without additional stabilization and error correction techniques, such as Time Majority Voting (TMV), pre-burning of PUF bits for end-of-life (EOL) prediction and reliability screening, masking algorithms, and balanced parity bits for error-correcting codes (ECC). Therefore, there is a need to fabricate semiconductor devices with stable PUF outputs.

[0015] Embodiments of the present invention provide a structure and method for forming random Vth variations in the gate structure of a FET. The FET can be a planar FET, nanosheet FET, vertical FET, nanowire FET, fin FET, or any other FET or semiconductor device having a gate structure. The random Vth is used as a PUF and is achieved by randomly depositing different high-k materials in multiple gate regions of the device. Figures 1-8 A method for fabricating a FET structure with random Vth variation as a PUF is shown. Figure 9 A top cross-sectional view of the gate region with a randomly distributed high-k material is shown, which enables the generation of different Vth values.

[0016] Now for reference Figure 1The diagram illustrates a structure 100 according to an embodiment. Structure 100 may include a substrate 102, a buried oxide 104, and a fin 106. The substrate 102 may include one or more semiconductor materials. Non-limiting examples of suitable substrate 102 materials may include Si (silicon), strained Si, Ge (germanium), SiGe (silicon-germanium), Si alloys, Ge alloys, III-V materials (e.g., GaAs (gallium arsenide), InAs (indium arsenide), InP (indium phosphide), or indium gallium arsenide (InGaAs)), II-VI materials (e.g., CdSe (cadmium selenide), CdS (cadmium sulfide), CdTe (cadmium telluride)) or any combination thereof. In this embodiment, the substrate 102 may include silicon.

[0017] Buried oxide 104 is disposed on substrate 102. Buried oxide 104 may be an oxide layer buried in a silicon wafer, such as silicon oxide. Fin 106 is disposed on the top surface of buried oxide 104. Fin 106 may be made of silicon. In an embodiment, fin 106 may be a silicon-on-insulator fin. In an alternative embodiment, fin 106 may be a body fin. Furthermore, it should be understood that even though silicon-on-insulator fins are shown, embodiments of the invention can be implemented on any CMOS device or transistor device including a gate structure.

[0018] Now for reference Figure 2 The diagram illustrates a structure 100 according to an embodiment, having a dummy gate 108, a gate spacer 110, a first source drain 112, and a second source drain 114. A sacrificial gate material can be deposited on the top surface of the fin 106. The sacrificial gate material can then be patterned to form the dummy gate 108.

[0019] The dummy gate 108 can be formed of a sacrificial gate material, such as amorphous silicon (α-Si) or polycrystalline silicon (polysilicon). The sacrificial material can be deposited using deposition processes, including but not limited to physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), inductively coupled plasma chemical vapor deposition (ICPCVD), or any combination thereof. The sacrificial material forming the dummy gate 108 can have a thickness of about 50 nm to about 250 nm, or about 100 nm to about 200 nm.

[0020] Once the dummy gate 108 is formed, a gate spacer 110 is conformally deposited on the dummy gate 108. The gate spacer 110 is then patterned to remove a portion of the gate spacer 110 on the top surface of the fin 106. As a result, the gate spacer 110 surrounds the dummy gate 108. The gate spacer 110 is located on the top surface and sidewalls of the dummy gate 108.

[0021] Gate spacer 110 may include an insulating material, such as silicon dioxide, silicon nitride, SiOCN, or SiBCN. Other non-limiting examples of materials for gate spacer 110 may include dielectric oxides (e.g., silicon oxide), dielectric nitrides (e.g., silicon nitride), dielectric oxide nitrides, or any combination thereof. The gate spacer 110 material is deposited by a deposition process, such as chemical vapor deposition (CVD) or physical vapor deposition (PVD). Gate spacer 110 has a thickness of about 3 to about 15 nm or about 5 to about 8 nm. Gate spacer 110 insulates dummy gate 108 from other materials formed or deposited around dummy gate 108. Furthermore, gate spacer 110 isolates dummy gate 108 from first and second source / drain 112, 114.

[0022] Once the gate spacer 110 has been deposited, an epitaxial layer is grown on the surface of the fin 106 to form a first source drain 112 and a second source drain 114. The first and second source drains 112, 114 can be grown using suitable growth processes, such as chemical vapor deposition (CVD), low-pressure (LP) or reduced-pressure chemical vapor deposition (RPCVD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), metal-organic chemical vapor deposition (MOCVD), or other suitable processes.

[0023] The source of the epitaxial layer material can be, for example, silicon, germanium, or a combination thereof. The gas source for depositing the epitaxial semiconductor material can include a silicon-containing gas source, a germanium-containing gas source, or a combination thereof. For example, an epitaxial silicon layer can be deposited from a silicon gas source selected from silane, dichlorosilane, propane, tetrasilane, hexachlorodichlorosilane, tetrachlorosilane, dichlorosilane, trichlorosilane, and combinations thereof. An epitaxial germanium layer can be deposited from a germanium gas source selected from germanane, dichlorogerane, halogerane, dichlorogerane, trichlorogerane, tetrachlorogerane, and combinations thereof. Combinations of these gas sources can be used to form epitaxial silicon-germanium alloy layers. Carrier gases such as hydrogen, nitrogen, helium, and argon can be used.

[0024] The first and second source / drain electrodes 112, 114 can be in-situ doped with p-type or n-type dopants. For example, for a p-type FET, the first and second source / drain electrodes 112, 114 can be made of silicon-germanium and in-situ doped with a p-type dopant such as boron. For an n-type FET, the first and second source / drain electrodes 112, 114 can be made of silicon and in-situ doped with an n-type dopant (e.g., phosphorus or arsenic).

[0025] Now for reference Figure 3The diagram illustrates a structure 100 with an interlayer dielectric (ILD) 116 according to an embodiment. Once the first and second source drains 112, 114 are formed, the ILD 116 can be deposited onto the top surfaces of the first and second source drains 112, 114 such that the top surface of the ILD 116 is substantially flush with the top surface of the gate spacer 110 (not shown). The ILD 116 surrounds the gate spacer 110. The ILD 116 can be formed from, for example, a low-k dielectric material (k < 4.0), including but not limited to silicon oxide, spin-coated glass, flowable oxide, high-density plasma oxide, borosilicate glass (BPSG), or any combination thereof.

[0026] ILD 116 is deposited using deposition processes, including but not limited to CVD, PVD, plasma-enhanced CVD, evaporation, chemical solution deposition, or similar processes. After depositing ILD 116, excess ILD 116 can be removed from the top surface of structure 100 using a planarization process such as CMP. CMP can also be used to remove the portion of gate spacer 110 directly above the dummy gate 108. Removing the gate spacer 110 directly above the dummy gate 108 exposes the upper surface of the dummy gate 108, allowing the dummy gate 108 to be removed in subsequent process steps.

[0027] Now for reference Figure 4 The diagram illustrates a plurality of structures 100 having trenches 118 according to an embodiment. It should be understood that although three structures 100 are shown, embodiments of the invention contemplate forming a plurality of structures 100 on a single substrate wafer. Each structure 100 includes a gate region surrounded by an ILD. Figure 4 Three gate regions, gate region 1, gate region 2 and gate region 3, are shown to illustrate that there are more than one gate region on the silicon wafer because there is more than one structure 100 on the silicon wafer.

[0028] An etching process (e.g., a wet etching process) can be performed to remove dummy gates 108 from each gate region of structure 100 until the top surface of fin 106 is exposed, thereby forming trenches 118. Each trench 118 can extend from the top surface of gate spacer 110 to the top surface of fin 106. The etching process selectively removes dummy gate 108 material relative to fin 106 material. However, this process does not remove gate spacer 110. As a result, gate spacer 110 separates the first and second source / drain electrodes 112, 114 from the gate regions.

[0029] Now for reference Figure 5The diagram illustrates three gate regions of structure 100 according to an embodiment. A first high-k material 120 is randomly deposited into trenches 118 of structure 100 using a timed atomic layer deposition process. The first high-k material 120 is deposited onto the surface of the exposed fin 106 (in the gate region). Deposition times are chosen very close to the nucleation time to facilitate random nucleation. Due to the nucleation variation, some of the first high-k material 120 can be randomly deposited in some gate regions such that the first high-k material 120 can partially cover the surface of the exposed fin 106 (in the gate region). As a result, some gate regions can leave at least a portion of the top surface of the fin 106 exposed after the formation of the first high-k material 120. Furthermore, not all gate regions of structure 100 have the first high-k material 120. As illustrated, gate regions 1 and 3 contain the first high-k material 120, while gate region 2 does not. Furthermore, the randomness of nucleation cannot be repeated. As a result, another deposition of the first high-k material 120 may not produce the same results as gate regions 1 and 3, which include the first high-k material 120. It should be understood that a typical substrate wafer can include thousands or even millions of gate regions. Due to random nucleation, each substrate wafer can have millions of gate regions with different nucleations of the first high-k material 120. Consequently, no two wafers will have all their gate regions nucleated in the same way with the first high-k material 120.

[0030] The first high-k material 120 can be made of materials such as alumina (Al2O3). Other materials, such as lutetium oxide (Lu2O3), yttrium oxide (Y2O3), magnesium oxide (MgO), and other rare earth oxides, can also be used as the first high-k material 120. The composition, deposition process, and post-deposition treatment of the first high-k material 120 can have different effects on the threshold voltage (Vth) of the structure 100, depending on whether the structure 100 is a pFET or an nFET, the electrical properties of the interface between the high-k material 120 and the top surface of the fin 106 (including the formation of interface oxides during or after high-k material deposition), the composition of the gate metal, the polarity of the charge distributed through the high-k dielectric and at the high-k dielectric / fin interface, and other device and process parameters known in the art.

[0031] Now for reference Figure 6According to an embodiment, three gate regions of a structure 100 having a second high-k material 122 are shown. The second high-k material 122 is deposited into trenches 118 of the structure 100 using a timed atomic layer deposition process. The second high-k material 122 is deposited on the surface of the exposed fin 106 (in the gate region). Like the first high-k material 120, the second high-k material 122 can be randomly nucleated in different gate regions, thereby partially covering the surface of the exposed fin 106 (in the gate region). As a result, some gate regions can leave at least a portion of the surface of the exposed fin 106 (in the gate region) exposed after the formation of the second high-k material 122. Therefore, some gate regions may include both the first high-k material 120 and the second high-k material 122, while some gate regions may have either the first high-k material 120 or the second high-k material 122. Gate regions that do not have either the first high-k material 120 or the second high-k material 122 may also exist. As described above with reference to the first high-k material 120, the second high-k material 122 is also randomly nucleated in millions of gate regions on the substrate wafer.

[0032] During nucleation, the second high-k material 122 may overlap with the first high-k material 120. The second high-k material 122 may also be adjacent to the first high-k material 120. The second high-k material 122 may or may not be in contact with the first high-k material 120, even if the first and second high-k materials 120 and 122 are both located in the same gate region.

[0033] The second high-k material 122 may be made of materials such as lanthanum oxide (La₂O₃) or other materials (e.g., lutetium oxide (Lu₂O₃), yttrium oxide (Y₂O₃), magnesium oxide (MgO), and other rare earth oxides). Similar to the first high-k material 120, the second high-k material 122 may have different effects on Vth, depending on its composition and various other materials, devices, and process parameters known in the art. For example, the first high-k material 120 may increase Vth, while the second high-k material 122 may decrease Vth, and vice versa; or both may increase or decrease Vth.

[0034] Now for reference Figure 7According to an embodiment, a structure 100 having a gate dielectric layer 124 is shown with three gate regions. Using an atomic layer deposition process, the gate dielectric layer 124 is conformally deposited into the trench 118 of the structure 100 along the bottom and sidewalls of the trench 118. The gate dielectric layer 124 is deposited into the trench 118 in all open gate regions. The gate dielectric layer 124 is made of a high-k dielectric material. Non-limiting examples of suitable materials for the gate dielectric layer 124 include oxides, nitrides, oxynitrides, silicates (e.g., metal silicates), aluminates, titanates, nitrides, or any combination thereof. Examples of high-k materials include, but are not limited to, metal oxides, such as hafnium oxide (HfO2). The portion of the fin 106 below the gate dielectric layer 124 may also be referred to as a channel.

[0035] Now for reference Figure 8 According to an embodiment, a structure 100 having a metal gate 126 is shown with three gate regions. Once the gate dielectric layer 124 is deposited along the sidewalls and bottom of a trench 118, the trench 118 is filled with a conductive metal to form the metal gate 126. Non-limiting examples of the conductive material forming the metal gate 126 may include aluminum (Al), platinum (Pt), gold (Au), tungsten (W), titanium (Ti), or any combination thereof. The conductive metal may be deposited by a suitable deposition process, such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, physical vapor deposition, electroplating, thermal or electron beam evaporation, and sputtering.

[0036] In addition to forming the metal gate 126, structure 100 undergoes further processing to form contacts, including first and second source / drain contacts 128 and 130, such as... Figure 8 The gate region 1 is shown. First and second source / drain contacts 128, 130 extend through ILD 116 to first and second source / drain contacts 112, 114, respectively, and are formed within trenches. To remove ILD 116 and form contact trenches, a resist, such as a photoresist, can be deposited and patterned. An etching process, such as reactive ion etching, can be performed using the patterned resist as an etching mask to remove ILD 116 until the first and second top source / drain contacts 112, 114 are exposed. The contact trenches are filled with a conductive material or a combination of conductive materials to form the first and second source / drain contacts 128, 130. The conductive material filler can be a conductive metal, such as aluminum (Al), platinum (Pt), gold (Au), tungsten (W), titanium (Ti), or any combination thereof. The conductive material can be deposited using a suitable deposition process, such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, physical vapor deposition, electroplating, thermal or electron beam evaporation, or sputtering. Perform planarization processes, such as chemical mechanical planarization, to remove any conductive material from the surface of ILD116.

[0037] like Figure 8As illustrated, the resulting structure 100 includes a gate region, which may contain different combinations of a first high-k material 120 and a second high-k material 122. For example, some gate regions may include the first and second high-k materials 120, 122, as shown in gate region 1. Some gate regions may include only the first high-k material 120, as shown in gate region 2, or the second high-k material 122, as shown in gate region 3. Additionally, there may be gate regions (not shown) that do not include either the first high-k material 120 or the second high-k material 122. However, all gate regions include a gate dielectric layer 124. All gate regions may also include a metal gate 126.

[0038] In certain gate regions of a circuit device, first and / or second high-k materials 120, 122 are present, generating or promoting different threshold voltages in these gate regions. Different threshold voltages are achieved by combining first and second high-k materials 120, 122 with different chemical compositions with a gate dielectric layer 124. For example, the first high-k material 120 may be referred to as A, the second high-k material 122 as B, and the gate dielectric layer 124 as C. As described above, all gate regions include C. Some gate regions include only C. Some gate regions have a combination of C and A, some have a combination of C and B, and some have a combination of C, A, and B, where A and B may be adjacent to each other or even overlap. Therefore, different threshold voltages can be provided for a random set of transistors in a given chip. Randomness is achieved through the random nucleation of the first and / or second high-k materials 120, 122 in the gate regions of structure 100. As described above, the nucleation within the gate regions is random, allowing each substrate wafer to have different combinations of the first and / or second high-k materials 120, 122. Therefore, some gate regions include both the first and second high-k materials 120, 122, some gate regions include only one of the high-k materials, and some gate regions include neither the first high-k material 120 nor the second high-k material 122. Furthermore, a typical substrate wafer can include millions of gate regions. Due to the randomness of the high-k material nucleation, no two substrate wafers have the same deposition pattern of the first and second high-k materials 120, 122 in each gate region of both wafers. As a result, each gate region of each substrate wafer has a specific threshold voltage. These threshold voltages can be used as a PUF to identify each chip.

[0039] Now for reference Figure 9According to an embodiment, a top view illustrating the random nucleation of first and second high-k materials is shown. As described above, Vth refers to the “effective” or “extrapolated” threshold voltage of the transistor. For example, the effective threshold voltage can be the minimum voltage required to turn on the transistor and allow current (e.g., a measurable or detectable current) to flow from the first source-drain 112 to the second source-drain 114, and vice versa. Due to the randomness of the nucleation process, the nucleation of the first, second, or both high-k materials 120, 122 in the gate region provides for variations in the effective threshold voltage.

[0040] The cross-section in the top row shows a first high-k material 120 and a second high-k material 122 extending from the top to the bottom. In this exemplary embodiment, the composition of the high-k materials, along with the device and process parameters, results in the portion of the transistor channel covered by the second high-k material 122 having a "locally" higher threshold voltage than the portion of the transistor channel covered by the first high-k material 120. Therefore, the addition of the second high-k material 122 increases the effective threshold voltage of the transistor. This increase in the effective threshold voltage of the transistor is most significant when the second high-k material 122 spans the entire channel width of the transistor, as illustrated in the top row. This is because when the transistor's gate voltage is lower than the local threshold voltage associated with the channel region covered by the second high-k material 122 but higher than the local threshold voltage associated with the channel region covered by the first high-k material 120, the presence of the second high-k material 122 across the entire channel width effectively blocks current flow between the two source-drain regions 112, 114; however, in the embodiment illustrated in the bottom row, a path still exists between the two source-drain regions 112, 114 for current to pass through the local lower threshold voltage region of the channel covered by the first high-k material 120. Therefore, in the embodiment illustrated in the bottom row, the presence of the second high-k material 122 can result in a relatively small or negligible increase in the effective threshold voltage compared to the embodiment illustrated in the top row. However, in the embodiment illustrated in the bottom row, the presence of the second high-k material 122 can reduce the transistor's on-current by reducing the effective channel width available for current flow. In the embodiment illustrated in the top row, the presence of the second high-k material 122 can also reduce the transistor's on-current by increasing the transistor's effective threshold voltage.

[0041] The peripheral circuitry can detect transistor-to-transistor variability in effective threshold voltage, transistor-to-transistor variability in turn-on current (for a given gate bias or a series of gate biases), or a combination of both. As described above, in Figure 9In the embodiments shown in the top row, the threshold voltage sensing circuit is most effective in detecting changes caused by random nucleation; while in the embodiments shown in the two rows, the current sensing circuit is effective in detecting changes caused by random nucleation. The threshold voltage sensing peripheral circuitry can be based on, for example, a switched capacitor or other circuit configurations known in the art. The current sensing circuitry can be based on, for example, a sensing amplifier or other circuit configurations known in the art. Both methods of detecting variability between transistors are within the scope of this invention.

[0042] Embodiments of the present invention describe the use of nucleation effects from atomic layer deposition of high-k materials in the gate region to form random Vth for any field-effect transistor structure or other structure including a gate and a gate dielectric layer. The randomness of nucleation of the first and second high-k materials 120, 122 allows Vth to be used as a PUF, thus providing chip / wafer identification and verification.

[0043] Various embodiments of the invention have been described for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used herein is chosen to best explain the principles of the embodiments, their practical application, or improvements to existing technologies in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A method for forming a semiconductor structure, comprising: A plurality of gate regions are formed above the channel, and the plurality of gate regions are surrounded by gate spacers; The high-k material is randomly nucleated in the plurality of gate regions, wherein the high-k material partially covers the surface of the channel; as well as A gate dielectric layer is deposited in each of the plurality of gate regions, the gate dielectric layer covering the entire surface of the channel.

2. The method according to claim 1, wherein the high-k material is a first high-k material or a second high-k material.

3. The method according to claim 2, wherein, Only the first high-k material is embedded in the gate dielectric layer.

4. The method according to claim 2, wherein, Only the second high-k material is embedded in the gate dielectric layer.

5. The method of claim 2, wherein both the first high-k material and the second high-k material are embedded in the gate dielectric layer.

6. The method of claim 1, wherein random nucleation of the high-k material in the plurality of gate regions promotes random threshold voltages within the plurality of gate regions, the random threshold voltages within the plurality of gate regions serving as a physically clonable function.

7. The method according to claim 1, further comprising: A first source drain and a second source drain are formed, and the first source drain and the second source drain are separated from the plurality of gate regions by the gate spacer; A metal gate is deposited on top of the gate dielectric layer; An interlayer dielectric is deposited around the plurality of gate regions, the interlayer dielectric being on top of the first source drain and the second source drain; as well as The first source-drain contact and the second source-drain contact are formed.

8. A semiconductor structure, comprising: Multiple metal gates in multiple gate regions; The channel beneath the plurality of metal gates; A gate dielectric layer that separates the plurality of metal gates from the channel; as well as A high-k material is embedded in the gate dielectric layer, wherein both the high-k material and the gate dielectric layer are in direct contact with the channel, and wherein the high-k material is configured to obtain different dielectric combinations among the plurality of gate regions, such that each gate region has a different threshold voltage.

9. The semiconductor structure of claim 8, wherein the high-k material provides a threshold voltage variation in the plurality of metal gates.

10. The semiconductor structure according to claim 8, wherein the high-k material is a first high-k material or a second high-k material.

11. The semiconductor structure according to claim 10, wherein, Only the first high-k material is embedded in the gate dielectric layer.

12. The semiconductor structure according to claim 10, wherein, Only the second high-k material is embedded in the gate dielectric layer.

13. The semiconductor structure of claim 10, wherein both the first high-k material and the second high-k material are embedded in the gate dielectric layer.

14. The semiconductor structure of claim 10, wherein the first high-k material is made of aluminum oxide and the second high-k material is made of lanthanum oxide.

15. A semiconductor structure comprising: Multiple gate regions of multiple field-effect transistors, the multiple gate regions being above the channel; Multiple metal gates, wherein the multiple metal gates are separated from the channel by a gate dielectric layer; A high-k material is embedded in the gate dielectric layer and formed by random nucleation, wherein both the high-k material and the gate dielectric layer are in direct contact with the channel, and wherein the high-k material is configured to obtain different dielectric combinations among the plurality of gate regions, such that each gate region has a different threshold voltage. as well as An interlayer dielectric surrounding the plurality of gate regions.

16. The semiconductor structure of claim 15, wherein the high-k material is a first high-k material or a second high-k material.

17. The semiconductor structure according to claim 16, wherein, Only the first high-k material is embedded in the gate dielectric layer.

18. The semiconductor structure according to claim 16, wherein, Only the second high-k material is embedded in the gate dielectric layer.

19. The semiconductor structure of claim 16, wherein both the first high-k material and the second high-k material are embedded in the gate dielectric layer.

20. The semiconductor structure of claim 15, wherein the high-k material provides a threshold voltage variation in the plurality of metal gates.

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