Method for optimizing sleep state based on power management of Feiteng processor platform

Abstract

The application discloses a kind of based on the sleep state optimization method of power management of Feiteng processor platform, comprising the following steps: starting Feiteng processor platform, Feiteng processor platform enters working state;Set timeout duration value T1;Feiteng processor platform is set to sleep state, and Feiteng processor platform enters S1 energy-saving state;The duration that Feiteng processor platform is in S1 energy-saving state is calculated, if T1 is not 0, the duration that Feiteng processor platform is in S1 energy-saving state is over, from S1 energy-saving state switches to S3 energy-saving state;If wake-up source wakes up, Feiteng processor platform is converted to working state from S1 or S3 energy-saving state.The application saves the sleep wake-up time of Feiteng processor platform, and effectively reduces power consumption.

Description

Technical Field

[0001] This invention relates to the field of power management technology, and in particular to a method for optimizing sleep state based on power management of the Phytium processor platform. Background Technology

[0002] Current power management mode research mainly focuses on the S0, S1, S3, and S4 state modes defined by the Advanced Configuration and Power Interface (ACPI). S0 is the normal operating state mode with the highest power consumption, while S1, S3, and S4 are power-saving states, with power consumption decreasing in that order. When the processor platform performs sleep and wake-up operations, S1 involves fewer steps compared to other power-saving modes, allowing the platform to recover to its operating state more quickly and offering a low-latency advantage. The processor platform consumes less power in S3 power-saving mode than in S1, demonstrating a low-energy consumption advantage. Maintaining low latency while reducing power consumption to improve user experience and satisfaction has become a pressing issue in current operating system power management.

[0003] To address the aforementioned issues, patent CN114415820A discloses a power management method and system for a processor platform. The processor platform can transition from the S3 sleep state to the S4 hibernation state after a timeout, enabling the device to have a longer standby time. However, this invention does not consider the problem of slow wake-up speed of the processor platform, which results in a poor user experience. Summary of the Invention

[0004] The technical problem to be solved by this invention is to provide a sleep state optimization method based on power management of the Phytium processor platform, which saves the sleep-wake time of the Phytium processor platform and effectively reduces power consumption.

[0005] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0006] A method for optimizing sleep state based on power management of the Phytium processor platform includes the following steps:

[0007] The Phytium processor platform is powered on and enters working mode.

[0008] Set the timeout duration value T1;

[0009] Set the Phytium processor platform to hibernation mode, and the Phytium processor platform enters S1 power-saving mode;

[0010] Calculate the duration of the Phytium processor platform in the S1 power-saving state. If T1 is not 0, the Phytium processor platform will switch from the S1 power-saving state to the S3 power-saving state after the duration of the S1 power-saving state expires.

[0011] If awakened by a wake-up source, the Phytium processor platform switches from S1 or S3 power-saving state to working state.

[0012] Furthermore, after calculating the duration of the Phytium processor platform in the S1 power-saving state, it also includes: if T1 is 0, the Phytium processor platform remains in the S1 power-saving state.

[0013] Furthermore, setting the timeout duration value T1 specifically includes: if T1 is not 0 and the value of T1 is less than the lower limit of the preset valid range, the value of T1 is adjusted to the lower limit of the valid range; if T1 is not 0 and the value of T1 is greater than the upper limit of the preset valid range, the value of T1 is adjusted to the upper limit of the valid range.

[0014] Furthermore, the Phytium processor platform entering the S1 power-saving state includes the following steps:

[0015] The Phytium processor platform enters the suspend_prepare phase, freezing processes and preventing devices on the processor platform from registering new sub-devices.

[0016] When the Phytium processor platform enters the dpm_suspend_start stage, it stops all input and output operations of the device, marks the wake-up source device interrupt used to wake up the S1 power-saving state, saves the device's registers, and puts the device into the corresponding low-power state according to the bus type to which the device belongs.

[0017] When the Phytium processor platform enters the dpm_suspend_late stage, it suspends other devices and then resumes processing the suspended devices.

[0018] The Phytium processor platform enters the dpm_suspend_noirq stage, disabling all interrupts except for the wake-up source device interrupt, and saving the registers that were not saved in the previous stage.

[0019] Furthermore, the transition from the S1 power-saving state to the S3 power-saving state specifically includes: the Phytium processor platform enters the s2idle_loop stage to execute the state timeout mechanism. If no wake-up source is activated within the state timeout period, the Phytium processor platform actively exits the S1 power-saving state loop and then enters the S3 power-saving state.

[0020] Furthermore, the Phytium processor platform's timeout mechanism for entering the s2idle_loop stage includes the following steps:

[0021] The Phytium processor platform enters the pm_wakeup_pending stage to ensure that the Phytium processor platform is not woken up by any wake-up source during the power-saving state transition;

[0022] When the Phytium processor platform enters the s2idle_support stage, it checks whether the Phytium processor platform supports the function of switching from S1 power saving state to S3 power saving state. If it does not support it, it will remain in S1 power saving state.

[0023] The Phytium processor platform enters the timeout_s2idle stage, ensuring that the Phytium processor platform is in the timeout state of the S1 power-saving state;

[0024] The Phytium processor platform enters the timeout_s2idle_wait_jump stage. If the Phytium processor platform has no wake-up source and is not in a state timeout, the Phytium processor platform will wait until time T1.

[0025] When the Phytium processor platform enters the timeout_s2idle_jump stage, if the Phytium processor platform has no wake-up source and is in a state timeout, the Phytium processor platform will exit the S1 power-saving state loop.

[0026] The Phytium processor platform enters the PCIe_device_save stage to save the environment of the PCIe bus device before power loss.

[0027] The Phytium processor platform enters the PCIe_device_pd stage to perform a power-down operation on the PCIe bus devices.

[0028] Furthermore, entering S3 energy-saving mode includes the following steps:

[0029] The Phytium processor platform enters the suspend_disable_secondary_cpus stage, disabling all CPU slave cores except for the main core CPU0.

[0030] The Phytium processor platform enters the syscore_suspend phase, suspending devices registered in the system, and the system core goes offline.

[0031] The Phytium processor platform enters the suspend_ops_enter stage and enters the S3 power-saving state mode.

[0032] Furthermore, the Phytium processor platform's transition from S1 or S3 power-saving state to operating state includes the steps of switching from S1 power-saving state to operating state, specifically including:

[0033] The Phytium processor platform enters the dpm_resume_noirq stage and receives an interrupt;

[0034] The Phytium processor platform enters the dpm_resume_early stage, which restores the information of the device that was previously processed for other device recovery before performing the operation to restore other device information.

[0035] The Phytium processor platform enters the dpm_resume_end stage, and the device returns to its working state, performing normal input and output.

[0036] The Phytium processor platform enters the suspend_finish phase, unfreezing all processes.

[0037] Furthermore, the Phytium processor platform's transition from S1 or S3 power-saving state to operating state includes the steps of switching from S3 power-saving state to operating state, specifically including:

[0038] The Phytium processor platform enters syscore_resume, canceling the actions of the syscore_suspend phase;

[0039] The Phytium processor platform enters the suspend_enable_secondary_cpus stage, enabling all slave cores except CPU0;

[0040] The Phytium processor platform enters the dpm_resume_noirq stage and receives an interrupt;

[0041] The Phytium processor platform enters the dpm_resume_early stage, and before performing the operation to restore the information of other devices, it first restores the information of the device that was processed for the restoration of other devices.

[0042] The Phytium processor platform enters the dpm_resume_end stage, returns to the working state, and performs normal input and output.

[0043] The Phytium processor platform enters the suspend_finish phase, unfreezing all processes.

[0044] Furthermore, the wake-up source includes one or more of the following: i8042 PS / 2 keyboard, power button, and EC reporting event.

[0045] Compared with the prior art, the present invention has the following advantages:

[0046] This invention leverages the advantages of S1 and S3 power-saving states in traditional power management modes. By setting a timeout duration for the S1 power-saving state and selecting an appropriate power-saving state based on the timeout duration, it preserves the PCIe environment and ensures safe power-off of PCIe devices. This saves sleep wake-up time, improves user experience and satisfaction, and prevents the Phytium processor platform from being in a high-power consumption state, thereby reducing standby power consumption. Attached Figure Description

[0047] Figure 1 This is a flowchart of an embodiment of the present invention.

[0048] Figure 2 This is a flowchart illustrating the logic of transitioning from energy-saving state S1 to S3 in an embodiment of the present invention.

[0049] Figure 3 This is a flowchart of the state timeout mechanism in an embodiment of the present invention. Detailed Implementation

[0050] The present invention will be further described below with reference to the accompanying drawings and specific preferred embodiments, but this does not limit the scope of protection of the present invention.

[0051] Before introducing specific embodiments of the present invention, the relevant concepts will be explained:

[0052] S0 operating state: S0 Sleeping State as defined in the Advanced Configuration and Power Management Interface Specification, which is a normal operating state with almost no delay.

[0053] S1 Power Saving State: This is the S1 Sleeping State defined in the Advanced Configuration and Power Management Interface Specification. It is a lightweight sleep state in which all peripherals are powered off, while the CPU and interrupt controller continue to function.

[0054] S3 Power Saving State: This refers to the S3 Sleeping State defined in the Advanced Configuration and Power Management Interface specification. It suspends the CPU into memory mode. Except for memory keep-refresh mode, before hibernation, the CPU saves the state of all operating systems, open files, etc., in memory; all other CPU, cache, and chipset contents are lost. Upon waking, the CPU resumes its previous operating state from memory.

[0055] S4 Power Saving State: Defined as the S4 Sleeping State in the Advanced Configuration and Power Management Interface (ACPI) specification, it represents the sleep state with the lowest power consumption and longest wake-up latency supported by ACPI. To minimize power consumption, it is assumed that all devices on the hardware platform are powered off, and the platform context is maintained by being written to disk.

[0056] EC stands for Embedded Controller. Events such as power-on and laptop opening / closing can be reported to the operating system via the EC. The operating system then takes appropriate action based on the event type reported by the EC.

[0057] like Figure 1As shown, this embodiment provides a method for optimizing the sleep state based on the power management of the Phytium processor platform, which saves the sleep-wake time of the Phytium processor platform and effectively reduces power consumption. Specifically, it includes the following steps:

[0058] P1: Start the Phytium processor platform, and the Phytium processor platform enters working state S0;

[0059] P2: Set the timeout duration value T1;

[0060] P3: Sets the Phytium processor platform to hibernation mode, and the Phytium processor platform enters S1 power-saving mode;

[0061] P4: Calculate the duration of the Phytium processor platform in the S1 power-saving state. If the duration of the S1 power-saving state exceeds the timeout duration value T1, then the state has timed out.

[0062] P5: The Phytium processor platform maintains the S1 power-saving state or switches from the S1 power-saving state to the S3 power-saving state after the state timeout, based on the set timeout duration value T1.

[0063] P6: When the Phytium processor platform is in the S1 or S3 power-saving state, if it is woken up by a wake-up source, the Phytium processor platform will switch from the S1 or S3 power-saving state to the S0 working state.

[0064] Step P2 of this implementation includes the following steps:

[0065] P21: Set the timeout duration value T1 to 0, which means that the Phytium processor platform only supports the S1 power-saving state. In response to the timeout situation calculated in step P4, the Phytium processor platform will maintain the S1 power-saving state in step P5.

[0066] P22: When the timeout duration value T1 is set within the effective range [a, b], it indicates that the Phytium processor platform supports switching from S1 power-saving state to S3 power-saving state. In this embodiment, the effective range of the timeout duration value T1 is set to [30, 5400]. Within this range, the power consumption of the Phytium processor platform can be effectively reduced. Specifically, the following steps are included:

[0067] P221: When the timeout value T1 of the Phytium processor platform is set to less than a seconds, the system automatically defines the timeout value as the minimum value a. For example, if the user sets the timeout value of the Phytium processor platform to 19 seconds, the Phytium processor platform will automatically extend 19 seconds to 30 seconds according to the valid range of the timeout value.

[0068] P222: When the timeout value T1 of the Phytium processor platform is set to be greater than b seconds, the system automatically defines the timeout value as the maximum value b. For example, if the user sets the timeout value of the Phytium processor platform to 5600s, the Phytium processor platform will automatically reduce 5600s to 5400s according to the valid range of the timeout value.

[0069] like Figure 2 As shown, in this embodiment, step P3 specifically includes the following steps:

[0070] P31: The Phytium processor platform enters the suspend_prepare stage. The processor platform freezes processes, prohibits devices on the processor platform from registering new sub-devices to prevent race conditions, and prepares for switching the power state of the processor platform.

[0071] P32: The Phytium processor platform enters the dpm_suspend_start stage. The processor platform stops all input and output operations of the device, marks the wake-up source device interrupt used to wake up the S1 power-saving state, saves the device registers, and allows the device to enter an appropriate low-power state according to the bus type to which the device belongs.

[0072] P33: The Phytium processor platform enters the dpm_suspend_late stage. After suspending other devices, the processor platform will then suspend and process the suspended devices.

[0073] P34: The Phytium processor platform enters the dpm_suspend_noirq stage. The processor platform disables all interrupts except for the wake-up source device interrupt, saves the registers that were not saved in the previous stage, and the device enters the S1 power-saving state.

[0074] like Figure 3 As shown, in this embodiment, step P5 specifically includes the following steps:

[0075] P51: When T1=0 is set, the Phytium processor platform will maintain the S1 power-saving state and will no longer switch to the S3 power-saving state;

[0076] P52: If the timeout duration T1 is set within the range of [30, 5400] (when the timeout duration is less than 30, the Phytium processor platform will adjust the timeout duration to 30. When the timeout duration is greater than 5400, the Phytium processor platform will automatically adjust the value back to 5400), and the duration of the Phytium processor platform in the S1 power-saving state exceeds the timeout duration T1, the Phytium processor platform will switch from the S1 power-saving state to the S3 power-saving state.

[0077] In step P52, such as Figure 2As shown, the Phytium processor platform switches from S1 power-saving state to S3 power-saving state through the following steps:

[0078] P521: The Phytium processor platform enters the s2idle_loop stage. During the s2idle_loop stage, the Phytium processor platform executes a state timeout mechanism. If no wake-up source is found within the state timeout period, the Phytium processor platform actively exits the S1 power-saving state loop.

[0079] P522: The Phytium processor platform has entered S3 power-saving mode.

[0080] like Figure 2 As shown, in this embodiment, step P521 specifically includes the following steps:

[0081] P5211: The Phytium processor platform has entered the pm_wakeup_pending stage. This ensures that the Phytium processor platform is not woken up by any wake-up source during the power-saving state transition.

[0082] P5212: The Phytium processor platform enters the s2idle_support stage. This checks whether the Phytium processor platform supports the transition from S1 power-saving state to S3 power-saving state. If not, it maintains the S1 power-saving state.

[0083] P5213: The Phytium processor platform enters the timeout_s2idle phase. This ensures the Phytium processor platform remains in the timeout state of the S1 power-saving state.

[0084] P5214: The Phytium processor platform enters the timeout_s2idle_wait_jump phase. If the Phytium processor platform has no wake-up source and is not in a state timeout state, the Phytium processor platform waits until time T1 until the state timeout condition is met;

[0085] P5215: The Phytium processor platform enters the timeout_s2idle_jump stage. If the Phytium processor platform has no wake-up source and is in a state timeout state, the Phytium processor platform will exit the S1 power-saving state loop;

[0086] Considering that PCIe bus devices are powered down in S3 state, but not in S1 power-saving state, if the system directly transitions from S1 to S3 power-saving state, an anomaly will occur during the PCIe bus device environment preparation process, leading to platform wake-up failure. Figure 2 As shown, this embodiment further includes the following steps after step P5215:

[0087] P5216: The Phytium processor platform enters the PCIe_device_save stage. The Phytium processor platform saves the environment of the PCIe bus device before power loss, and performs environmental preprocessing work to prepare for the subsequent power-on of the bus device in the S3 power-saving state.

[0088] P5217: The Phytium processor platform enters the PCIe_device_pd stage. The Phytium processor platform performs a power-down operation on the PCIe bus devices. This is to handle the conflict caused by the PCIe bus devices remaining powered on in S1 power-saving mode, while the Phytium processor platform needs to power on the PCIe bus devices when resuming from S3 power-saving mode.

[0089] Steps P5216 and P5217 switch the PCIe environment from S1 power-saving state to S3 power-saving state, ensuring safe power-off of PCIe devices. This allows the processor platform to quickly return to its operating state with low latency, while also preventing the Phytium processor platform from remaining in a high-power-consumption state, thus reducing standby power consumption.

[0090] like Figure 2 As shown, in this embodiment, step P522 specifically includes the following steps:

[0091] P5221: The Phytium processor platform has entered the suspend_disable_secondary_cpus phase. The processor platform disables all CPU slave cores except for the master core CPU0.

[0092] P5222: The Phytium processor platform enters the syscore_suspend phase. The processor platform suspends devices registered in the system, and the system core is offline.

[0093] P5223: The Phytium processor platform enters the suspend_ops_enter stage, and the processor platform enters the S3 power-saving state mode.

[0094] In step P6 of this embodiment, the Phytium processor platform transitions from the S1 or S3 power-saving state to the S0 working state, specifically including the following steps:

[0095] P61: The Phytium processor platform switches from S1 power-saving state to S0 working state;

[0096] P62: The Phytium processor platform switches from S3 power-saving state to S0 working state.

[0097] like Figure 2 As shown in the upper half, in this embodiment, step P61 specifically includes the following steps:

[0098] P611: The Phytium processor platform enters the dpm_resume_noirq phase. The Phytium processor platform receives an interrupt, thus canceling the actions of the suspend_noirq phase;

[0099] P612: The Phytium processor platform enters the dpm_resume_early stage. Before performing the operation to restore information from other devices, the Phytium processor platform first restores the information of the devices that have been restored from other devices; this is the inverse operation of dpm_suspend_late.

[0100] P613: The Phytium processor platform enters the dpm_resume_end stage. The device returns to its working state, and the Phytium processor platform can perform normal input / output and execute the undo work of the dpm_suspend_start stage;

[0101] P614: The Phytium processor platform enters the suspend_finish phase. The Phytium processor platform unfreezes all processes, i.e., cancels the actions of the suspend_prepare phase.

[0102] like Figure 2 As shown in the right half of the diagram, in this embodiment, step P62 specifically includes the following steps:

[0103] P621: The Phytium processor platform enters syscore_resume. The Phytium processor platform cancels the actions of the syscore_suspend phase;

[0104] P622: The Phytium processor platform enters the suspend_enable_secondary_cpus stage. This enables all slave cores except CPU0, effectively canceling the suspend_disable_secondary_cpus stage.

[0105] P623: The Phytium processor platform enters the dpm_resume_noirq phase. The Phytium processor platform receives an interrupt, thus canceling the actions of the suspend_noirq phase;

[0106] P624: The Phytium processor platform enters the dpm_resume_early stage. Before performing the operation to restore information from other devices, the Phytium processor platform first restores the information of the device that was processing the restoration of information from other devices, which is the inverse operation of dpm_suspend_late;

[0107] P625: The Phytium processor platform enters the dpm_resume_end stage. The Phytium processor platform device returns to the working state, can perform normal input / output, and execute the undo work of the dpm_suspend_start stage;

[0108] P626: The Phytium processor platform enters the suspend_finish phase. The Phytium processor platform unfreezes all processes and cancels the actions of the suspend_prepare phase.

[0109] In summary, this invention provides a method for optimizing the sleep state in the power management of the Phytium platform. By setting a timeout duration value, the Phytium processor platform can switch from the S1 power-saving state to the S3 power-saving state while preserving the PCIe environment, ensuring the safe power-off of PCIe devices, and preventing the Phytium processor platform from remaining in the S1 power-saving state, thus greatly reducing the power consumption of the Phytium processor platform.

[0110] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Therefore, any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention should fall within the protection scope of the present invention.

Claims

1. A method for optimizing sleep state based on power management of the Phytium processor platform, characterized in that, Includes the following steps: The Phytium processor platform is powered on and enters working mode. Set the timeout duration value T1; Set the Phytium processor platform to hibernation mode, and the Phytium processor platform enters S1 power-saving mode; Calculate the duration of the Phytium processor platform in the S1 power-saving state. If T1 is not 0, the Phytium processor platform will switch from the S1 power-saving state to the S3 power-saving state after the duration of the S1 power-saving state expires. If awakened by a wake-up source, the Phytium processor platform switches from S1 or S3 power-saving state to working state.

2. The sleep state optimization method based on Phytium processor platform power management according to claim 1, characterized in that, The calculation of the duration of the Phytium processor platform in the S1 power-saving state also includes: if T1 is 0, the Phytium processor platform remains in the S1 power-saving state.

3. The sleep state optimization method based on Phytium processor platform power management according to claim 1, characterized in that, Setting the timeout duration value T1 specifically includes: if T1 is not 0 and the value of T1 is less than the lower limit of the preset valid range, adjust the value of T1 to the lower limit of the valid range; if T1 is not 0 and the value of T1 is greater than the upper limit of the preset valid range, adjust the value of T1 to the upper limit of the valid range.

4. The sleep state optimization method based on Phytium processor platform power management according to claim 1, characterized in that, The Phytium processor platform enters the S1 power-saving state through the following steps: The Phytium processor platform enters the suspend_prepare phase, freezing processes and preventing devices on the processor platform from registering new sub-devices. When the Phytium processor platform enters the dpm_suspend_start stage, it stops all input and output operations of the device, marks the wake-up source device interrupt used to wake up the S1 power-saving state, saves the device's registers, and puts the device into the corresponding low-power state according to the bus type to which the device belongs. When the Phytium processor platform enters the dpm_suspend_late stage, it suspends other devices and then resumes processing the suspended devices. The Phytium processor platform enters the dpm_suspend_noirq stage, disabling all interrupts except for the wake-up source device interrupt, and saving the registers that were not saved in the previous stage.

5. The sleep state optimization method based on Phytium processor platform power management according to claim 1, characterized in that, The transition from S1 power-saving state to S3 power-saving state specifically includes: the Phytium processor platform enters the s2idle_loop stage to execute the state timeout mechanism. If no wake-up source is activated within the state timeout period, the Phytium processor platform actively exits the S1 power-saving state loop and then enters the S3 power-saving state.

6. The sleep state optimization method based on Phytium processor platform power management according to claim 5, characterized in that, The Phytium processor platform's timeout mechanism for entering the s2idle_loop stage includes the following steps: The Phytium processor platform enters the pm_wakeup_pending stage to ensure that the Phytium processor platform is not woken up by any wake-up source during the power-saving state transition; When the Phytium processor platform enters the s2idle_support stage, it checks whether the Phytium processor platform supports the function of switching from S1 power saving state to S3 power saving state. If it does not support it, it will remain in S1 power saving state. The Phytium processor platform enters the timeout_s2idle stage, ensuring that the Phytium processor platform is in the timeout state of the S1 power-saving state; The Phytium processor platform enters the timeout_s2idle_wait_jump stage. If the Phytium processor platform has no wake-up source and is not in a state timeout, the Phytium processor platform will wait until time T1. When the Phytium processor platform enters the timeout_s2idle_jump stage, if the Phytium processor platform has no wake-up source and is in a state timeout, the Phytium processor platform will exit the S1 power-saving state loop. The Phytium processor platform enters the PCIe_device_save stage to save the environment of the PCIe bus device before power loss. The Phytium processor platform enters the PCIe_device_pd stage to perform a power-down operation on the PCIe bus devices.

7. The sleep state optimization method based on Phytium processor platform power management according to claim 5, characterized in that, Entering S3 power-saving mode involves the following steps: The Phytium processor platform enters the suspend_disable_secondary_cpus stage, disabling all CPU slave cores except for the main core CPU0. The Phytium processor platform enters the syscore_suspend phase, suspending devices registered in the system, and the system core goes offline. The Phytium processor platform enters the suspend_ops_enter stage and enters the S3 power-saving state mode.

8. The sleep state optimization method based on Phytium processor platform power management according to claim 1, characterized in that, The Phytium processor platform transitions from S1 or S3 power-saving state to operating state, including the steps involved in switching from S1 power-saving state to operating state, specifically: The Phytium processor platform enters the dpm_resume_noirq stage and receives an interrupt; The Phytium processor platform enters the dpm_resume_early stage, which restores the information of the device that was previously processed for other device recovery before performing the operation to restore other device information. The Phytium processor platform enters the dpm_resume_end stage, and the device returns to its working state, performing normal input and output. The Phytium processor platform enters the suspend_finish phase, unfreezing all processes.

9. The sleep state optimization method based on Phytium processor platform power management according to claim 1, characterized in that, The Phytium processor platform transitions from S1 or S3 power-saving state to operating state, including the steps involved in switching from S3 power-saving state to operating state, specifically: The Phytium processor platform enters syscore_resume, canceling the actions of the syscore_suspend phase; The Phytium processor platform enters the suspend_enable_secondary_cpus stage, enabling all slave cores except CPU0; The Phytium processor platform enters the dpm_resume_noirq stage and receives an interrupt; The Phytium processor platform enters the dpm_resume_early stage, and before performing the operation to restore the information of other devices, it first restores the information of the device that was processed for the restoration of other devices. The Phytium processor platform enters the dpm_resume_end stage, returns to the working state, and performs normal input and output. The Phytium processor platform enters the suspend_finish phase, unfreezing all processes.

10. The sleep state optimization method based on Phytium processor platform power management according to claim 1, characterized in that, The wake-up source includes one or more of the following: i8042 PS / 2 keyboard, power button, and EC reporting events.

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