A single-bit all-digital in-memory computing unit based on dynamic logic multiplication

Abstract

The application discloses a single-bit all-digital in-memory computing unit based on dynamic logic multiplication, comprising an input driving module, an SRAM array, a flip-flop array and an adder; each output end of the input driving module is connected to the input end of each row of SRAM storage units in the SRAM array, for providing an input excitation signal; each row of SRAM storage units is used for storing weight information; the input end of each row of flip-flops in the flip-flop array is connected to the output end of each row of SRAM storage units, for registering output results and performing synchronous operation; each input end of the adder is connected to the output end of each row of flip-flops, for performing accumulation operation on the output results after the synchronous operation; compared with in-memory computing in an analog domain and in-memory computing structure in a digital domain, the output results are accurate values and are less disturbed by noise sources; the dynamic logic adopted reduces the number of transistors used and reduces the area consumption compared with a traditional AND gate multiplier.

Description

Technical Field

[0001] This invention relates to a single-bit all-digital in-memory computing unit based on dynamic logic multiplication, belonging to the field of in-memory computing technology. Background Technology

[0002] In today's era of rapid development in artificial intelligence technology, convolutional neural networks (CNNs) are widely used as a highly efficient and fast type of neural network. However, due to the large amount of data exchange required, the efficiency of CNNs under the von Neumann architecture is relatively low. To reduce the impact of the memory wall on performance, in-memory computing techniques based on CNNs have emerged.

[0003] There are two types of in-memory computing architectures: digital-domain in-memory computing and analog-domain in-memory computing. Compared to analog-domain in-memory computing, digital-domain in-memory computing has many advantages, such as high precision and strong robustness. However, multiplication and addition in digital-domain in-memory computing architectures increase circuit area due to the addition of extra components, causing new technical problems. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a single-bit all-digital in-memory computing unit based on dynamic logic multiplication, which solves the technical problem that multiplication and addition in digital domain in-memory computing architectures increase the circuit area due to the addition of additional components.

[0005] To achieve the above objectives, the present invention is implemented using the following technical solution:

[0006] This invention provides a single-bit all-digital in-memory computing unit based on dynamic logic multiplication, including an input driver module, an SRAM array, a flip-flop array, and an adder;

[0007] Each output terminal of the input driving module is connected to the input terminal of each row of SRAM storage cells in the SRAM array to provide input excitation signals;

[0008] Each row of SRAM storage units is used to store weight information;

[0009] The input terminals of each row of triggers in the trigger array are connected to the output terminals of each row of SRAM storage units to store output results and perform synchronization operations.

[0010] Each input of the adder is connected to the output of each row of flip-flops, and is used to accumulate the output results after the synchronization operation.

[0011] Optionally, the SRAM array includes 4 rows and 1 column of SRAM storage cells, and the trigger array includes 4 rows and 1 column of triggers.

[0012] Optionally, the adder includes a full adder, a first half adder, and a second half adder;

[0013] The outputs of the first, second, and third row flip-flops are respectively connected to the addend A, addend B, and carry-in CIN of the full adder;

[0014] The output terminal of the four-row flip-flop and the local sum terminal S of the full adder are respectively connected to the addend terminal A and the addend terminal B of the first half adder;

[0015] The high-level carry terminal C of the full adder and the high-level carry terminal C of the first half adder are respectively connected to the adder terminal A and the adder terminal B of the second half adder;

[0016] The first half-adder outputs the OUT0 signal at its local sum terminal S, and the second half-adder outputs the OUT1 signal at its high carry terminal C and the OUT2 signal at its local sum terminal S.

[0017] Optionally, the SRAM memory cell includes NMOS transistors N1, NMOS transistors N2, NMOS transistors N3, NMOS transistors N4, PMOS transistor P1, inverter C1, inverter C2, and inverter C3;

[0018] The input terminal of inverter C1 and the output terminal of inverter C2 are connected and the connection point is denoted as storage node Q. The output terminal of inverter C1 and the input terminal of inverter C2 are connected and the connection point is denoted as storage node QB.

[0019] The gates of NMOS transistors N1 and N2 are both connected to word line WL, the drains of NMOS transistors N1 and N2 are connected to memory node Q and memory node QB respectively, and the sources of NMOS transistors N1 and N2 are connected to bit line BL and bit line BLB respectively.

[0020] The source, gate, and drain of the PMOS transistor P1 are connected to the power supply voltage VDD, the precharge signal PRE, and the source of the NMOS transistor N4, respectively. The gate and drain of the NMOS transistor N4 are connected to the storage node Q and the source of the NMOS transistor N3, respectively. The drain of the NMOS transistor N3 is connected to the ground zero voltage VSS, and the gate of the NMOS transistor N3 serves as the input terminal of the SRAM storage cell. The input terminal of the inverter C3 is connected to the source of the NMOS transistor N4 and the drain of the PMOS transistor P1, and the output terminal of the inverter C3 serves as the output terminal of the SRAM storage cell.

[0021] Optionally, the word line WL is used to load the write enable signal, and the bit line BL and bit line BLB are used to load weight data.

[0022] Optionally, the clock input terminal Clk of each row of the flip-flops is connected to the same clock signal CK, and the adder controls the accumulation operation of the output result after the synchronous operation corresponding to each row of SRAM storage cells according to the clock signal CK.

[0023] Compared with the prior art, the beneficial effects achieved by the present invention are as follows:

[0024] This invention provides a single-bit all-digital in-memory computing unit based on dynamic logic multiplication. Compared to in-memory computing in the analog domain, the output results of the digital domain in-memory computing structure are all accurate values ​​and are less affected by noise sources. Therefore, it has advantages in large-scale and high-precision applications. The dynamic logic used reduces the number of transistors used compared to traditional AND gate multipliers, thus reducing area consumption. At the same time, compared to the charging and discharging operations and quantization of calculation results using an ADC in the analog domain, it can reduce unnecessary power consumption during calculation. Attached Figure Description

[0025] Figure 1 This is a structural diagram of the single-bit all-digital in-memory computing unit based on dynamic logic multiplication provided in Embodiment 1 of the present invention;

[0026] Figure 2 This is a structural diagram of the SRAM storage unit provided in Embodiment 1 of the present invention. Detailed Implementation

[0027] The present invention will be further described below with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and should not be used to limit the scope of protection of the present invention.

[0028] Example 1:

[0029] like Figure 1 As shown, this invention provides a single-bit all-digital in-memory computing unit based on dynamic logic multiplication, including an input driver module, an SRAM array, a flip-flop array, and an adder. Each output terminal of the input driver module is connected to the input terminal of each row of SRAM storage cells in the SRAM array to provide input excitation signals. Each row of SRAM storage cells is used to store weight information (1 bit). The input terminals of each row of flip-flops in the flip-flop array are connected to the output terminals of each row of SRAM storage cells to register output results and perform synchronization operations. Each input terminal of the adder is connected to the output terminals of each row of flip-flops to perform accumulation operations on the output results after synchronization operations.

[0030] In this embodiment, the SRAM array includes 4 rows and 1 column of SRAM memory cells, and the flip-flop array includes 4 rows and 1 column of flip-flops. All flip-flops are D-type flip-flops. The clock input terminal Clk of each row of flip-flops is connected to the same clock signal CK. The adder controls the accumulation operation of the output result after the synchronous operation corresponding to each row of SRAM memory cells according to the clock signal CK.

[0031] The adder includes a full adder, a first half adder (Half Adder 1), and a second half adder (Half Adder 2). The outputs of the first, second, and third row flip-flops are connected to the addend A, addend B, and low-order carry CIN of the full adder, respectively. The outputs of the four row flip-flops and the local sum S of the full adder are connected to the addend A and addend B of the first half adder, respectively. The high-order carry C of the full adder and the high-order carry C of the first half adder are connected to the addend A and addend B of the second half adder, respectively. The local sum S of the first half adder outputs the OUT0 signal, and the high-order carry C and local sum S of the second half adder output the OUT1 and OUT2 signals, respectively.

[0032] like Figure 2 As shown, the SRAM memory cell includes NMOS transistors N1, NMOS transistors N2, NMOS transistors N3, NMOS transistors N4, PMOS transistor P1, inverter C1, inverter C2, and inverter C3.

[0033] The input terminal of inverter C1 is connected to the output terminal of inverter C2, and the connection point is denoted as storage node Q. The output terminal of inverter C1 is connected to the input terminal of inverter C2, and the connection point is denoted as storage node QB. The storage nodes Q and QB of the first, second, third, and fourth rows of SRAM memory cells are respectively denoted as Q... <3> QB <3> Q <2> QB <2> Q <1> QB <1> Q <0> QB <0> .

[0034] The gates of NMOS transistors N1 and N2 are both connected to word line WL. The drains of NMOS transistors N1 and N2 are connected to memory node Q and memory node QB, respectively. The sources of NMOS transistors N1 and N2 are connected to bit line BL and bit line BLB, respectively. Word line WL is used to load the write enable signal, and bit lines BL and BLB are used to load weight information. The word lines WL of the first, second, third, and fourth rows of SRAM memory cells are denoted as WL. <3> WL <2> WL <1> WL <0> The bit lines BL and BLB of the first, second, third, and fourth rows of SRAM memory cells are the same.

[0035] The source, gate, and drain of PMOS transistor P1 are connected to the power supply voltage VDD, the precharge signal PRE, and the source of NMOS transistor N4, respectively. The gate and drain of NMOS transistor N4 are connected to the storage node Q and the source of NMOS transistor N3, respectively. The drain of NMOS transistor N3 is connected to ground zero voltage VSS. The gate of NMOS transistor N3 serves as the input terminal of the SRAM storage cell (i.e., connected to the output terminal of the input driver module to obtain the input excitation signal IN). The excitation signals IN for the first, second, third, and fourth rows of SRAM storage cells are denoted as IN1, IN2, IN3, IN4, IN5, IN6, IN7, IN8, IN9, IN10 ... <3> IN <2> IN <1> IN <0> The input of inverter C3 is connected to the source of NMOS transistor N4 and the drain of PMOS transistor P1. The output of inverter C3 serves as the output of the SRAM memory cell (i.e., connected to the input of the flip-flop). NMOS transistors N3, NMOS transistor N4, and PMOS transistor P1 perform bit-by-bit multiplication. PMOS transistor P1 is used for pre-charging, while NMOS transistors N3 and NMOS transistor N4 are used for bit-by-bit multiplication and to determine whether the SRAM memory cell needs to be discharged. Inverter C3 is used for inversion and to increase drive.

[0036] The working modes of this embodiment include:

[0037] In storage mode, a normal SRAM write operation is performed. When the word line WL signal is high, two N-type transistors (NMOS transistor N1 and NMOS transistor N2) are turned on to write the preloaded weight information on bit lines BL and BLB into the SRAM storage cell. The written weight information is stored in the SRAM storage cell in the form of 1 bit.

[0038] After the storage mode is complete, the calculation mode begins. In calculation mode, the precharge signal PRE is first activated to precharge the signal to the power supply voltage VDD, followed by a discharge operation. Different combinations of the input excitation signal IN and the weight information stored in the SRAM memory cells will produce different calculation results. The calculation results are shown in Table 1.

[0039] Table 1: Calculation table of input excitation signal IN and weight information stored in SRAM memory cells

[0040] -1 -1 no VDD 0 -1 +1 no VDD 0 +1 -1 no VDD 0 +1 +1 yes VSS 1

[0041] As can be seen from Table 1, the path will only discharge when both N-type transistors (NMOS transistor N1 and NMOS transistor N2) are turned on, that is, when both the input excitation signal IN and the weight information W are "+1". After the discharge, the result of the bit-by-bit multiplication can be obtained through the inverter, and after entering the flip-flop, it will be synchronized and then the accumulation operation will be performed.

[0042] This invention provides a single-bit all-digital in-memory computing unit based on dynamic logic multiplication. This structure supports multiplication and accumulation operations on binarized input excitation signals and weight information in neural networks, i.e., it supports BNN-type networks. In the binarized network, "+1" is represented by VDD and "-1" by VSS. Addition in the binarized network can be viewed as counting the number of "+1" values. This design uses dynamic logic for multiplication, employing five transistors to complete bitwise multiplication, and then using flip-flops for synchronous timing. Finally, the four SRAM cells in each column are added together using a full adder to obtain the final accurate 3-bit multiplication and accumulation result.

[0043] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A single-bit all-digital in-memory computing unit based on dynamic logic multiplication, characterized in that, Includes input driver module, SRAM array, flip-flop array, and adder; Each output terminal of the input driving module is connected to the input terminal of each row of SRAM storage cells in the SRAM array to provide input excitation signals; Each row of SRAM storage units is used to store weight information; The input terminals of each row of triggers in the trigger array are connected to the output terminals of each row of SRAM storage units to store output results and perform synchronization operations. Each input of the adder is connected to the output of each row of flip-flops, and is used to accumulate the output results after the synchronization operation. The SRAM array comprises 4 rows and 1 column of SRAM storage cells, and the flip-flop array comprises 4 rows and 1 column of flip-flops. The adder includes a full adder, a first half adder, and a second half adder; The outputs of the first, second, and third row flip-flops are connected to the addend A, addend B, and carry-in CIN of the full adder, respectively. The output of the four-row flip-flop and the local sum S of the full adder are connected to the addend A and addend B of the first half adder, respectively. The high-level carry terminal C of the full adder and the high-level carry terminal C of the first half adder are respectively connected to the adder terminal A and the adder terminal B of the second half adder; The first half-adder outputs the OUT0 signal from its local sum terminal S, and the second half-adder outputs the OUT1 signal from its high carry terminal C and the OUT2 signal from its local sum terminal S. The SRAM memory cell includes NMOS transistors N1, NMOS transistors N2, NMOS transistors N3, NMOS transistors N4, PMOS transistor P1, inverter C1, inverter C2, and inverter C3; The input terminal of inverter C1 and the output terminal of inverter C2 are connected and the connection point is denoted as storage node Q. The output terminal of inverter C1 and the input terminal of inverter C2 are connected and the connection point is denoted as storage node QB. The gates of NMOS transistors N1 and N2 are both connected to word line WL, the drains of NMOS transistors N1 and N2 are connected to memory node Q and memory node QB respectively, and the sources of NMOS transistors N1 and N2 are connected to bit line BL and bit line BLB respectively. The source, gate, and drain of the PMOS transistor P1 are connected to the power supply voltage VDD, the precharge signal PRE, and the source of the NMOS transistor N4, respectively. The gate and drain of the NMOS transistor N4 are connected to the storage node Q and the source of the NMOS transistor N3, respectively. The drain of the NMOS transistor N3 is connected to the ground zero voltage VSS, and the gate of the NMOS transistor N3 serves as the input terminal of the SRAM storage cell. The input terminal of the inverter C3 is connected to the source of the NMOS transistor N4 and the drain of the PMOS transistor P1, and the output terminal of the inverter C3 serves as the output terminal of the SRAM storage cell.

2. The single-bit all-digital in-memory computing unit based on dynamic logic multiplication according to claim 1, characterized in that, The word line WL is used to load the write enable signal, and the bit line BL and bit line BLB are used to load weight data.

3. The single-bit all-digital in-memory computing unit based on dynamic logic multiplication according to claim 1, characterized in that, The clock input terminal Clk of each row of the flip-flops is connected to the same clock signal CK. The adder controls the accumulation operation of the output result after the synchronous operation corresponding to each row of SRAM memory cells according to the clock signal CK.

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