A multifunctional computing device and method for floating-point data

Abstract

This invention discloses a multifunctional floating-point data processing device and method. The device employs a three-stage pipeline structure. The first part performs data preprocessing, exponentiation, and mantissa multiplication; it includes an enable control module, a data preprocessing module, a data extraction module, a sign bit processing module, a data normalization module, an exponent preprocessing module, a path determination module, a mantissa booth encoding module, a Wallace tree compression module, a special data detection module, and a first-stage DFF. The second part performs floating-point mantissa addition. The third part performs exponentiation, mantissa calculation, rounding, special value handling, and exception flag handling, and outputs the final result. The device and method disclosed in this invention utilize resource reuse technology to improve resource reuse rate, thereby reducing hardware resource overhead and enabling the support of multiple computational functions with relatively small hardware resources.

Description

Technical Field

[0001] This invention relates to the field of floating-point arithmetic technology in microprocessors, and particularly to a multifunctional arithmetic device and method for floating-point data. Background Technology

[0002] In applications such as high-definition image processing, modern mobile communications, and radar signal processing, numerous multiplication-accumulation operations are involved, requiring ultra-high-performance signal processors to process large amounts of data. Simultaneously, these applications demand extremely high computational accuracy and real-time performance. Floating-point numbers offer high representational precision and a large dynamic range, and floating-point operations can meet the high-precision and real-time requirements of modern microprocessors. Therefore, floating-point multiplication-accumulation capability has become a crucial characteristic for evaluating the performance of DSP chips. Floating-point fused multiplication-accumulation combines addition and multiplication into a single operation, improving accuracy and throughput. It has become the mainstream architecture for floating-point processing units, and fast, high-performance, and high-precision floating-point multipliers-accumulators have become a research hotspot both domestically and internationally.

[0003] Floating-point multiply-add operations combine the result of a floating-point multiplication with another operand, obtaining the final result without intermediate rounding steps. This improves precision while reducing the overall execution latency of the floating-point multiply-add operation. Due to the complexity of floating-point arithmetic, the hardware resource overhead and latency of multiply-add operations pose significant challenges to hardware implementation. Furthermore, high-precision applications sometimes require support for denormalized data computation, multiple rounding modes, and exception handling. This leads to a significant increase in the hardware resources required for floating-point multiply-add operations. Using fewer hardware resources while meeting timing requirements has become a current research focus. Since standalone floating-point multiply-add operations have high hardware overhead, designing multifunctional floating-point computing devices holds significant application potential. Summary of the Invention

[0004] To address the aforementioned technical problems, this invention provides a multifunctional computing device and method for floating-point data. By utilizing resource reuse technology, the resource reuse rate is improved, thereby reducing hardware resource overhead and enabling the support of multiple computing functions with relatively small hardware resources.

[0005] To achieve the above objectives, the technical solution of the present invention is as follows:

[0006] A multi-functional floating-point data processing device, which adopts a three-stage pipeline structure, divided into three parts, each of which is a one-stage pipeline;

[0007] The first part completes data preprocessing, exponentiation, and mantissa multiplication; including an enable control module, a data preprocessing module, a data extraction module, a sign bit processing module, a data normalization processing module, an exponent preprocessing module, a path judgment module, a mantissa booth encoding module, a Wallace tree compression module, a special data detection module, and a first-level DFF;

[0008] The second part completes the addition operation of floating-point mantissas; including the addend path, partial product path, and Close path;

[0009] The third part completes the exponent calculation, mantissa calculation, rounding operation, special value handling, exception flag handling, and outputs the final result; it includes a sign bit calculation module, an exponent calculation module, a 48-bit composite adder module, a mantissa prenormalization processing module, a denormalized number processing module, a result preprocessing module, a result postprocessing module, a result concatenation module, and a third-level DFF.

[0010] In the above scheme, the adder path includes a multiplication carry module, a 28-bit shift module 1, a 28-bit shift module 2, a 75-bit compression module, and a rounding bit processing module 1.

[0011] In the above scheme, the partial product path includes a 49-bit shift module, a 74-bit compression module, and a rounding bit processing module 2.

[0012] In the above scheme, the Close path includes a 4-bit shift module, a 49-bit compression module 1, a 49-bit compression module 2, a leading zero prediction module, a leading zero detection module, a comparison module, a data selection module 1, a data selection module 2, a normalization and rounding bit processing module 1, a normalization and rounding bit processing module 2, and a second-level DFF.

[0013] In the above scheme, the input data of the device is an opcode, an opcode enable, a rounding mode, and three operands fa, fb, and fc, where operands fa, fb, and fc can be positive, negative, normalized, or denormalized numbers.

[0014] In the above scheme, the device is used to perform seven operations on operands fa, fb, and fc: floating-point multiplication and addition, multiplication and subtraction, negative multiplication and addition, negative multiplication and subtraction, addition, subtraction, and multiplication.

[0015] In the above scheme, the data normalization processing module includes a leading zero detection module 1, a leading zero detection module 2, a leading zero detection module 3, an 8-bit addition module, and a 24-bit left shift module.

[0016] A multi-functional floating-point data arithmetic method, employing a multi-functional floating-point data arithmetic device as described above, includes the following process:

[0017] Phase 1: Input data includes opcode, opcode enable, rounding mode, fa, fb, and fc. The opcode and opcode enable enter the enable control module for opcode decoding to determine which of the seven operations the signal represents, and simultaneously obtain the enable signal. The rounding mode directly enters the first-level DFF. fa, fb, and fc enter the data preprocessing module, which performs data preprocessing on the input fa, fb, and fc based on the enable signal output by the enable control module.

[0018] The processed fa, fb, and fc are then output to the data extraction module to extract the sign bit, exponent bit, and mantissa bit of the data. Then, the exponent and mantissa bits of fa, fb, and fc output by the data extraction module are normalized to convert the denormalized number into a normalized number representation. The process is then divided into sign preprocessing, exponent preprocessing, mantissa preprocessing, and special data detection.

[0019] Next, path determination is performed. The path determination module makes a judgment based on the difference between the output of the sign bit processing module and the exponent preprocessing module. Based on the judgment conditions, it processes the data and outputs the addend path valid signal, the partial product path valid signal, and the Close path valid signal.

[0020] Finally, the valid enable signal output by the enable control module is used as the control enable. When valid, the output results of the input rounding mode, enable control module, data extraction module, sign bit processing module, data normalization processing module, exponent preprocessing module, path judgment module, mantissa booth encoding module, Wallace tree compression module and special data detection module are stored in the first-level DFF. When invalid, the original data of the first-level DFF remains unchanged.

[0021] The second stage consists of three paths: the addend path, the partial product path, and the Close path.

[0022] For the adder path, firstly, the 48-bit Sum and 48-bit Carry output from the Wallace tree compression module of the first-level DFF register are operated on. Using the multiplication carry module, the most significant bit of Sum and Carry is ORed and output. Then, the 48-bit Sum and 48-bit Carry are shifted using 28-bit shift module 1 and 28-bit shift module 2. After shifting, the result is compressed using the 75-bit compression module and the mantissa of fc output from the data normalization processing module of the first-level DFF register. Finally, the carry value, 48-bit Sum, 48-bit Carry, lower 27-bit Sum, and lower 27-bit Carry are output. The lower 27-bit Sum and Carry are transmitted to the rounding bit processing module 1 to obtain the rounding bit S and mantissa carry for addition and subtraction operations, respectively.

[0023] For partial product paths, a 49-bit shift module is used to right-shift the mantissa bits of the data normalization processing module output from the first-level DFF register, resulting in a 74-bit shifted result. This shifted result is then compressed using a 74-bit compression module and either the 48-bit Sum and 48-bit Carry output from the Wallace tree compression module of the first-level DFF register, or by inverting the two data values. The final output is the carry value, 48-bit Sum, 48-bit Carry, lower 26-bit Sum, and lower 26-bit Carry. The lower 26-bit Sum and Carry are transmitted to the rounding bit processing module 2 to obtain the rounding bits S and mantissa carry for addition and subtraction operations, respectively.

[0024] For the Close path, firstly, a 4-bit shift module is used to shift the mantissa of the data normalization processing module output from the first-level DFF register, resulting in a 27-bit shifted result. Then, this result is transmitted to 49-bit compression modules 1 and 2 respectively, where it is compressed with the 48-bit Sum and 48-bit Carry output from the Wallace tree compression module of the first-level DFF register. This results in two sets of 49-bit Sum and 49-bit Carry, which are then output. Finally, the Sum and Carry output from 49-bit compression module 1 are transmitted to the leading zero prediction module and the comparison module. The leading zero prediction module outputs a 49-bit leading zero. The 0-predictive encoding is passed to the leading 0 detection module, which outputs the number of high-order 0s. The comparison module operates on the Sum and Carry outputs of the 49-bit compression module 1 to obtain an enable signal that is larger than the output of the 4-bit shift module. Then, the data selection modules 1 and 2 select the outputs of the 49-bit compression modules 1 and 2 based on the signal generated by the comparison module. Finally, the normalization and rounding bit processing modules 1 and 2 operate on the outputs of the data selection modules 1 and 2 respectively to obtain the carry value, the 48-bit Sum, the 48-bit Carry, the rounding bit S for the subtraction operation, and the mantissa carry.

[0025] Finally, the valid enable signal output by the enable control module of the first-level DFF register is used as the enable signal. When valid, the output results of the input rounding mode, enable control module, data extraction module, sign bit processing module, exponent preprocessing calculation module, path judgment module, and special data detection module of the first-level DFF register, as well as the output signal of the multiplication carry module and the leading zero detection module of the second-level DFF register (the Close path calculation result is 0), and the comparison signal output by the comparison module are registered in the second-level DFF. The three enable signals output by the path judgment module of the first-level DFF register are used as enable signals, and the carry values ​​generated by the three paths, the 48-bit Sum, the 48-bit Carry, the rounding bit S and mantissa carry of the addition operation, and the rounding bit S and mantissa carry of the subtraction operation are registered in the second-level DFF. When all the above enable signals are invalid, the original data of the second-level DFF remains unchanged.

[0026] The third stage: The third stage is divided into symbolic calculation, exponent calculation, mantissa calculation, and final data processing;

[0027] The sign bit calculation module first calculates the sign bit of the special data based on the special data indication signal generated by the special data detection module in the second-level DFF register and the sign bit of the data extraction module. If the data is not special, the sign bit is calculated for the three paths in the second stage. The selection calculation is performed based on the enable signal of the three paths output by the path judgment module in the second-level DFF register, and finally the sign bit result is output.

[0028] For mantissa calculation, firstly, a 48-bit composite adder module is used to perform a composite addition operation on the 48-bit Sum and 48-bit Carry stored in the second-stage DFF register. The 48-bit Sum and 48-bit Carry are then added together to obtain a carry-in value of 1 and a 48-bit Sum1. Next, the 48-bit Sum and 48-bit Carry are added together and then 1 is added to obtain a carry-out value of 2 and a 48-bit Sum2. Finally, the two sets of data are output and transmitted to the mantissa prenormalization processing module. The mantissa prenormalization processing module operates based on the rounding bits S and mantissa carry from the addition and subtraction registers in the second-stage DFF register, the subtraction signal output from the sign bit processing module in the second-stage DFF register, and the multiplication carry output from the multiplication carry module in the second-stage DFF register. Finally, the valid signals shifted right by 2 bits, shifted right by 1 bit, shifted left by 1 bit, the most significant bit of Sum, the second most significant bit of Sum, and the mantissa calculation result are output.

[0029] The exponent calculation is performed using the exponent calculation module and is divided into two types of calculations: when the Close path valid signal output by the path judgment module of the second-level DFF register is valid, the exponent calculation is performed for the Close path; when the addend path valid signal or the partial product path valid signal output by the path judgment module of the second-level DFF register is valid, the exponent calculation is performed for the Far path; finally, the exponent result is output.

[0030] The final data processing involves operating on the exponent result output by the exponent calculation module and the mantissa result output by the mantissa prenormalization module, and finally outputting the exponent and mantissa results in denormalized number representation; then the sign bit output by the sign bit calculation module, the exponent and mantissa output by the denormalization module, and the mantissa prenormalization module are transmitted to the result preprocessing module.

[0031] The result preprocessing module processes the special data based on the special data indication signal generated by the special data detection module in the second-level DFF register to obtain the exponent, mantissa, and NV anomaly flag. If it is not a special value, the exponent and mantissa output by the exponent calculation module and the mantissa prenormalization processing module, the exponent and mantissa results from the denormalization processing module, the rounding mode in the second-level DFF register, and the sign bit generated by the sign bit calculation module are used as operation data for boundary value processing. The exponent, mantissa, rounding bits, and OF and UF anomaly flags of the first result processing are output and transmitted to the result postprocessing module.

[0032] The post-processing module performs five rounding operations based on the mantissa and rounding bits output by the result preprocessing module, the sign bit generated by the calculation module, and the rounding mode of the second-level DFF register, while generating an NX exception flag. Then, it performs boundary checks on the rounded result to determine whether there is overflow or underflow and outputs the exception flag, exponent, and mantissa to the result concatenation module.

[0033] The result concatenation module merges the exponent, mantissa, and exception flags generated by the result preprocessing module and the exception flags, exponent, and mantissa output by the result postprocessing module. If the data is special, the exponent, mantissa, and exception flags output by the result preprocessing module are used; otherwise, the exponent, mantissa, and exception flags output by the result postprocessing module are used. Finally, the result is concatenated with the output of the sign bit calculation module to obtain the final calculation result and four exception flags, which are then transmitted to the third-level DFF.

[0034] The third-level DFF uses the valid enable signal output by the enable control module stored in the first-level DFF register as the enable signal. When valid, it is used to store the calculation results and exception flag data generated by the result splicing module. When invalid, it retains the data.

[0035] Through the above technical solution, the multifunctional floating-point data processing device and method provided by the present invention have the following beneficial effects:

[0036] This device integrates floating-point multiplication-addition, multiplication-subtraction, negative multiplication-addition, negative multiplication-subtraction, addition, subtraction, and multiplication operations, using a single floating-point multiplication-addition calculation unit to implement all functions. This calculation unit can be used as a parameterized calculation unit, supporting floating-point data formats with m-bit exponents and n-bit mantissas. This parameterized calculation unit can be implemented by adjusting the bit width.

[0037] This invention incorporates denormalized number calculation, rounding mode processing, and exception flag processing into the multifunctional computing device. Firstly, it integrates denormalized operand processing into the normalized data stream to maximize hardware resource sharing and improve resource reuse.

[0038] This device improves resource reuse rate by reducing the complexity of rounding mode processing and by reducing the complexity of exception flag processing. This multi-functional floating-point computing device utilizes resource reuse technology in multiple places during its implementation to improve resource reuse rate and thus reduce hardware resource overhead, enabling a computing device with multiple functions to be supported with relatively small hardware resources. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below.

[0040] Figure 1 Schematic diagram of five rounding modes: (a) RNE; (b) RTZ; (c) RDN; (d) RUP; (e) RMM.

[0041] Figure 2 This invention provides a schematic diagram of the overall framework of a multifunctional floating-point data processing device.

[0042] Figure 3 This is a schematic diagram of the standardization processing module structure;

[0043] Figure 4 This is a schematic diagram of the Booth encoder circuit structure;

[0044] Figure 5 The input is a Wallace tree point graph with 13 partial products. Detailed Implementation

[0045] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0046] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to specific embodiments, accompanying drawings, and tables. The specific implementation will be illustrated using the IEEE 754-2008 standard floating-point single-precision format as an example. This example can be extended to floating-point data format operations with an m-bit exponent and n-bit mantissa.

[0047] First, we introduce floating-point data, rounding modes, and exception flag handling. The specific representation of floating-point data is shown in Table 1. Besides normalized numbers, some special values ​​have specific representations in the standard. These special values ​​include positive 0, negative 0, positive infinity (+Inf), negative infinity (-Inf), denormalized numbers, and Not-a-N (NaN). Denormalized numbers and Not-a-N are handled differently in floating-point arithmetic. General floating-point arithmetic does not support denormalized number operations, but this device does, resulting in higher arithmetic precision. Not-a-N can be represented as Quiet-NaN (QNaN) or Signaling-NaN (SNaN) based on its most significant bit. The exception flag settings differ for these two types of Not-a-N.

[0048] Table 1 Floating-point format data

[0049]

[0050] The specific meanings of the rounding modes are shown in Table 2. There are a total of 5 rounding modes: Round to Nearest Neighbor to Even (RNE), Round to Zero (RTZ), Round to Negative Infinity (RDZ), Round to Positive Infinity (RUP), and Round to Nearest Neighbor to Farthest Neighbor (RMM). The diagrams illustrating the specific meanings of the five rounding modes are shown below. Figure 1 As shown.

[0051] Table 2 Meaning of Rounding Mode

[0052]

[0053] There are four types of abnormal flags, and the specific handling methods are as follows:

[0054] (1) NV anomaly indicators:

[0055] If any operand is NaN, the output is Canonical-NaN, i.e., 0x7fc00000. If any operand is SNaN, the NV flag needs to be set. If floating-point multiplication-addition, multiplication-subtraction, negative multiplication-addition, and negative multiplication-subtraction operations appear in the form (+Inf)+(-Inf) and 0×Inf+c, the output is Canonical-NaN, and the NV flag is set. If floating-point addition and subtraction operations appear in the form (+Inf)+(-Inf), the output is Canonical-NaN, and the NV flag is set. If floating-point multiplication appears in the form 0×Inf, the output is Canonical-NaN, and the NV flag is set.

[0056] (2) OF Abnormal Indicators:

[0057] An overflow exception signal should be issued if and only if the target data range is unbounded and the resulting floating-point value exceeds the maximum finite number of the target format. The default result should be determined by the rounding direction attribute and the sign of intermediate results. RNE and RMM rounding use the sign of intermediate results to carry all overflows to Inf. RTZ rounding carries all overflows to the maximum finite number of the format with the sign of intermediate results. RDN rounding mode carries positive overflows to the maximum finite number of the format and negative overflows to -Inf. RUP rounding mode carries negative overflows to the least negative finite number of the format and positive overflows to +Inf.

[0058] In addition, under the default exception handling for overflow, the OF exception flag should be set and the NX exception flag signal should be emitted.

[0059] (3) UF anomaly indicators:

[0060] The IEEE 754-2008 floating-point standard offers two options: detection after rounding and detection before rounding. This invention employs detection after rounding. After rounding, results that are non-zero (within an unbounded data range) are strictly within ±b. emin When b is 2 and emin is the minimum normalization exponent -126, b emin It is the normalized number with the smallest absolute value.

[0061] The default exception handling for underflow must always deliver a rounded result, which could be zero, a denormalized number, or ±b. emin The absolute value ratio of b emin Small numbers can be represented as b emin or -b emin 0 and denormalized numbers are used to represent the output of this invention.

[0062] Under the default underflow exception handling, if the rounding result is inaccurate, the UF flag must be set and an NX exception must be sent. If the rounding result is accurate, no flag is set and no UF exception flag is signaled.

[0063] (4) NX anomaly flags:

[0064] If the result of a rounding operation is inaccurate, the NX exception flag must be sent.

[0065] The implementation scheme of this device will be described in detail below.

[0066] like Figure 2 As shown, this invention proposes a multifunctional floating-point data processing device that supports seven instruction operations: floating-point multiplication-addition, multiplication-subtraction, negative multiplication-addition, negative multiplication-subtraction, addition, subtraction, and multiplication, all implemented using a single multiplication-addition processing unit. The device employs a three-stage pipeline architecture, divided into three parts, each a single-stage pipeline. The first part performs data preprocessing, exponentiation, and mantissa multiplication. The second part performs floating-point mantissa addition. The third part performs exponentiation, mantissa calculation, rounding, special value handling, exception flag handling, and outputs the final result.

[0067] like Figure 2 As shown, this embodiment describes a multi-functional computing device for floating-point data. Its function is to take three operands A, B, and C as input and perform a multiplication-addition operation A*B+C on them. A, B, and C can be positive or negative numbers, and can be either normalized or denormalized. (In the diagram, fa represents A, fb represents B, and fc represents C.)

[0068] Part 1

[0069] The first part includes an enable control module, a data preprocessing module, a data extraction module, a sign bit processing module, a data normalization processing module, an exponent preprocessing module, a path judgment module, a mantissa booth encoding module, a Wallace tree compression module, a special data detection module, and a first-level DFF.

[0070] The enable control module decodes the opcode based on the input opcode and opcode enable signal to determine which of the seven operations it represents, and simultaneously obtains the enable signal.

[0071] The data preprocessing module preprocesses the input fa, fb, and fc based on the enable signal output by the enable control module. It performs the following preprocessing operations: floating-point multiplication and addition (no processing); floating-point multiplication and subtraction (inverting the sign bit of fc); floating-point negative multiplication and addition (inverting the sign bits of fa and fc); floating-point negative multiplication and subtraction (inverting the sign bit of fa); floating-point addition (fa and fc as operands, fb set to a floating-point constant 1); floating-point subtraction (fa and fc as operands, fb set to a floating-point constant 1, fc inverted); and floating-point multiplication (fa and fb as operands, fc set to 0). The preprocessed fa, fb, and fc are then output.

[0072] The data extraction module extracts the sign bit, exponent bit, and mantissa bit of the data based on the two operands output by the data preprocessing module. For normalized numbers, it pads the hidden mantissa bit with a 1; for denormalized numbers, it pads the hidden mantissa bit with a 0 to ensure data integrity. It then outputs the sign bit, exponent bit, and mantissa bit of fa, fb, and fc. Simultaneously, it checks the enable control module's output for a valid enable; if invalid, it sets all data in the sign bit, exponent bit, and mantissa bit to 0.

[0073] The sign bit processing module performs an XOR operation on the three operands based on the sign bits of fa, fb, and fc output by the data extraction module. This XOR operation is used as a subtraction enable signal as the output. When the sign bit is valid, it indicates subtraction; when it is invalid, it indicates addition.

[0074] The data normalization module normalizes the exponent and mantissa bits of fa, fb, and fc output by the data extraction module. The specific structure is as follows: Figure 3 As shown. It includes a leading zero detection module 1, a leading zero detection module 2, a leading zero detection module 3, an 8-bit addition module, and a 24-bit left shift module. Its functions are as follows:

[0075] Leading zero detection module 1 performs high-order zero detection on the mantissa of the input fa and outputs the number of high-order zeros.

[0076] Leading zero detection module 2 performs high-order zero detection on the mantissa of the input fb and outputs the number of high-order zeros.

[0077] Leading zero detection module 3 performs high-order zero detection on the mantissa of the input fc and outputs the number of high-order zeros.

[0078] The 8-bit addition module calculates the number of high-order zeros in fa, fb, and fc output by the leading zero detection modules 1, 2, and 3, and performs an operation with the 8-bit exponent bits of the input fa, fb, and fc. The exponent bits are then subtracted from the number of high-order zeros and 1 is added to obtain the normalized exponent bits of fa, fb, and fc, and the result is output.

[0079] The 24-bit left shift module uses the number of high-order zeros in fa, fb, and fc output by the leading zero detection modules 1, 2, and 3 as the shift value to perform a left shift operation on the mantissa of the input fa, fb, and fc, and outputs the normalized mantissa of fa, fb, and fc.

[0080] The combined function of the above 5 sub-modules is the function of the data normalization processing module, which is to complete the normalization processing of the exponent and mantissa of fa, fb and fc.

[0081] The exponent preprocessing module calculates the exponents of fa, fb, and fc output from the data normalization module. It adds the exponent of fa to the exponent of fb and subtracts the bias bit 127, naming the result 'a'. It then subtracts the exponents of fa, fb, and 127 from the exponent of fc, naming the result 'd'. Based on the value of 'd', it generates a valid signal with a larger exponent for fc. Finally, it calculates the absolute value of 'd'. If 'd' is positive, it remains unchanged; if negative, it is inverted and then incremented by 1. The final output includes 'a', the exponent difference 'd', the valid signal with a larger exponent for fc, and the absolute value of the exponent difference 'd'.

[0082] The path determination module makes a judgment based on the output of the sign bit processing module and the exponent difference d output of the exponent preprocessing module, and sets the output of the sign bit processing module to g. It then processes the data according to the judgment conditions in Table 3, outputting the addend path valid signal, the partial product path valid signal, and the Close path valid signal.

[0083] Table 3. Judgment conditions for the path judgment module

[0084]

[0085] The mantissa booth encoding module performs radix-4 booth encoding on the mantissa of fb output from the data normalization module. fb is then used as y. i For single-precision floating-point data i∈[23:0], for y i Extending by bits 0 yields i ∈ [24:-1]. For y... i Starting from the -1st bit, the mantissa is treated as a group of three bits at a time, shifting two bits each time, with one bit overlapping between different groups. As shown in Table 4, the booth decoding result z of the multiplier is obtained according to the radix-4 Booth encoding table. i ∈{-2,-1,0,1,2}, ultimately yielding 13 sets of z. i As a result, the circuit structure is as follows Figure 4 As shown. Then, the Bush decoding result z, obtained by multiplying the mantissa of fa by the multiplier, is processed by the data normalization module. iWhen the single signal is 1, the data remains unchanged. When the double signal is 1, the data is shifted left by one bit. When the negative signal is 1, the result is inverted and incremented by 1. If both the single and double signals are 0, the data remains unchanged. Finally, 13 sets of z-signals are generated. i The signal yields 13 partial product outputs.

[0086] Table 4. Booth Encoding Table

[0087] 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 0 1 1 0 0 0 1 1 2 0 1 0 1 0 0 -2 0 1 1 1 0 1 -1 1 0 1 1 1 0 -1 1 0 1 1 1 1 0 0 0 1

[0088] The Wallace tree compression module compresses the Wallace number based on the 13 partial product data output by the mantissa booth encoding module, with the structure as follows: Figure 5 As shown, the 13 partial products are compressed by a cascaded 3:2 compressor, and after passing through 5 levels of logic, the final 48-bit Sum and Carry results are obtained.

[0089] The special data detection module, based on the sign bit, exponent bit, and mantissa bit of fa, fb, and fc output by the data preprocessing module, detects positive 0, negative 0, positive infinity, negative infinity, SNAN, and QNAN. It outputs the corresponding indicator signals for these special values.

[0090] The first-level DFF uses the valid enable signal output by the enable control module as the control enable. When valid, it is used to store the output results of the input rounding mode, enable control module, data extraction module, sign bit processing module, data normalization processing module, exponent preprocessing module, path judgment module, mantissa booth encoding module, Wallace tree compression module, and special data detection module. When invalid, it keeps the original data unchanged.

[0091] Part Two

[0092] The second part includes the addend path, the partial product path, and the close path;

[0093] 1. Addend path

[0094] The adder path includes a multiplication carry module, a 28-bit shift module 1, a 28-bit shift module 2, a 75-bit compression module, and a rounding bit processing module 1.

[0095] The multiplication carry module operates on the highest bit of Sum and Carry output from the Wallace tree compression module stored in the first-level DFF register, performing an OR operation on the two operands and then outputting them.

[0096] 28-bit shift module 1 uses the exponent difference output by the exponent preprocessing module in the first-level DFF register as the shift value. When this shift value is greater than 28, the shift value is 28. Then, the 48-bit Sum output from the Wallace tree compression module in the first-level DFF register is bit-extended and padded with 0s, with the lower bits padded with 28 bits. Then, a right shift operation is performed to obtain a 76-bit shifted result. The lower 75 bits of the shifted Sum result are then output.

[0097] 28-bit shift module 2 uses the exponent difference output by the exponent preprocessing module in the first-level DFF register as the shift value. When this shift value is greater than 28, the shift value is 28. Then, the 48-bit Carry output by the Wallace tree compression module in the first-level DFF register is bit-expanded and padded with 0s, with the lower bits padded with 28 bits. Then, a right shift operation is performed to obtain a 76-bit shifted result. The lower 75 bits of the shifted Carry result are then output.

[0098] The 75-bit compression module operates on the mantissa bits of the outputs of the 28-bit shift module 1, the 28-bit shift module 2, and the data normalization processing module in the first-stage DFF register. It uses the sign bit processing module output from the first-stage DFF register as a subtraction enable signal; when valid, it inverts the outputs of the 28-bit shift module 1 and 28-bit shift module 2; otherwise, it performs no operation. Then, the three operands are compressed using a 3:2 compressor. During this operation, the sign bit processing module output from the first-stage DFF register is used as an increment signal; when valid, it considers the increment operation during 3:2 compression. This results in a 76-bit Sum and a 75-bit Carry. The most significant bit of the Sum is output as the carry value, and the remaining 75 bits of the Sum and Carry are split into a high 48 bits and a low 27 bits for output.

[0099] Rounding bit processing module 1 treats the lower 27 bits of Sum and Carry output by the 75-bit compression module as the mantissa and performs operations on them. Based on the sign bit processing module output by the first-level DFF register, during subtraction, it considers adding 1 in the least significant bit, and obtains the rounding bit S and mantissa carry for addition and subtraction operations respectively.

[0100] 2. Partial product path

[0101] The partial product path includes a 49-bit shift module, a 74-bit compression module, and a rounding bit processing module 2.

[0102] The 49-bit shift module uses the exponent difference output by the exponent preprocessing module in the first-level DFF register as the shift value. When this shift value is greater than 49, the shift value is 49. The mantissa bits of the fc output by the data normalization processing module in the first-level DFF register are padded with 0s, with 1 bit padded to the high-order bits and 49 bits padded to the low-order bits. Then, a right shift operation is performed to obtain a 74-bit shifted result, which is then output.

[0103] The 74-bit compression module operates on the 48-bit Sum and 48-bit Carry outputs from the 49-bit shift module and the Wallace tree compression module in the first-stage DFF register. It uses the sign bit processing module output from the first-stage DFF register as a subtraction enable signal; when valid, it inverts the output of the 49-bit shift module; otherwise, it performs no operation. Then, the three operands are compressed using a 3:2 compressor. During this operation, the sign bit processing module output from the first-stage DFF register is used as an increment signal. The increment operation is considered during the 3:2 compressor compression, ultimately resulting in a 75-bit Sum and a 74-bit Carry. The most significant bit of the Sum is output as the carry value, and the remaining 74 bits of the Sum and Carry are split into a high 48 bits and a low 26 bits for output.

[0104] Rounding bit processing module 2 treats the lower 26 bits of Sum and Carry output by the 74-bit compression module as the mantissa and performs operations on them. Based on the output of the sign bit processing module stored in the first-level DFF register, it obtains the rounding bit S and mantissa carry for addition and subtraction operations, respectively.

[0105] 3. Close path

[0106] The Close path includes a 4-bit shift module, a 49-bit compression module 1, a 49-bit compression module 2, a leading zero prediction module, a leading zero detection module, a comparison module, a data selection module 1, a data selection module 2, a normalization and rounding bit processing module 1, a normalization and rounding bit processing module 2, and a second-level DFF.

[0107] The 4-bit shift module shifts the mantissa bits of fc output from the data normalization processing module of the first-stage DFF register. First, it performs bit extension, padding with 0s: 2 bits for the high-order bits and 1 bit for the low-order bits, resulting in a 27-bit mantissa. Then, it uses the exponent difference output from the exponent preprocessing module of the first-stage DFF register as the shift value. The left and right shifts are controlled by comparing the magnitude of fc and the exponent fa*fb output from the first-stage DFF exponent preprocessing module; a left shift occurs when fc is larger, and a right shift occurs otherwise. Finally, the 27-bit shifted result is obtained and output.

[0108] The 49-bit compression module 1 operates on the 48-bit Sum and 48-bit Carry outputs from the 4-bit shift module output and the Wallace tree compression module output from the first-level DFF register. First, the output of the 4-bit shift module is inverted. Then, the three operands are compressed using a 3:2 compressor to finally obtain and output the 49-bit Sum and 49-bit Carry.

[0109] The 49-bit compression module 2 operates on the 48-bit Sum and 48-bit Carry outputs from the 4-bit shift module output and the Wallace tree compression module output from the first-level DFF register. First, the Sum and Carry are inverted. Then, the three operands are compressed using a 3:2 compressor, considering an increment operation during this operation, ultimately resulting in a 49-bit Sum and a 49-bit Carry, which are then output.

[0110] The comparison module compares the output of the 4-bit shifted module with the 48-bit Sum and 48-bit Carry output of the Wallace tree compression module stored in the first-level DFF, based on the Sum and Carry results output by the 49-bit compression module 1. The module determines the enable signal with the larger output result of the 4-bit shifted module. When the enable signal is active, the output of the 4-bit shifted module is larger; otherwise, the sum of Sum and Carry is larger.

[0111] Data selection module 1 uses the enable signal output by the comparison module as a judgment. If it is valid, it selects the Sum of 49-bit compression module 2 for output. If it is invalid, it selects the Sum of 49-bit compression module 1 for output.

[0112] Data selection module 2 uses the enable signal output by the comparison module as a criterion. If it is valid, it selects the Carry of 49-bit compression module 2 for output; if it is invalid, it selects the Carry of 49-bit compression module 1 for output.

[0113] The leading zero prediction module operates based on the Sum and Carry output by the 49-bit compression module 1. First, Carry is inverted, and then leading zero prediction encoding is performed based on these two operands, outputting a 49-bit leading zero prediction code.

[0114] The leading zero detection module performs high-order zero detection on the 49-bit leading zero prediction code output by the leading zero prediction module, outputs the number of high-order zeros, and generates an output signal that the Close path calculation result is 0 when all high-order zeros are 0.

[0115] Normalization and rounding bit processing module 1 first uses the output of the leading zero detection module as the shift value. When the value is greater than 49, the shift value is 49. It then performs a right shift operation on the Sum output by data selection module 1, resulting in a 97-bit shifted result. The high 48 bits of Sum are output directly, and the low 49 bits are rounded. Considering the increment operation, the rounding bit S and the mantissa carry are obtained.

[0116] Normalization and rounding bit processing module 2 first uses the output of the leading zero detection module as the shift value. When the value is greater than 49, the shift value is 49. It then performs a right shift operation on the Carry output by data selection module 2, resulting in a 97-bit shifted result. The high 48 bits of Carry are output directly, and the low 49 bits are rounded. Ignoring the increment operation, the rounding bit S and mantissa carry are obtained.

[0117] The second-level DFF uses the valid enable signal output from the enable control module registered in the first-level DFF as its enable signal. When valid, it registers the output results of the input rounding mode, enable control module, data extraction module, sign bit processing module, exponent preprocessing module, path judgment module, and special data detection module; when invalid, it keeps the data unchanged. It uses the three enable signals output from the path judgment module registered in the first-level DFF as its enable signals. When the addend path valid signal is valid, it registers the carry output from the 75-bit compression module, the 48-bit Sum and 48-bit Carry, the carry output from the multiplication carry module, and the rounding bits S and mantissa carry output from the rounding bit processing module 1 for addition and subtraction. When the partial product path valid signal is valid, it registers the carry from the 74-bit compression module, the 48-bit Sum and 48-bit Carry, and the rounding bit processing module... The output of the addition operation's rounding bit S and mantissa carry, and the subtraction operation's rounding bit S and mantissa carry; when the Close path valid signal is valid, the 48-bit Sum and 48-bit Carry output by the normalization and rounding bit processing module 1 and the normalization and rounding bit processing module 2 are stored, the output signal of the Close path calculation result being 0 output by the leading zero detection module, the comparison signal output by the comparison module, and the rounding bit S and mantissa carry of the subtraction operation and the rounding bit S and mantissa carry of the addition operation are represented by 0; when all are invalid, the data remains unchanged.

[0118] Part Three

[0119] The third part includes a sign bit calculation module, an exponent calculation module, a 48-bit composite adder module, a mantissa prenormalization processing module, a denormalized number processing module, a result preprocessing module, a result postprocessing module, a result concatenation module, and a third-level DFF.

[0120] The sign bit calculation module first calculates the sign bit of the special data based on the special data indication signal generated by the special data detection module in the second-level DFF register and the sign bit of the data extraction module. If it is not special data, the sign bit is calculated for the three paths in the second part. When the addend path valid signal output by the path judgment module in the second-level DFF register is valid, if fc is 0, the result is the XOR operation of the sign bits of fa and fb; if fc is not 0, the result is the sign bit of fc. When the partial product path valid signal output by the path judgment module in the second-level DFF register is valid, the result is the XOR operation of the sign bits of fa and fb. When the Close path valid signal output by the path judgment module in the second-level DFF register is valid, if the output result of the path is 0, the sign bit is 1 if the rounding mode is rounding to negative infinity, and 0 otherwise. If fc of the path is larger, the result is the sign bit of fc; otherwise, the result is the XOR operation of the sign bits of fa and fb.

[0121] The 48-bit composite adder module operates on the 48-bit Sum and 48-bit Carry stored in the second-stage DFF register. It adds the 48-bit Sum and 48-bit Carry together to obtain a carry-1 and a 48-bit Sum1; it adds the 48-bit Sum and 48-bit Carry together and then adds 1 to obtain a carry-2 and a 48-bit Sum2. Finally, it outputs both sets of data.

[0122] The mantissa prenormalization module first uses the subtraction signal output from the sign bit processing module in the second-stage DFF register as a selection signal. If valid, it selects the rounding bit S and mantissa carry from the subtraction register in the second-stage DFF register; otherwise, it selects the rounding bit S and mantissa carry from the addition register. Then, based on the valid mantissa carry, it selects the carry value 2 and 48-bit Sum2 output from the 48-bit composite adder module as operands; otherwise, it selects the carry value 1 and 48-bit Sum1 as operands, ultimately obtaining the carry value and the 48-bit Sum value. Then, it performs a logical AND operation between the obtained carry value and the carry value output from the multiplication carry module in the second-stage DFF register to obtain a valid signal that is right-shifted by 2 bits. If the subtraction signal output from the sign bit processing module in the second-stage DFF register is invalid and the carry value or the carry value output from the multiplication carry module in the second-stage DFF register is valid, it generates a valid signal that is right-shifted by 1 bit. Based on the valid subtraction signal, invalid Sum (most significant bit), and valid Sum (second most significant bit) output from the sign bit processing module of the second-level DFF register, a valid signal shifted left by 1 bit is generated. Finally, using the subtraction signal and the valid signal shifted right by 1 bit from the sign bit processing module of the second-level DFF register as signals, the rounding bit S is appended to the least significant bit of Sum, and the data is then processed to obtain the mantissa calculation result. Finally, the valid signals shifted right by 2 bits, shifted right by 1 bit, shifted left by 1 bit, the most significant bit of Sum, the second most significant bit of Sum, and the mantissa calculation result are output.

[0123] The exponent calculation module is divided into two categories: Close path exponent calculation and Far path exponent calculation, which are the exponent calculations for addend paths or partial product paths. For Close path exponent calculation, the path determination module in the second-level DFF register outputs a valid Close path signal, and the Leading Zero Detection module in the second-level DFF register outputs a Leading Zero Detection module. If the Leading Zero Detection module outputs a Leading Zero 0 signal, the Close path exponent result is 0. If the Leading Zero Detection module outputs a Leading Zero 0 signal, the Close path exponent result is 0. If the Leading Zero Detection module outputs a Leading Zero 0 signal, the following calculations are performed. Based on the comparison signal output by the exponent preprocessing module of the second-level DFF register, if the exponent fc is larger, subtract 2 from the number of leading zeros detected by the second-level DFF register's output module, and then add the absolute value of d output by the second-level DFF register's exponent preprocessing module. Conversely, subtract 2 from the number of leading zeros detected by the second-level DFF register's output module, use the highest bit of this data for high-bit extension and padding, then invert it as the leading zero correction data. Then, add the leading zero correction data to the larger exponent output by the second-level DFF register's exponent preprocessing module, and simultaneously calculate the larger exponent output by the second-level DFF register's exponent preprocessing module, add the leading zero correction data, and then add 1, thus producing results without adding 1 and results with adding 1. Data selection is performed based on the valid signal generated by the mantissa prenormalization processing module, which generates a left shift of 1 bit. If valid, the result without adding 1 is selected; if invalid, the result with adding 1 is selected as the exponent result output. When the addend path valid signal or the partial product path valid signal output by the path judgment module of the second-level DFF register is valid, the Far path exponent is calculated. First, when the partial product path valid signal output by the path determination module of the second-level DFF register is valid, the larger exponent output by the exponent preprocessing module of the second-level DFF register is selected as the intermediate result. When the addend path valid signal output by the path determination module of the second-level DFF register is valid, if fc is 0, the absolute value of d output by the exponent preprocessing module of the second-level DFF register minus the larger exponent output by the exponent preprocessing module of the second-level DFF register is selected as the intermediate result. If it is not 0, the larger exponent output by the exponent preprocessing module of the second-level DFF register is selected as the intermediate result. The result is incremented by 1, incremented by 2, decremented by 1, and decremented by 2 to obtain four temporary results. Then, based on the valid signals of the addend path and the partial product path output by the path judgment module of the second-level DFF register, the subtraction signal of the second-level DFF register, the valid signals of right shift by 1 bit, right shift by 2 bits, and left shift by 1 bit output by the mantissa prenormalization processing module, and the most significant and second most significant bits of Sum, the larger exponent, intermediate results, and four temporary results output by the exponent preprocessing module of the second-level DFF register are selected to finally obtain the exponent result output.

[0124] The denormalized number processing module uses the exponent result output by the exponent calculation module and whether it is less than 0 as a judgment signal. It calculates the absolute value of the exponent plus 1 as the shift value, performs a right shift operation on the output result of the mantissa prenormalization processing module, and finally outputs the exponent and mantissa results represented by the denormalized number.

[0125] The result preprocessing module processes the special data based on the special data indication signal generated by the special data detection module in the second-level DFF register to obtain the exponent, mantissa, and NV anomaly flag. If it is not a special value, it uses the exponent and mantissa output by the exponent calculation module and the mantissa prenormalization processing module, the exponent and mantissa results from the denormalization processing module, the rounding mode in the second-level DFF register, and the sign bit generated by the sign bit calculation module as operation data for boundary value processing, and outputs the exponent, mantissa, rounded mantissa, and OF and UF anomaly flags of the first result processing.

[0126] The result post-processing module performs five rounding operations based on the mantissa and rounding mantissa output by the result preprocessing module, the sign bit generated by the sign bit calculation module, and the rounding mode of the second-level DFF register. If a carry-in exists, the exponent is incremented by 1. When a rounding operation occurs, an NX exception flag is generated simultaneously. Afterwards, boundary checks are performed on the rounded result to determine if overflow or underflow exists, and the exception flag, exponent, and mantissa are output.

[0127] The result concatenation module merges the exponent, mantissa, and exception flags generated by the result preprocessing module with the exception flags, exponent, and mantissa output by the result postprocessing module. For special data, the exponent, mantissa, and exception flags output by the result preprocessing module are used; otherwise, the exponent, mantissa, and exception flags output by the result postprocessing module are used. Then, the outputs from the exponent, mantissa, and sign bit calculation module are concatenated, along with the four exception flags, to obtain the final calculation result and the four exception flags.

[0128] The third-level DFF uses the valid enable signal output by the enable control module stored in the first-level DFF register as the enable signal. When valid, it is used to store the calculation results and exception flag data generated by the result splicing module. When invalid, it retains the data.

[0129] The following is the overall calculation method flow, which integrates the calculation flow of floating-point multiplication and addition, multiplication and subtraction, negative multiplication and addition, negative multiplication and subtraction, addition, subtraction and multiplication.

[0130] like Figure 2 As shown, it is implemented in three cycles, which can be defined as the first stage, the second stage, and the third stage.

[0131] I. First Phase

[0132] The input data consists of the opcode, opcode enable, rounding mode, fa, fb, and fc. The opcode and opcode enable signal enter the enable control module, where opcode decoding determines which of the seven operations is being performed, and simultaneously obtains the enable signal. The rounding mode signal directly enters the first-level DFF; fa, fb, and fc signals enter the data processing module, where, based on the enable signal output from the enable control module, the input fa, fb, and fc signals undergo data preprocessing. Implement floating-point multiplication and addition without processing; implement floating-point multiplication and subtraction by inverting the sign bit of fc; implement floating-point negative multiplication and addition by inverting the sign bits of fa and fc; implement floating-point negative multiplication and subtraction by inverting the sign bit of fa; implement floating-point addition instruction, with fa and fc as operands and fb set to the floating-point constant 1; implement floating-point subtraction operation, with fa and fc as operands, fb set to the floating-point constant 1, and the sign bit of fc inverted; implement floating-point multiplication operation, with fa and fb as operands and fc set to 0.

[0133] The processed fa, fb, and fc are then output to the data extraction module. The sign bit, exponent bit, and mantissa bit of the data are extracted. For normalized numbers, a 1 is added to the hidden mantissa bit; for denormalized numbers, a 0 is added to the hidden mantissa bit to ensure data integrity. The sign bit, exponent bit, and mantissa bit of fa, fb, and fc are output. Simultaneously, the enable control module's output is used to determine if it is enabled; if not, all data in the sign bit, exponent bit, and mantissa bit are set to 0.

[0134] Then, the exponent and mantissa bits of fa, fb, and fc output by the data extraction module are normalized to convert the denormalized number into a normalized representation.

[0135] The process is then divided into sign preprocessing, exponent preprocessing, mantissa preprocessing, and special data detection.

[0136] The sign preprocessing uses a sign bit processing module. Based on the sign bits of fa, fb, and fc output by the data extraction module, it performs an XOR operation on the three operands. This XOR operation is used as a subtraction enable signal as the output. When the signal is valid, it indicates subtraction; when it is invalid, it indicates addition.

[0137] The exponent preprocessing calculates the exponent bits of fa, fb, and fc output from the data normalization module. It adds the exponent bits of fa to the exponent bits of fb and subtracts the bias bit 127, naming the result 'a'. It then subtracts the exponent bits of fa, fb, and the bias bit 127 from the exponent bits of fc, naming the result 'd'. Based on the value of 'd', a valid signal with a larger exponent in fc is generated. Finally, the absolute value of 'd' is calculated. If 'd' is positive, it remains unchanged; if negative, it is inverted and then incremented by 1. The final output includes the result 'a', the exponent difference 'd', the valid signal with a larger exponent in fc, and the absolute value of the exponent difference 'd'.

[0138] The mantissa preprocessing first uses the mantissa booth encoding module to perform radix-4 booth encoding on the mantissa of fb output by the data normalization module. Then, it is calculated with the mantissa of fa output by the data normalization module to finally obtain 13 partial products, which are then transmitted to the Wallace number compression module and compressed using a 3:2 compressor to obtain 48-bit Sum and Carry results.

[0139] The special data detection module performs special data indication signals by detecting positive 0, negative 0, positive infinity, negative infinity, QNaN, and SNaN based on the sign bit, exponent bit, and mantissa bit of the input data preprocessing module.

[0140] Next, path determination is performed. The path determination module determines the path based on the output of the sign bit processing module and the exponent difference d output of the exponent preprocessing module. The determination is then processed according to the judgment conditions in Table 3, and the following signals are output: valid addend path, valid partial product path, and valid Close path.

[0141] Finally, the valid enable signal output by the enable control module is used as the control enable. When valid, the output results of the input rounding mode, enable control module, data extraction module, sign bit processing module, data normalization processing module, exponent preprocessing module, path judgment module, mantissa booth encoding module, Wallace tree compression module and special data detection module are stored in the first-level DFF. When invalid, the original data of the first-level DFF remains unchanged, waiting for the next stage pipeline operation.

[0142] II. Second Phase

[0143] The second stage is divided into three paths: the addend path, the partial product path, and the Close path.

[0144] 1. Addend path

[0145] For the addend path, the multiplication carry module operates on the most significant bits of Sum and Carry output from the Wallace tree compression module in the first-level DFF register, performing a bitwise OR operation on the two operands and outputting the result. Then, the 48-bit Sum and 48-bit Carry output from the Wallace tree compression module in the first-level DFF register are shifted using 28-bit shift modules 1 and 28-bit shift modules 2, based on the exponent difference output from the exponent preprocessing module in the first-level DFF register. This shift value is set to 28 if it is greater than 28.

[0146] Then, both Sum and Carry are padded with 0s and the lower bits are padded with 28 bits. A right shift operation is then performed to obtain a 76-bit shifted result. The lower 75 bits of the shifted Sum and Carry are output. These two Sum and Carry results are then compared with the mantissa of fc output from the data normalization processing module of the first-stage DFF register. The sign bit processing module output from the first-stage DFF register serves as the subtraction enable signal. If valid, Sum and Carry are inverted; otherwise, no operation is performed.

[0147] Then, the three operands are compressed using a 75-bit compression module and a 3:2 compressor. During this operation, the sign bit processing module of the first-stage DFF register outputs an increment signal. When valid, the increment operation is considered during the 3:2 compressor compression, resulting in a 76-bit Sum and a 75-bit Carry. The most significant bit of Sum is output as the carry value. The remaining 75 bits of Sum and Carry are split into a high 48 bits and a low 27 bits for output. The low 27 bits of Sum and Carry are transmitted to the rounding bit processing module 1. The subtraction signal is output based on the sign bit processing module of the first-stage DFF register. During subtraction, the least significant bit is considered for incrementing; during addition, no operation is performed. Finally, the rounding bits S and mantissa carry for addition and subtraction are obtained respectively.

[0148] 2. Partial product path

[0149] For partial product paths, the exponent difference output by the exponent preprocessing module in the first-level DFF register is used as the shift value. When this shift value is greater than 49, the shift value is 49. The mantissa bits of the fc output by the data normalization processing module in the first-level DFF register are padded with 0s, with 1 bit padded to the high bits and 49 bits padded to the low bits. Then, a right shift operation is performed to obtain a 74-bit shifted result, which is then output. This output is then operated on with the 48-bit Sum and 48-bit Carry output by the Wallace tree compression module in the first-level DFF register. The sign bit processing module output in the first-level DFF register is used as the subtraction enable signal. When valid, the 49-bit shift module output result is inverted; otherwise, no operation is performed.

[0150] Then, the three operands are compressed using a 3:2 compressor. During this operation, the sign bit processing module of the first-stage DFF register outputs the increment signal (S1). During subtraction, the increment operation is considered during the 3:2 compressor compression, resulting in a 75-bit Sum and a 74-bit Carry. The most significant bit of Sum is output as the carry value. The remaining 74 bits of Sum and Carry are split into a high 48-bit and a low 26-bit output. The low 26 bits of Sum and Carry are transmitted to the rounding bit processing module 2, which outputs the subtraction signal based on the sign bit processing module of the first-stage DFF register, obtaining the rounding bit S and mantissa carry for addition and subtraction respectively.

[0151] 3. Close path

[0152] For the Close path, firstly, a 4-bit shift module is used to shift the mantissa bits of fc output from the data normalization processing module of the first-stage DFF register. First, it is padded with 0s, with 2 bits padded to the high-order bits and 1 bit padded to the low-order bits, resulting in a 27-bit mantissa. Then, the exponent difference output from the exponent preprocessing module of the first-stage DFF register is used as the shift value. The left and right shift controls are based on the comparison signal between fc and the exponent fa*fb output from the exponent preprocessing module of the first-stage DFF register: a left shift occurs when fc is larger, and a right shift occurs otherwise. Finally, the 27-bit shifted result is obtained and output.

[0153] Then the data is transmitted to 49-bit compression module 1 and 49-bit compression module 2 respectively.

[0154] In the 49-bit compression module 1, operations are performed on the 48-bit Sum and 48-bit Carry outputs of the 4-bit shift module output and the Wallace tree compression module output from the first-level DFF register. First, the output of the 4-bit shift module is inverted. Then, the three operands are compressed using a 3:2 compressor to finally obtain and output the 49-bit Sum and 49-bit Carry.

[0155] In the 49-bit compression module 2, operations are performed on the 48-bit Sum and 48-bit Carry outputs from the 4-bit shift module output and the Wallace tree compression module output from the first-level DFF register. First, the Sum and Carry are inverted. Then, the three operands are compressed using a 3:2 compressor, with an increment operation considered during this operation. Finally, the 49-bit Sum and 49-bit Carry are obtained and output.

[0156] Then, the Sum and Carry output from the 49-bit compression module 1 are transmitted to the preamble prediction module and the comparison module. The preamble 0 prediction module operates based on the Sum and Carry results from the 49-bit compression module 1. First, it inverts the Carry value, then performs preamble 0 prediction encoding based on these two operands, outputting a 49-bit preamble 0 prediction code to the preamble 0 detection module. It then performs high-order 0 detection on the 49-bit preamble 0 prediction code output from the preamble 0 prediction module and outputs the number of high-order 0s. The comparison module operates based on the Sum and Carry results from the 49-bit compression module 1. It compares the output of the 4-bit shifted module with the 48-bit Sum and 48-bit Carry output from the Wallace tree compression module stored in the first-level DFF register. It determines the enable signal with the larger 4-bit shifted module output; if this is active, the 4-bit shifted module output is larger; otherwise, the sum of Sum and Carry is larger.

[0157] Then, data selection module 1 and data selection module 2 select the outputs of 49-bit compression module 1 and 49-bit compression module 2 based on the comparison signal generated by the comparison module. For data selection module 1, when the enable signal output by the comparison module is valid, it selects the Sum value of 49-bit compression module 2 for output; otherwise, it selects the Sum value of 49-bit compression module 1 for output. For data selection module 2, when the enable signal output by the comparison module is valid, it selects the Carry value of 49-bit compression module 2 for output; otherwise, it selects the Carry value of 49-bit compression module 1 for output.

[0158] Finally, the valid enable signal output by the enable control module registered in the first-level DFF is used as the enable signal. When valid, the output results of the input rounding mode, enable control module, data extraction module, sign bit processing module, exponent preprocessing module, path judgment module, and special data detection module are registered in the second-level DFF; when invalid, the data remains unchanged. The three enable signals output by the path judgment module registered in the first-level DFF are used as the enable signals. When the addend path valid signal is valid, the carry, 48-bit Sum and 48-bit Carry outputs from the 75-bit compression module, the carry output from the multiplication carry module, and the rounding bits S and mantissa carry outputs from the rounding bit processing module 1 for addition and subtraction are registered in the second-level DFF. When the partial product path valid signal is valid, the carry, 48-bit Sum and 48-bit Carry outputs from the 74-bit compression module, and the rounding bits S and mantissa carry output from the rounding bit processing module 2 for addition are registered in the second-level DFF. The rounding bit S and mantissa carry, and the rounding bit S and mantissa carry of the subtraction operation are registered in the second-level DFF. When the Close path valid signal is valid, the 48-bit Sum and 48-bit Carry output by the normalization and rounding bit processing module 1 and the normalization and rounding bit processing module 2, the output signal of the Close path calculation result of the leading zero detection module (which is 0), the comparison signal output by the comparison module, the rounding bit S and mantissa carry of the subtraction operation, and the rounding bit S and mantissa carry of the addition operation are represented by 0 and registered in the second-level DFF. When all are invalid, the data in the second-level DFF remains unchanged.

[0159] 3. Third stage

[0160] The third stage is divided into symbolic calculation, exponent calculation, and mantissa calculation.

[0161] 1. Symbolic computation

[0162] The sign bit calculation, using the sign bit calculation module, first calculates the sign bit of the special data based on the special data indication signal generated by the special data detection module of the second-level DFF register and the sign bit of the data extraction module. If it is not special data, the sign bit is calculated for the three paths in the second stage. When the addend path valid signal output by the path judgment module of the second-level DFF register is valid, if fc is 0, it is the result of the XOR operation of the sign bits of fa and fb; if fc is not 0, it is the sign bit of fc. When the partial product path valid signal output by the path judgment module of the second-level DFF register is valid, it is the result of the XOR operation of the sign bits of fa and fb. When the Close path valid signal output by the path judgment module of the second-level DFF register is valid, if the output result of the path is 0, the sign bit is 1 if the rounding mode is rounding to negative infinity, and 0 otherwise. If fc of the path is larger, it is the sign bit of fc; otherwise, it is the result of the XOR operation of the sign bits of fa and fb.

[0163] 2. Calculation of the last digit

[0164] For mantissa calculation, the 48-bit Sum and 48-bit Carry data stored in the second-stage DFF register are first transferred to the 48-bit composite adder module. The 48-bit Sum and 48-bit Carry data in the second-stage DFF register are then processed. The 48-bit Sum and 48-bit Carry are added together to obtain a carry-1 and a 48-bit Sum1; then, the 48-bit Sum and 48-bit Carry are added together and then incremented by 1 to obtain a carry-2 and a 48-bit Sum2. Finally, both sets of data are output and transferred to the mantissa prenormalization processing module.

[0165] First, the subtraction signal output from the sign bit processing module of the second-stage DFF register is used as the selection signal. If valid, the subtraction rounding bit S and the mantissa carry are selected from the second-stage DFF register; otherwise, the addition rounding bit S and the mantissa carry are selected. Then, if the mantissa carry is valid, the 48-bit composite adder module outputs the carry value 2 and the 48-bit Sum2 as operands; otherwise, the carry value 1 and the 48-bit Sum1 are selected as operands, ultimately obtaining the carry value and the 48-bit Sum value.

[0166] Then, a logical AND operation is performed between the obtained carry value and the carry value output by the multiplication carry module in the second-level DFF register to obtain a valid signal shifted right by 2 bits. If the subtraction signal output by the sign bit processing module in the second-level DFF register is invalid and the carry value or the carry value output by the multiplication carry module in the second-level DFF register is valid, a valid signal shifted right by 1 bit is generated. If the subtraction signal output by the sign bit processing module in the second-level DFF register is valid, the most significant bit of Sum is invalid, and the second most significant bit of Sum is valid, a valid signal shifted left by 1 bit is generated.

[0167] Finally, based on the subtraction signal and the right-shifted-1-bit valid signal output from the sign bit processing module of the second-level DFF register, the rounding bit is appended to the least significant bit of Sum, and then the data is processed to obtain the mantissa calculation result. Finally, the right-shifted-2-bit valid signal, the right-shifted-1-bit valid signal, the left-shifted-1-bit valid signal, the most significant bit of Sum, the second most significant bit of Sum, and the mantissa calculation result are output.

[0168] 3. Index Calculation

[0169] Exponent calculation is performed using the exponent calculation module. It is divided into two types of calculations: one is the exponent calculation of the Close path, and the other is the exponent calculation of the Far path, which is the exponent calculation of the addend path or the partial product path.

[0170] When the Close path valid signal output by the path judgment module of the second-level DFF register is valid, the Close path exponent is calculated. Based on the output signal from the leading zero detection module of the second-level DFF register indicating a Close path calculation result of 0, if this signal is valid, the Close path exponent result is 0; otherwise, the following calculation is performed. Based on the comparison signal output by the exponent preprocessing module of the second-level DFF register, if the fc exponent is larger, the number of outputs from the leading zero detection module of the second-level DFF register is subtracted by 2, and then the absolute value of d output by the exponent preprocessing module of the second-level DFF register is added. Conversely, the number of outputs from the leading zero detection module of the second-level DFF register is subtracted by 2, the most significant bit of this data is padded with high-order extension, and then inverted as the leading zero correction data. Then, the larger exponent output by the exponent preprocessing module of the second-level DFF register is added to the leading zero correction data. Simultaneously, the larger exponent output by the exponent preprocessing module of the second-level DFF register is calculated, plus the leading zero correction data, and then 1 is added, thus producing results without adding 1 and results with adding 1.

[0171] The data selection is based on the valid signal generated by the mantissa prenormalization processing module, which is shifted left by 1 bit. If valid, the result without incrementing by 1 is selected; otherwise, the result with incremented by 1 is selected as the exponent result. When the addend path valid signal or the partial product path valid signal output by the path judgment module in the second-stage DFF register is valid, the Far path exponent is calculated.

[0172] First, when the partial product path valid signal output by the path determination module of the second-level DFF register is valid, the larger exponent output by the exponent preprocessing module of the second-level DFF register is selected as the intermediate result. When the addend path valid signal output by the path determination module of the second-level DFF register is valid, if fc is 0, the absolute value of d output by the exponent preprocessing module of the second-level DFF register minus the larger exponent output by the exponent preprocessing module of the second-level DFF register is selected as the intermediate result. If it is not 0, the larger exponent output by the exponent preprocessing module of the second-level DFF register is selected as the intermediate result. The result is incremented by 1, incremented by 2, decremented by 1, and decremented by 2 to obtain four temporary results. Then, based on the valid signals of the addend path and the partial product path output by the path judgment module of the second-level DFF register, the subtraction signal of the second-level DFF register, the valid signals of right shift by 1 bit, right shift by 2 bits, and left shift by 1 bit output by the mantissa prenormalization processing module, and the most significant and second most significant bits of Sum, the larger exponent, intermediate results, and four temporary results output by the exponent preprocessing module of the second-level DFF register are selected to finally obtain the exponent result output.

[0173] The exponent and mantissa results are transmitted to the denormalized number processing module. Based on the exponent result output by the exponent calculation module, its value is used as a judgment signal to calculate the absolute value of the exponent plus 1 as the shift value. The output result of the mantissa prenormalization processing module is right-shifted, and finally the exponent and mantissa results in denormalized number representation are output.

[0174] The sign bit output by the sign bit calculation module, the exponent and mantissa output by the denormalization module, and the mantissa prenormalization module are then transmitted to the result preprocessing module. This module processes the special data based on the special data indication signal generated by the special data detection module in the second-level DFF register, deriving the exponent, mantissa, and NV anomaly flag. If the data is not a special value, boundary value processing is performed using the exponent and mantissa output by the exponent calculation module and the mantissa prenormalization module, the exponent and mantissa results from the denormalization module, the rounding mode in the second-level DFF register, and the sign bit generated by the sign bit calculation module. The resulting exponent, mantissa, rounding bit, and OF and UF anomaly flags are then transmitted to the result postprocessing module. This module performs five rounding operations based on the mantissa and rounding bit output by the result preprocessing module, the sign bit generated by the sign bit calculation module, and the rounding mode in the second-level DFF register. If a carry-in exists, the exponent is incremented by 1; if a rounding operation occurs, an NX anomaly flag is generated simultaneously. Next, boundary checks are performed on the rounded result to determine if overflow or underflow exists, and the exception flag, exponent, and mantissa are output and transmitted to the result concatenation module. This module merges the exponent, mantissa, and exception flag generated by the result preprocessing module with the exception flag, exponent, and mantissa output by the result postprocessing module. If the data is special, the exponent, mantissa, and exception flag output by the result preprocessing module are used; otherwise, the exponent, mantissa, and exception flag output by the result postprocessing module are used. Then, the outputs of the exponent, mantissa, and sign bit calculation module are concatenated, and the four exception flags are also concatenated to obtain the final calculation result and the four exception flags, which are then transmitted to the third-level DFF.

[0175] Finally, the third-level DFF uses the valid enable signal output by the enable control module stored in the first-level DFF register as the enable signal. When valid, it is used to store the calculation results and exception flag data generated by the result splicing module; when invalid, it retains the data.

[0176] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A multi-functional arithmetic method for floating-point data, characterized in that, The process includes the following: Phase 1: Input data includes opcode, opcode enable, rounding mode, fa, fb, and fc. The opcode and opcode enable enter the enable control module for opcode decoding to determine which of the seven operations the signal represents, and simultaneously obtain the enable signal. The rounding mode directly enters the first-level DFF. fa, fb, and fc enter the data preprocessing module, which performs data preprocessing on the input fa, fb, and fc based on the enable signal output by the enable control module. The processed fa, fb, and fc are then output to the data extraction module to extract the sign bit, exponent bit, and mantissa bit of the data. Then, the exponent and mantissa bits of fa, fb, and fc output by the data extraction module are normalized to convert the denormalized number into a normalized number representation. The process is then divided into sign preprocessing, exponent preprocessing, mantissa preprocessing, and special data detection. Next, path determination is performed. The path determination module makes a judgment based on the difference between the output of the sign bit processing module and the exponent preprocessing module. Based on the judgment conditions, it processes the data and outputs the addend path valid signal, the partial product path valid signal, and the Close path valid signal. Finally, the valid enable signal output by the enable control module is used as the control enable. When valid, the output results of the input rounding mode, enable control module, data extraction module, sign bit processing module, data normalization processing module, exponent preprocessing module, path judgment module, mantissa booth encoding module, Wallace tree compression module and special data detection module are stored in the first-level DFF. When invalid, the original data of the first-level DFF remains unchanged. The second stage consists of three paths: the addend path, the partial product path, and the Close path. For the adder path, firstly, the 48-bit Sum and 48-bit Carry output from the Wallace tree compression module of the first-level DFF register are operated on. Using the multiplication carry module, the most significant bit of Sum and Carry is ORed and output. Then, the 48-bit Sum and 48-bit Carry are shifted using 28-bit shift module 1 and 28-bit shift module 2. After shifting, the result is compressed using the 75-bit compression module and the mantissa of fc output from the data normalization processing module of the first-level DFF register. Finally, the carry value, 48-bit Sum, 48-bit Carry, lower 27-bit Sum, and lower 27-bit Carry are output. The lower 27-bit Sum and Carry are transmitted to the rounding bit processing module 1 to obtain the rounding bit S and mantissa carry for addition and subtraction operations, respectively. For partial product paths, a 49-bit shift module is used to right-shift the mantissa bits of the data normalization processing module output from the first-level DFF register, resulting in a 74-bit shifted result. This shifted result is then compressed using a 74-bit compression module along with the 48-bit Sum and 48-bit Carry output from the Wallace tree compression module of the first-level DFF register, or by inverting either two data points. The final output is the carry value, 48-bit Sum, 48-bit Carry, and the lower 26 bits of Sum and Carry. The lower 26 bits of Sum and Carry are then transmitted to the rounding bit processing module 2 to obtain the rounding bits S and mantissa carry for addition and subtraction operations, respectively. For the Close path, firstly, a 4-bit shift module is used to shift the mantissa of the data normalization processing module output from the first-level DFF register, resulting in a 27-bit shifted result. Then, this result is transmitted to 49-bit compression modules 1 and 2 respectively, where it is compressed with the 48-bit Sum and 48-bit Carry output from the Wallace tree compression module of the first-level DFF register. This results in two sets of 49-bit Sum and 49-bit Carry, which are then output. Finally, the Sum and Carry output from 49-bit compression module 1 are transmitted to the leading zero prediction module and the comparison module. The leading zero prediction module outputs a 49-bit leading zero. The 0-predictive encoding is passed to the leading 0 detection module, which outputs the number of high-order 0s. The comparison module operates on the Sum and Carry outputs of the 49-bit compression module 1 to obtain an enable signal that is larger than the output of the 4-bit shift module. Then, the data selection modules 1 and 2 select the outputs of the 49-bit compression modules 1 and 2 based on the signal generated by the comparison module. Finally, the normalization and rounding bit processing modules 1 and 2 operate on the outputs of the data selection modules 1 and 2 respectively to obtain the carry value, the 48-bit Sum, the 48-bit Carry, the rounding bit S for the subtraction operation, and the mantissa carry. Finally, the valid enable signal output by the enable control module of the first-level DFF register is used as the enable signal. When valid, the output results of the input rounding mode, enable control module, data extraction module, sign bit processing module, exponent preprocessing calculation module, path judgment module, and special data detection module of the first-level DFF register, as well as the output signal of the multiplication carry module and the leading zero detection module of the second-level DFF register (the Close path calculation result is 0), and the comparison signal output by the comparison module are registered in the second-level DFF. The three enable signals output by the path judgment module of the first-level DFF register are used as enable signals, and the carry values ​​generated by the three paths, the 48-bit Sum, the 48-bit Carry, the rounding bit S and mantissa carry of the addition operation, and the rounding bit S and mantissa carry of the subtraction operation are registered in the second-level DFF. When all the above enable signals are invalid, the original data of the second-level DFF remains unchanged. The third stage: The third stage is divided into symbolic calculation, exponent calculation, mantissa calculation, and final data processing; The sign bit calculation module first calculates the sign bit of the special data based on the special data indication signal generated by the special data detection module in the second-level DFF register and the sign bit of the data extraction module. If the data is not special, the sign bit is calculated for the three paths in the second stage. The selection calculation is performed based on the enable signal of the three paths output by the path judgment module in the second-level DFF register, and finally the sign bit result is output. For mantissa calculation, firstly, a 48-bit composite adder module is used to perform a composite addition operation on the 48-bit Sum and 48-bit Carry stored in the second-stage DFF register. The 48-bit Sum and 48-bit Carry are then added together to obtain a carry-in value of 1 and a 48-bit Sum1. Next, the 48-bit Sum and 48-bit Carry are added together and then 1 is added to obtain a carry-out value of 2 and a 48-bit Sum2. Finally, the two sets of data are output and transmitted to the mantissa prenormalization processing module. The mantissa prenormalization processing module operates based on the rounding bits S and mantissa carry from the addition and subtraction registers in the second-stage DFF register, the subtraction signal output from the sign bit processing module in the second-stage DFF register, and the multiplication carry output from the multiplication carry module in the second-stage DFF register. Finally, the valid signals shifted right by 2 bits, shifted right by 1 bit, shifted left by 1 bit, the most significant bit of Sum, the second most significant bit of Sum, and the mantissa calculation result are output. The exponent calculation is performed using the exponent calculation module and is divided into two types of calculations: when the Close path valid signal output by the path judgment module of the second-level DFF register is valid, the exponent calculation is performed for the Close path; when the addend path valid signal or the partial product path valid signal output by the path judgment module of the second-level DFF register is valid, the exponent calculation is performed for the Far path; finally, the exponent result is output. The final data processing involves operating on the exponent result output by the exponent calculation module and the mantissa result output by the mantissa prenormalization module, and finally outputting the exponent and mantissa results in denormalized number representation; then the sign bit output by the sign bit calculation module, the exponent and mantissa output by the denormalization module, and the mantissa prenormalization module are transmitted to the result preprocessing module. The result preprocessing module processes the special data based on the special data indication signal generated by the special data detection module in the second-level DFF register to obtain the exponent, mantissa, and NV anomaly flag. If it is not a special value, the exponent and mantissa output by the exponent calculation module and the mantissa prenormalization processing module, the exponent and mantissa results from the denormalization processing module, the rounding mode in the second-level DFF register, and the sign bit generated by the sign bit calculation module are used as operation data for boundary value processing. The exponent, mantissa, rounding bits, and OF and UF anomaly flags of the first result processing are output and transmitted to the result postprocessing module. The post-processing module performs five rounding operations based on the mantissa and rounding bits output by the result preprocessing module, the sign bit generated by the calculation module, and the rounding mode of the second-level DFF register, while generating an NX exception flag. Then, it performs boundary checks on the rounded result to determine whether there is overflow or underflow and outputs the exception flag, exponent, and mantissa to the result concatenation module. The result concatenation module merges the exponent, mantissa, and exception flags generated by the result preprocessing module and the exception flags, exponent, and mantissa output by the result postprocessing module. If the data is special, the exponent, mantissa, and exception flags output by the result preprocessing module are used; otherwise, the exponent, mantissa, and exception flags output by the result postprocessing module are used. Finally, the result is concatenated with the output of the sign bit calculation module to obtain the final calculation result and four exception flags, which are then transmitted to the third-level DFF. The third-level DFF uses the valid enable signal output by the enable control module stored in the first-level DFF register as the enable signal. When valid, it is used to store the calculation results and exception flag data generated by the result splicing module. When invalid, it retains the data.

2. A multi-functional floating-point data processing device, employing the method as described in claim 1, characterized in that, The device adopts a three-stage pipeline structure, which is divided into three parts, each of which is a single-stage pipeline. The first part completes the data preprocessing, exponentiation, and mantissa multiplication. It includes an enable control module, a data preprocessing module, a data extraction module, a sign bit processing module, a data normalization processing module, an exponent preprocessing module, a path judgment module, a mantissa booth encoding module, a Wallace tree compression module, a special data detection module, and a first-level DFF; The second part completes the addition operation of floating-point mantissas; including the addend path, partial product path, and Close path; The third part completes the exponent calculation, mantissa calculation, rounding operation, special value handling, exception flag handling, and outputs the final result; It includes a sign bit calculation module, an exponent calculation module, a 48-bit composite adder module, a mantissa prenormalization processing module, a denormalized number processing module, a result preprocessing module, a result postprocessing module, a result concatenation module, and a third-level DFF.

3. The multi-functional floating-point data processing device according to claim 2, characterized in that, The adder path includes a multiplication carry module, a 28-bit shift module 1, a 28-bit shift module 2, a 75-bit compression module, and a rounding bit processing module 1.

4. A multi-functional floating-point data processing device according to claim 2, characterized in that, The partial product path includes a 49-bit shift module, a 74-bit compression module, and a rounding bit processing module 2.

5. A multi-functional floating-point data processing device according to claim 2, characterized in that, The Close path includes a 4-bit shift module, a 49-bit compression module 1, a 49-bit compression module 2, a leading zero prediction module, a leading zero detection module, a comparison module, a data selection module 1, a data selection module 2, a normalization and rounding bit processing module 1, a normalization and rounding bit processing module 2, and a second-level DFF.

6. A multi-functional floating-point data processing device according to claim 2, characterized in that, The input data of the device consists of an opcode, an opcode enable, a rounding mode, and three operands fa, fb, and fc, where operands fa, fb, and fc can be positive, negative, normalized, or denormalized numbers.

7. A multi-functional floating-point data processing device according to claim 6, characterized in that, The device is used to perform seven operations on operands fa, fb, and fc: floating-point multiplication and addition, multiplication and subtraction, negative multiplication and addition, negative multiplication and subtraction, addition, subtraction, and multiplication.

8. A multi-functional floating-point data processing device according to claim 2, characterized in that, The data normalization processing module includes a leading zero detection module 1, a leading zero detection module 2, a leading zero detection module 3, an 8-bit addition module, and a 24-bit left shift module.

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