System and method for testing asynchronous finite machines

Abstract

Systems and methods of testing an asynchronous finite state machine are disclosed. A method of testing a fault of an asynchronous finite state machine, the method comprising disabling state transitions out of a state of the asynchronous finite state machine, and inputting test data to the AFSM to trigger a transition from the state to an expected state. The method further comprises enabling state transitions out of the state of the asynchronous finite state machine, and determining whether the asynchronous finite state machine has performed a successful transition to the expected state.

Description

Technical Field

[0001] This invention generally relates to methods and systems for testing asynchronous finite machines. Background Technology

[0002] Testing asynchronous finite state machines can be problematic. Known methods exist for functionally testing asynchronous finite state machines. However, functional testing may miss potential faults and consume significant time. Summary of the Invention

[0003] According to one embodiment, a method for testing the failure of an asynchronous finite state machine (AFSM) includes: disabling state transitions out of the AFSM; inputting test data into the AFSM to trigger a transition from that state to the expected state; enabling state transitions out of the AFSM; and determining whether the AFSM has successfully transitioned to the expected state.

[0004] According to one embodiment, the asynchronous finite state machine includes: a state unit configured to store a value after receiving a transition signal; and an ARC unit configured to generate a transition signal, the asynchronous finite state machine being configured to disable the generation of the transition signal when the asynchronous finite state machine receives a disable signal.

[0005] According to one embodiment, the test system includes: an asynchronous finite state machine (AFSM) having an initial state, the AFSM being configured to transition from the initial state to a destination state in response to receiving trigger data; a test register configured to provide trigger data to the AFSM during a test mode of the test system; and an output register coupled to the AFSM to receive a state signal that changes in response to a state transition of the AFSM, the AFSM being configured to disable the state transition signal in response to an assertion of a disable signal received by the AFSM. Attached Figure Description

[0006] To gain a more complete understanding of the invention and its advantages, the following description is now taken in conjunction with the accompanying drawings, in which:

[0007] Figure 1 A schematic diagram describing AFSM is shown;

[0008] Figure 2 The inputs and outputs of the AFSM are shown;

[0009] Figure 3 A system for testing AFSM according to an embodiment is described;

[0010] Figure 4A The steps of the AFSM test according to an embodiment are described;

[0011] Figure 4BA finite state machine locked to a given state according to an embodiment is shown;

[0012] Figure 5 A method for testing the transitions of an asynchronous finite state machine according to an embodiment is described;

[0013] Figure 6 The ARC unit according to the embodiment is described;

[0014] Figure 7 The state unit according to the embodiment is described;

[0015] Figure 8 The arrangement of the ARC unit and state unit according to an embodiment is described; and

[0016] Figure 9 A method for testing the failure of an AFSM according to an embodiment is described. Specific Implementation

[0017] Many known and emerging technologies rely on asynchronous finite state machines (AFSMs). State transitions can occur quickly and efficiently. However, known methods and systems for testing AFSMs involve functional testing, which is expensive in terms of time and cost. An alternative approach offers early, rapid, and accurate fault detection.

[0018] In various embodiments, tests can be performed by setting the input of the AFSM to a value known to trigger the transformation and confirming that the transformation has occurred.

[0019] Figure 1 A schematic diagram illustrating AFSM is shown.

[0020] AFSM 100 can include multiple states. For example, Figure 1 The AFSM shown includes an initial state S0, a first state S1, a second state S2, a third state S3, and a fourth state S4. As will be understood, the AFSM may include any number of states.

[0021] When certain conditions are met, the AFSM can transition between states. These transitions can be called ARCs. When a condition is met, an ARC signal can be generated to trigger the AFSM to transition from one state to another. When the corresponding conditions are met, a state can transition through different ARCs. For example, a single state may have more than one possible ARC to leave that state. Similarly, a single state may have more than one possible ARC to enter that state.

[0022] like Figure 1As shown, AFSM 100 can transition from initial state S0 to first state in response to a first ARC signal F1. AFSM can transition from first state S1 to second state S2 in response to a second ARC signal F2. AFSM can transition from first state S1 to third state S3 in response to a third ARC signal F3. AFSM can transition from first state S1 to fourth state S4 in response to a fourth ARC signal F4.

[0023] As will be understood, the ARC signal can be generated depending on the input received by the AFSM. The ARC signal can also depend on the current state of the AFSM. For example, being in the first state can be a prerequisite for the ARC to leave the first state and for the input conditions.

[0024] Figure 2 The inputs and outputs of AFSM are shown.

[0025] The inputs to the AFSM determine when a state transition occurs. The AFSM 200 can receive input signals 202 at input 200A. These input signals 202 are received from other components of the device or system. For example, input signals 202 may originate from various sensors or other components. As will be understood, signals may undergo various forms of processing and conversion (such as conversion to digital signals) before being transmitted to the AFSM.

[0026] AFSM 200 can also generate a status signal 204. Status signal 204 indicates the status of AFSM 200. The status signal can also be provided to additional logic to generate an output. The status signal can also be encoded to represent the status of the AFSM. In various embodiments, this can include a one-hot encoding.

[0027] Functional testing of an AFSM requires the system or device to be running to check its performance. However, it is difficult to functionally test all possible conditions to confirm the operation of an AFSM. This may lead to faults being overlooked and excessive time being required. Functional testing may impose limitations on when tests can be performed. For example, input signals may depend on other components that may need to be installed and tested before testing the AFSM.

[0028] Setting up AFSM inputs using test data provides a faster, more accurate, and more flexible testing methodology.

[0029] Figure 3 A system for testing AFSM according to an embodiment is described.

[0030] In various embodiments, AFSM 302 may include logic units that store the state of AFSM 302 and trigger transitions. ARC unit 304 may trigger transitions from one state to another, and state unit 306 may store the state of AFSM 302. State unit 306 and ARC unit 304 may be coupled to each other via an internal bus.

[0031] In various embodiments, the system 300 for testing the AFSM may further include input logic 308. Input logic 308 may define when to generate an ARC signal based on functional input 310 received by input logic 308. A given ARC signal may be triggered in response to a predefined condition being met. For example, input logic 308 may provide a first ARC signal 312A, a second ARC signal 312B, a third ARC signal 312C, and a fourth ARC signal 312D. As will be understood, conditions may be defined differently for different embodiments depending on the desired functionality of the AFSM. Furthermore, in various embodiments, the number of ARC signals may be fewer or more. Additionally, ARC signals may be used to encode ARC (e.g., "1011" at an input may trigger an eleventh ARC, etc.).

[0032] In various embodiments, AFSM 302 may also output status signals indicating the state of AFSM 302. For example, AFSM 302 may provide a first status signal 314A when in a first state, a second status signal 314B when in a second state, a third status signal 314C when in a third state, and a fourth status signal 314D when in a fourth state. As will be understood, the number of status signals may be different in various embodiments. The state may also be encoded at the output (e.g., "1011" may correspond to the eleventh state, etc.).

[0033] System 300 may also include output logic 316, which receives status signals from AFSM 302 and generates outputs based on the status of AFSM.

[0034] By providing a test signal to the AFSM instead of a standard input, efficient and accurate testing of the AFSM can be permitted. Test data simulating functional data can be provided at the AFSM's input, rather than the functional data itself. In various embodiments, the test signal can be controlled and input to the AFSM to trigger a transition based on the test progress used to test the AFSM's operation.

[0035] System 300 may include a MUX (multiplexer) or a group of multiplexers to switch inputs provided to the AFSM between inputs provided during functional (or standard operation) and test data inputs. One or more multiplexers may receive data from functional input sources and test input sources (such as test registers).

[0036] In various embodiments, system 300 may include a first multiplexer 318A receiving a first test signal 320A and a first ARC signal 312A, a second multiplexer 318B receiving a second test signal 320B and a second ARC signal 312B, a third multiplexer 318C receiving a third test signal 320C and a third ARC signal 312C, and a fourth multiplexer 318D receiving a fourth test signal 320D and a fourth ARC signal 312D. As will be understood, the number of test signals and multiplexers may vary in different embodiments. The test signals (e.g., the first test signal 320A, the second test signal 320B, the third test signal 320C, and the fourth test signal 320D) may provide test data to the AFSM, which is triggering data to the AFSM.

[0037] The outputs of the multiplexers can be switched between their outputs. This can be achieved via a test enable signal 321 coupled to each multiplexer. In various embodiments, the test enable signal can be provided by a test controller or an off-chip tester when testing of the AFSM 302 is initiated. The test enable signal 321 can be received from the test enable port 323. Therefore, test data can be provided to the AFSM instead of data provided from a functional or operational source. In this way, the system 300 can include a test mode. When in test mode, test data can be provided to the AFSM 302.

[0038] In various embodiments, system 300 may include a test register 322 for loading test data. Test data may be loaded into the test register from a test device such as a test controller or an off-chip automated test equipment (“ATE”). The test register may be coupled to an input interface 324 to receive test data. In various embodiments, test data may be loaded into the test register one bit at a time. For example, when in shift mode, data from the test register may be loaded into a first flip-flop 322A of the test register on a first clock pulse. On the next clock pulse, the data may be shifted to a second flip-flop 322B. This may continue until test data is loaded into the test register. Figure 3 The third flip-flop 322C and the fourth flip-flop 324D of the test register 322 are also shown. However, it should be understood that the test register 322 may include any number of flip-flops.

[0039] Test register 322 may also include a capture mode in which data is provided from the flip-flops of test register 322 to a multiplexer. For example, when a capture signal is received, data from first flip-flop 322A can be provided to first multiplexer 318A, data from second flip-flop 322B can be provided to second multiplexer 318B, data from third flip-flop 322C can be provided to third multiplexer 318C, and data from fourth flip-flop 322D can be provided to fourth multiplexer 318D. Therefore, when system 300 is in test mode, data from the test register can be provided to AFSM 302. For example, when test enable signal 321 is asserted, the multiplexer can output data received from the test register to AFSM 302.

[0040] Test register 322 can be switched between modes via selector signal 325. Selector signal 325 can set test register 322 to shift data. Selector signal 325 can also set test register 322 to capture. Selector signal 325 can be received from select port 326. Selector signal 325 can be provided by an off-chip tester (e.g., ATE or other test equipment).

[0041] In various embodiments, test register 322 may also receive clock signal 332. The clock signal may be provided to flip-flops in test register 322. When in shift mode, the flip-flops may shift data over each clock cycle. In various embodiments, the clock signal may be provided by an off-chip test device (such as an ATE). It may be received at clock port 334.

[0042] Disabling the state transition of AFSM 302 may be advantageous when data is loaded into test register 322. This allows data to be loaded into the test register without triggering a state transition as data is shifted through the test register. Such an undesirable state transition could interfere with the desired test progress, making the test complex, impractical, or impossible.

[0043] To freeze the state of AFSM 302, AFSM 302 can receive a disable signal 328. The disable signal can be asserted when data is loaded into test register 322 to prevent unwanted transitions. In various embodiments, the disable signal 328 can be derived from selector signal 325. For example, selector signal 325 can be coupled to inverter 330 to generate disable signal 328. This allows AFSM 302 to be disabled whenever test register 322 is in shift mode, thus freezing the state of AFSM 302. This also allows enabling AFSM 302 to transition simultaneously with test register 322 entering capture mode. Therefore, data input and capture of test register 322 can be synchronized with disabling and enabling test registers. As will be understood, in other embodiments, the disable signal 328 can also be provided independently of selector signal 325.

[0044] In various embodiments, reset signal 336 may also be provided to AFSM 302. Reset signal 336 can reset the state of AFSM 302 to an initial or default state. In various embodiments, the reset signal may be provided by an off-chip test device. This may include, for example, an ATE (Automatic Test Equipment). Reset signal 336 may be received at reset port 338.

[0045] In various embodiments, a status signal from AFSM 302 can also be provided to output register 340. Output register 340 can be used to store the status of AFSM 302. Output register 340 may include a shift mode in which data is output to output port 342. In various embodiments, when output register 340 is in shift mode, data from output register 340 can be serially output to output port 342. Output register 340 can receive a selection signal to switch between a shift mode when outputting data and a capture mode when loading data from AFSM 302. In various embodiments, selector signal 325 of test register 322 can be coupled to the output register and used as a selection signal for output register 340. As will be understood, the operation of the output register can be synchronized with test register 322 and AFSM 302. For example, when test register 322 is in shift mode, the output register can also be in shift mode, and the status of AFSM 302 can be fixed by disable signal 328. The status signal can then be set so that data can be accurately output and read. This facilitates testing of the AFSM 302. In various embodiments, the output register 340 can be switched between shift and capture states by a signal driven separately from the selector signal 325. Such a signal can also be synchronized with the selector signal 325 if needed.

[0046] As a non-limiting example, in various embodiments, output register 340 may include a first output flip-flop 340A, a second output flip-flop 340B, a third output flip-flop 340C, and a fourth output flip-flop 340D. The first output flip-flop 340A may receive a first status signal 314A. The second output flip-flop 340B may receive a second status signal 314B. The third output flip-flop 340C may receive a third status signal 314C. The fourth output flip-flop 340D may receive a fourth status signal 314D. Output register 340 may store the status of AFSM 302, which may be output to output port 342 and checked. Output port 342 may be coupled to an off-chip test device (such as an ATE).

[0047] Data indicating the state of AFSM 302 can be stored in an output register. For example, when in a first state, AFSM 302 can assert a first state signal 314A, which can be provided to a first output flip-flop 340A. This can be stored and output to output port 342, which can be achieved by serially shifting data through output register 340 to output port 342. As will be understood, the size of output register 340 can vary.

[0048] As a non-limiting example, testing of the AFSM 302 can be initiated by asserting the test enable signal 321. This opens a path for providing test data to the AFSM 302 via a multiplexer or multiplexer group (e.g., first multiplexer 318A, second multiplexer 318B, third multiplexer 318C, and fourth multiplexer 318D). In various embodiments, the AFSM 302 can be reset to an initial or default state. This can be done using the reset signal 336. Data can then be loaded into the test register 322 while the test register 322 is in shift mode, the shift mode being controlled by the selector signal 325. The AFSM 302 can have its state fixed by the disable signal 328 to prevent state changes while loading data to prevent unwanted state changes.

[0049] Data loaded into test register 322 can be selected to trigger a desired transition from one state to another in AFSM 302 when transitions are enabled. After loading, test register 322 can switch from shift mode to capture mode. Simultaneously, selector signal 325 can enable transitions in AFSM 302 (via inverter 330 in various embodiments). The test data can then trigger the internal logic of AFSM 302 (if functioning correctly) to generate the desired transition signal, thereby causing AFSM 302 to change the state indicated by the test data. This, in turn, can lead to a change in the state signal output by AFSM 302.

[0050] When test register 322 is set to capture mode, output register 340 can also receive selector signal 325 (or an independent signal) and be set to capture mode simultaneously. The output register stores the status signal output of AFSM 302. In various embodiments, the status signal can be stored in parallel in the flip-flops of output register 340.

[0051] Test register 322 and output register 340 can return to shift mode, and transitions of AFSM 302 can be disabled. In various embodiments, this can occur by toggling selector signal 325, which switches test register 322 and output register 340 to shift mode and asserts a disable signal 328. Data can be output from output register 340 to indicate the state of AFSM 302. It may be beneficial that the state of AFSM 302 is fixed by the disable signal while data is being output, so that the state signal does not flow when data is being output. The state data can be compared with the expected state of AFSM 302 to determine whether AFSM 302 is operating correctly. New test data can also be loaded into test register 322 simultaneously to test another transition of AFSM 302. This can be repeated for all possible transitions of AFSM 302 to test the internal components of AFSM 302. If the simulation is successful, the internal logic of AFSM can operate properly without a stuck-at fault.

[0052] Figure 4A The description illustrates the steps of the AFSM test according to an embodiment.

[0053] Figure 4AA simplified embodiment of a finite state machine 400 is described. This simplified example is provided for illustration and should not be construed as limiting the application of this disclosure. The finite state machine 400 includes an initial state S0, a first state S1, a second state S2, a third state S3, and a fourth state S4. The logic of the finite state machine 400 allows a first ARC A1 to leave the initial state S0 and allows a second ARC A2 to leave the first state. The logic of the finite state machine 400 also allows both ARCs to leave the first state: the first ARC B1 to the second state S1 and the second ARC B2 to the third state.

[0054] As will be understood, these ARCs can be triggered by satisfying different conditions that can be defined by the design of the finite state machine. When the first ARC A1 is triggered, the finite state machine 400 is configured to shift to the first state. When the second ARC A2 is triggered, the finite state machine 400 can be configured to transition to the fourth state S4. When the first ARC B1, which exits the first state, is triggered, the finite state machine can shift to the second state S2. And, when the second state is triggered, the finite state machine shifts to the third state S3. When in each state, the finite state machine can output a corresponding state signal, which allows the state of the finite state machine to be compared with the expected result.

[0055] For the purposes of this example, the finite state machine can be assumed to be in its initial state. This is represented by a star in the initial state S0. Test data can be input into the finite state machine 400 to satisfy the conditions for transitioning out of the first state S1 on the first ARC A1. When the test data is loaded, the transition out of the initial state of the finite state machine can be prevented by a disable signal. Once the disable signal is deasserted, the test data will trigger the finite state machine to transition to the first state S1. Figure 4A In the middle, the second ARC is blocked by "X" to indicate that the first ARC A1 has been triggered.

[0056] The state of a finite state machine can be fixed again by asserting a disable signal, and then the disable signal can lock the finite state machine into the first state.

[0057] Figure 4B A finite state machine locked to a given state according to an embodiment is shown.

[0058] After the transition, finite state machine 400 is now in state 1, S1. Figure 4BThe state signal can be asserted again to lock the finite state machine in the first state S1. The state signal can then be checked to determine if the finite state machine 400 operates as expected and transitions to the first state S1. Further tests can also be performed by inputting more test data without unintentionally triggering a transition. This can happen simultaneously when data is output from the output register of the storage-level signal value.

[0059] Figure 5 A method for testing the transitions of an asynchronous finite state machine is described.

[0060] In various embodiments, method 500 may include resetting the asynchronous finite state machine to an initial state in step 502. This may be implemented using a reset signal 336 in various embodiments. In step 504, the method may include disabling transitions out of the current state of the asynchronous state machine. This may be implemented using a disable signal 328 in various embodiments. In step 506 of various embodiments, method 500 may further include scanning test input test data to trigger transitions out of the current state. In various embodiments, this may include setting a test register to shift mode and serially loading data into the test register.

[0061] In various embodiments, the method may include, in step 508, enabling transitions of the asynchronous finite state machine. This can be achieved by deasserting a disable signal. In step 510, in various embodiments, the method 500 may include disabling transitions of the asynchronous finite state machine. This can be achieved by again asserting a disable signal. And, in various embodiments, in step 512, the method 500 may include scanned output data reflecting the state of the asynchronous state machine. This may include serially outputting data from an output register storing state signals, where the state signals are received from the asynchronous finite state machine. This data may be compared with the expected states of the asynchronous finite state machine. And, these states may be repeated until all expected transitions have been checked. If state transitions occur as expected, it can be proven that the AFSM is working as expected and that there is no “stuck” fault in the digital logic constituting the AFSM.

[0062] In various embodiments, ARC unit 304 and state unit 306 may include an arrangement of logic components. The AFSM test of this disclosure can identify stuck faults in the components.

[0063] Figure 6 An ARC unit according to an embodiment is shown.

[0064] As will be understood, the ARC unit may include different forms in different embodiments. Figure 6Only one example of ARC unit 600 is shown. ARC unit 600 may include AND gate 602 and OR gate 604. ARC signal 606 may be provided to the input of OR gate 604. The source of the ARC signal may depend on whether testing is enabled. For example, the ARC signal may be received from the output of a multiplexer (such as a first multiplexer 318A, a second multiplexer 318B, a third multiplexer 318C, or a fourth multiplexer 318D). Furthermore, the output of the multiplexer may depend on test enable port 323. When testing is being performed, ARC signal 606 may be functional test data or analog test data used to trigger the conversion of the ARC signal at its transmission point.

[0065] The output of AND gate 602 may include a transition signal 608. The transition signal may be coupled to the input of a state unit. The transition signal 608 may also be fed back to the input of OR gate 604. AND gate 602 may also receive an acknowledgment signal 610, which reflects whether AFSM 302 is in the appropriate state for asserting a transition signal to leave ARC unit 600. The acknowledgment signal 610 may include a signal enabling ARC to leave the current state, allowing a transition to be triggered from the current state, and may disable ARC for all other states.

[0066] In various embodiments, the AND gate 602 of the ARC unit 600 can be coupled to a disable signal 328. This allows the disable signal 328 to prevent the generation of the transition signal 608. For example, in various embodiments, the test register 322 can be set to shift mode by setting the selector signal 325 to "1". This can be inverted by the inverter 330 and provided to the input of the AND gate 602, which can disable any transition signal 608. In various embodiments, each ARC unit 600 of the AFSM 302 can be disabled to present transition signals, which will freeze the state of the AFSM. It should be understood that this only represents one method of freezing the state of the AFSM (disabling transitions). In various embodiments, transitions can be disabled by a state unit instead of an ARC unit.

[0067] Figure 7 A state unit according to an embodiment is described.

[0068] As will be understood, in various embodiments, the state unit may be implemented in different ways. Figure 7This is just one example. State unit 700 may include an OR gate 704. OR gate 704 may receive an input signal RI. The input signal RI may be asserted when a trigger signal from the corresponding ARC unit 600 is asserted. In some cases, multiple trigger signals may trigger a transition to a given state, so the input symbol RI may be asserted when any of the relevant trigger signals is generated. This can be achieved by inputting the trigger signal to the OR gate, and the output of the OR gate being provided to OR gate 704 as the input signal RI. OR gate 704 may provide the output RO of state unit 700.

[0069] State unit 700 may include an AND gate 702 and an OR gate 704. The AND gate may receive an acknowledgment signal indicating whether the AFSM is in another state. The state unit may also include an inverter 706. The AND gate may also receive a reset signal 708, which may reset the state unit 700 from an asserted state. In various embodiments, the reset signal may include a reset signal 336. State unit 700 may be used to store the state of AFSM 302. Therefore, the output RO of the OR gate is fed back to the AND gate. This allows the output RO of state unit 700 to retain its state once it is asserted by a triggered signal, unless another state unit is asserted (indicated by an acknowledgment signal AO) and the reset signal 708 is not issued. The output of AND gate 702 may also be coupled to the input of OR gate 704.

[0070] Figure 8 The arrangement of the ARC unit and the state unit according to an embodiment is described.

[0071] To avoid redundancy, the points discussed elsewhere in this disclosure will not be repeated here. Figure 8 Explanation of the components. The internal logic 800 of the AFSM may include multiple ARC units and state units. The ARC unit may include ARC unit 600, but may also utilize other ARC units. The state unit may include state unit 700, but may also utilize other state units. Figure 8 Each ARC unit 600 depicted may correspond to a potential ARC of the AFSM. Similarly, each state unit 700 may correspond to a state of the AFSM. As mentioned above, there may be more than one possible transition to a given state. Therefore, the transition signal 608 from the ARC unit 600 can be provided to an OR gate. For example, OR gate 802 can receive the transition signal 608 as well as an additional transition signal 804. The output of OR gate 802 can then be provided to the state unit 700. As will be understood, the internal logic 800 may also include OR gates 806, 810, and 814. Each of these gates can receive the transition signal 608 from the ARC unit 600 and can originate from... Figure 8Additional conversion signals of the ARC unit (such as conversion signal 808, conversion signal 812 and conversion signal 816, not shown in the diagram).

[0072] In various embodiments, the acknowledgment signal 610 of the ARC unit can be received from the output RO of the receiving state unit and an AND gate containing one or more inverted conversion signals. For example, AND gates 818, 820, and 822 can each output an acknowledgment signal 610 to their respective ARC units.

[0073] The output RO of state unit 700 can also be provided to an OR gate (along with the outputs from other state units). The output of such an OR gate can be provided as an acknowledgment signal for the state unit. In various embodiments, AFSM 302 may include internal logic 800. When a state transition has occurred, the acknowledgment signal can turn to "1", which can propagate to the source state to acknowledge the existence of a new current state, so that the RO signal of the source state turns to "0" in response to the acknowledgment signal.

[0074] As will be understood, testing transitions with test data can detect jamming faults in an AFSM, where a logic component cannot switch from one binary state to another. As described in this disclosure, testing an AFSM can reveal undesirable perforated state faults, where a subsequent transition occurs after the transition from the initial state to the target state. For example, if test data is provided to an AFSM that causes it to transition from an initial state S0 to a first state S1, and the AFSM also transitions to a third state S3 due to a jamming fault, this can be termed an undesirable perforated state.

[0075] Testing can also reveal stuck faults that prevent the AFSM from correctly transitioning to a given state. For example, a stuck fault may cause the AFSM to remain in its initial state, even after data that should have been received by the AFSM has triggered it to leave that state. Finally, a stuck fault may cause the AFSM to simultaneously occupy more than one state. This can be referred to as the default state.

[0076] Tests performed according to embodiments of this disclosure can detect jamming faults at various inputs and outputs of the state unit and ARC unit. This provides comprehensive jamming fault detection for the AFSM. For illustrative purposes, examples from state unit 700 and ARC unit 600 will be used in detail. However, this can be used with other ARC unit and state unit embodiments. Each of the following examples can be detected after test data is loaded to trigger a transition and the state of the AFSM is checked, for example by reading the output scanned from output register 340.

[0077] Taking state unit 700 as an example, a stuck-at-"0" fault at input RI can prevent the AFSM from transitioning to the target state. This can be determined by reading the status signal data (e.g., scanning from output register 340) and determining that the AFSM has not transitioned to the intended target state (it remains in the previous state). A stuck-at-"1" fault at input RI of state unit 700 can result in a default state. This can be detected by reading the status signal data (e.g., scanning from output register 340) and determining that it indicates the AFSM includes more than one state.

[0078] A stuck-on-"1 fault at the acknowledgment signal AO can prevent the AFSM from transitioning to the intended state. This can be determined by reading the status signal data (e.g., scanning from output register 340) and determining that the AFSM has not transitioned to the intended destination state (it remains in the previous state). A stuck-on-"0" fault at the acknowledgment signal AO of status unit 700 can result in a default state. This can be detected by reading the status signal data (e.g., scanning from output register 340) and determining that it indicates the AFSM includes more than one state.

[0079] A stuck-at-"0 fault at the output signal RO can prevent the AFSM from transitioning to the target state. This can be determined by reading the status signal data (e.g., scanning from output register 340) and determining that the AFSM has not transitioned to the intended target state (it remains in the previous state). A stuck-at-"1" fault at the output signal RO of status unit 700 can result in a default state. This can be detected by reading the status signal data (e.g., scanning from output register 340) and determining that it indicates the AFSM includes more than one state.

[0080] A stuck-on-"0" fault at reset signal 708 can prevent the AFSM from transitioning to the desired state. This can be determined by reading the status signal data (e.g., scanned from output register 340) and determining that the AFSM has not transitioned to the intended destination state (it remains in the previous state). In various embodiments, a stuck-on-"1" fault at the acknowledgment signal reset state unit 700 can be detected by setting the AFSM to the appropriate state and triggering a reset. If the AFSM is able to reset to the given state, it can be confirmed at reset signal 708 that there is no stuck-on-"1" fault. As will be understood, this can be achieved by toggling the reset signal of AFSM 302 (such as reset signal 336). This can be detected by reading the status signal data (e.g., scanned from output register 340) and determining that it indicates the AFSM includes more than one state.

[0081] Taking ARC unit 600 as an example, a stuck-at-"0" fault at acknowledgment signal 610 can prevent ARC unit 600 from being triggered to generate a transition signal. Therefore, the AFSM may not transition to a given state in response to a trigger input designed to trigger the ARC unit with a fault. This can be determined by reading the status signal data (e.g., scanned from output register 340) and determining that the AFSM has not transitioned to the intended destination state (it remains in the previous state). A stuck-at-"1" fault at acknowledgment signal 610 can create a default state in the AFSM. This can be detected by reading the status signal data (e.g., scanned from output register 340) and determining that it indicates the AFSM includes more than one state.

[0082] A stuck-at-"0 fault at ARC signal 606 can prevent ARC unit 600 from being triggered to generate a transition signal. Therefore, the AFSM may not transition to a given state in response to a trigger input designed to trigger the ARC unit with a fault. This can be determined by reading the status signal data (e.g., scanning from output register 340) and determining that the AFSM has not transitioned to the intended destination state (it remains in the previous state). A stuck-at-"1" fault at ARC signal 606 can produce an unintended punctured state for the AFSM. This can be detected by reading the status signal data (e.g., scanning from output register 340) and determining that the AFSM has transitioned from the intended state to the next state.

[0083] A stuck-at-"0" fault at transition signal 608 can prevent ARC unit 600 from being triggered to generate a transition signal. Therefore, the AFSM may not transition to a given state in response to a trigger input designed to trigger the ARC unit with a fault. This can be determined by reading the status signal data (e.g., scanning from output register 340) and determining that the AFSM has not transitioned to the intended destination state (it remains in the previous state). A stuck-at-"1" fault at transition signal 608 can create a default state in the AFSM. This can be detected by reading the status signal data (e.g., scanning from output register 340) and determining that it indicates the AFSM includes more than one state.

[0084] A stuck-at-"0 fault at disable signal 328 prevents ARC unit 600 from being triggered to generate a transition signal. Therefore, the AFSM may not transition to a given state in response to a trigger input designed to trigger the ARC unit with a fault. This can be determined by reading the status signal data (e.g., scanning from output register 340) and determining that the AFSM has not transitioned to the intended destination state (it remains in its previous state). A stuck-at-"1" fault at disable signal 328 prevents the AFSM's state from being fixed while data is shifted during testing. This can be detected by monitoring the status signal while loading data and disabling the transition, and determining whether a transition has occurred.

[0085] As described above, using a disable signal and loading test data to test the AFSM can detect all potential stuck faults in ARC units and status units (such as ARC unit 600 and status unit 700). This provides the AFSM with more efficient and accurate testing capabilities.

[0086] For unwanted perforation states and faults that cause the AFSM to remain in a given state, the location of the stuck fault can also be determined. The location of the default state can be detected using a one-hot encoding of the state, thus identifying the area of ​​interest within the default state (the location of the stuck fault).

[0087] In various embodiments, test patterns should be generated to test every possible ARC from each state, thereby testing all potential stuck faults. In various embodiments, given the states of the AFSM and ARC that define the AFSM, a graphical algorithm can be utilized. This can be used to determine each possible data input to test each possible state and ARC (such as a Karnaugh map solver, so that for each ARC, there are corresponding test data inputs that allow one ARC to deviate from a given state, and no ARC deviates from the expected state). Finally, patterns for the data inputs can be generated to determine the most efficient sequence for synthesis testing.

[0088] For example, data can be input during a transition to test the first ARC (Autocorrelation Syndrome) outside the initial state. The transition can be enabled and the results recorded. The transition can be disabled again, and data can be input to test different ARCs. The transition can be enabled again and the results recorded. Furthermore, this can continue until all ARCs and states have been tested. Graph algorithms can be used to determine the different inputs used for testing, and pattern generation can be used to determine the order of the sequence of input data.

[0089] Figure 9 A method for testing the failure of an asynchronous finite state machine according to an embodiment is described.

[0090] In various embodiments, the method 900 may include, in step 902, disabling state transitions out of the AFSM state; in step 904, inputting test data into the AFSM to trigger a transition from that state to the desired state; in step 906, enabling state transitions out of the AFSM state; and in step 908, determining whether the AFSM has successfully transitioned to the desired state.

[0091] In various embodiments, the method 900 may further include: wherein determining whether the AFSM has successfully transitioned to the expected state includes determining whether the AFSM is in the expected state and not in any other state.

[0092] In various embodiments, the method 900 may further include: determining that a successful conversion was not performed and concluding that the AFSM includes a stuck fault.

[0093] In various embodiments, the method 900 may further include: determining whether the AFSM has successfully transitioned to the expected state by disabling all state transitions of the AFSM and reading a state signal scanned from the AFSM indicating whether the AFSM is in the expected state.

[0094] In various embodiments, the method 900 may further include: selecting test data to prevent all transitions from deviating from the expected state.

[0095] In various embodiments, the method 900 may further include: wherein disabling state transitions includes disabling all state transitions of the AFSM using a disable signal.

[0096] In various embodiments, the method 900 may further include: wherein the input test data includes serial input into a test register in a shift mode.

[0097] In various embodiments, the method 900 may further include: disabling state transitions out of the state while switching the test register from shift mode to capture mode.

[0098] In various embodiments, the method 900 may further include: determining whether the AFSM has successfully transitioned to the expected state by reading the state signal stored in the output register and serially scanned from the AFSM while disabling the state transition of the AFSM.

[0099] In various embodiments, the method 900 may further include repeating the method for each possible transition from each state of the AFSM.

[0100] Example 1. A method for testing the failure of an asynchronous finite state machine (AFSM), comprising: disabling state transitions out of an AFSM state; inputting test data into the AFSM to trigger a transition from that state to a desired state; enabling transitions out of an AFSM state; and determining whether the AFSM has successfully transitioned to the desired state.

[0101] Example 2. According to the method of Example 1, determining whether the AFSM has successfully transitioned to the expected state includes determining whether the AFSM is in the expected state and not in any other state.

[0102] Example 3. According to the method of Example 1 or Example 2, it further includes determining that the conversion was not successfully performed and concluding that the AFSM includes a stuck fault.

[0103] Example 4. According to the method of Examples 1 to 3, determining whether the AFSM has successfully transitioned to the expected state includes disabling all state transitions of the AFSM and reading the state signal scanned from the AFSM indicating whether the AFSM is in the expected state.

[0104] Example 5. According to the method of Examples 1 to 4, test data is selected to prevent all transitions from deviating from the expected state.

[0105] Example 6. According to the method of Examples 1 to 5, wherein disabling state transitions includes disabling all state transitions of the AFSM using a disable signal.

[0106] Example 7. According to the method of Examples 1 to 6, the input test data includes serial input into the test register in a shift mode.

[0107] Example 8. According to the method of Examples 1 to 7, the state transition from the state is disabled while the test register is switched from shift mode to capture mode.

[0108] Example 9. Determining whether the AFSM has successfully transitioned to the expected state according to the methods of Examples 1 to 8 includes reading the state signal stored in the output register and serially scanned from the AFSM while disabling the state transition of the AFSM.

[0109] Example 10. The method according to Examples 1 to 9 further includes repeating the method for each possible transition from each state of the AFSM.

[0110] Example 11. An asynchronous finite state machine, comprising: a state unit configured to store a value after receiving a transition signal; and an ARC unit configured to generate a transition signal, the asynchronous finite state machine being configured to disable the generation of the transition signal when the asynchronous finite state machine receives a disable signal.

[0111] Example 12. An asynchronous finite state machine according to Example 11, wherein the ARC unit is configured to receive a disable signal.

[0112] Example 13. An asynchronous finite state machine according to Example 11 or Example 12, wherein the ARC unit includes an AND gate configured to receive a disable signal and a transition signal.

[0113] Example 14. An asynchronous finite state machine according to Examples 11 to 13, wherein the ARC unit includes an OR gate configured to receive a trigger signal and receive the output of an AND gate, the transition signal being generated at the output of the OR gate.

[0114] Example 15. A test system includes: an asynchronous finite state machine (AFSM) having an initial state, the asynchronous finite state machine being configured to transition from the initial state to a destination state in response to receiving trigger data; a test register being configured to provide trigger data to the AFSM during a test mode of the test system; and an output register coupled to the AFSM to receive a state signal that changes in response to a state transition of the AFSM, the AFSM being configured to disable the state transition signal in response to an assertion of a disable signal received by the AFSM.

[0115] Example 16. A test system according to Example 15, wherein the test system is configured to assert a disabled signal while trigger data is serially loaded into the test register.

[0116] Example 17. A test system according to Example 15 or Example 16, wherein the output register is configured to serially output data while trigger data is serially loaded into the test register.

[0117] Example 18. The test system according to Examples 15 to 17 further includes a selection port coupled to a test register to provide a selection signal, the test register being configured to switch between a shift mode and a capture mode according to the selection signal.

[0118] Example 19. A test system according to Examples 15 to 18, wherein the test system is configured to invert the selection signal to generate a disable signal.

[0119] Example 20. The test system according to Examples 15 to 19 further includes at least one multiplexer coupled to a test register, the at least one multiplexer being configured to output data received from the test register to the AFSM during test mode.

[0120] Although the invention has been described with reference to illustrative embodiments, this description is not intended to be limiting. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to those skilled in the art upon reference to the specification. Therefore, the appended claims cover any such modifications or embodiments.

Claims

1. A method for testing faults in an asynchronous finite state machine (AFSM), comprising: During the loading of test data into the test register of the system used to test the AFSM, state transitions out of the state of the AFSM are disabled; The test data is input into the AFSM to trigger a transition from the state to the expected state; Enable the transition from the state that is removed from the AFSM; as well as Determine whether the AFSM has successfully transitioned to the expected state.

2. The method of claim 1, wherein determining whether the AFSM has performed the successful transition to the expected state comprises determining whether the AFSM is in the expected state and not in any other state.

3. The method of claim 2, further comprising determining that the successful conversion was not performed and concluding that the AFSM includes a stuck fault.

4. The method of claim 1, wherein determining whether the AFSM has performed the successful transition to the expected state comprises: Disable all state transitions of the AFSM and read the state signal scanned from the AFSM indicating whether the AFSM is in the expected state.

5. The method of claim 1, wherein the test data is selected to prevent any transitions that deviate from the expected state.

6. The method of claim 1, wherein disabling state transitions comprises disabling all state transitions of the AFSM using a disable signal.

7. The method of claim 1, wherein input test data comprises serially inputting it into the test register in a shift mode.

8. The method of claim 7, wherein disabling state transitions out of the state while switching the test register from the shift mode to the capture mode.

9. The method of claim 1, wherein determining whether the AFSM has performed the successful transition to the expected state comprises: While the state transitions of the AFSM are disabled, the state signals stored in the output register and serially scanned from the AFSM are read.

10. The method of claim 1, further comprising repeating the method for each possible transition from each state of the AFSM.

11. An asynchronous finite state machine, comprising: The state unit is configured to store a value after receiving a transition signal; as well as An ARC unit is configured to generate the transition signal, and the asynchronous finite state machine is configured to disable the generation of the transition signal when a disable signal is received by the asynchronous finite state machine, wherein the disable signal is asserted during the loading of test data into the test register of the system used to test the asynchronous finite state machine.

12. The asynchronous finite state machine of claim 11, wherein the ARC unit is configured to receive the disable signal.

13. The asynchronous finite state machine of claim 11, wherein the ARC unit includes an AND gate configured to receive the disable signal and the transition signal.

14. The asynchronous finite state machine of claim 13, wherein the ARC unit includes an OR gate configured to receive a trigger signal and receive the output of the AND gate, the transition signal being generated at the output of the OR gate.

15. A testing system, comprising: An asynchronous finite state machine (AFSM) with an initial state, the asynchronous finite state machine being configured to transition from the initial state to a destination state in response to receiving trigger data; The test register is configured to provide trigger data to the AFSM during the test mode of the test system; as well as An output register, coupled to the AFSM, receives a state signal that changes in response to a state transition of the AFSM, the AFSM being configured to disable the state transition signal in response to an assertion of a disable signal received by the AFSM, the disable signal being asserted during the loading of test data into the test register.

16. The test system of claim 15, wherein the test system is configured to assert the disable signal while the trigger data is serially loaded into the test register.

17. The test system of claim 16, wherein the output register is configured to serially output data while the trigger data is serially loaded into the test register.

18. The test system of claim 16, further comprising a selection port coupled to the test register to provide a selection signal, the test register being configured to switch between a shift mode and a capture mode according to the selection signal.

19. The test system of claim 18, wherein the test system is configured to invert the selection signal to generate the disable signal.

20. The test system of claim 15, further comprising at least one multiplexer coupled to the test register, the at least one multiplexer being configured to output data received from the test register to the AFSM during the test mode.

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