Bus structure, data transmission method and chip

Abstract

The application relates to the chip field, in particular to a bus structure, a data transmission method and a chip. The bus structure comprises: a first processing unit, the sum of distances between each first processing unit and multiple functional units in a first functional unit group is less than a first preset threshold; a second processing unit, the sum of distances between each second processing unit and multiple functional units in a second functional unit group is less than a second preset threshold; and a third processing unit, the third processing unit is used for receiving a first data request and a second data request, sending the first data request and / or the second data request to a target device, receiving reply data returned by the target device, and sending the reply data to the functional unit. Compared with the prior art, the bus structure, the data transmission method and the chip provided by the embodiment of the application have the advantage that the access delay caused by the bus structure can be reduced.

Description

Technical Field

[0001] This invention relates to the field of chips, and more specifically, to a bus structure, a data transmission method, and a chip. Background Technology

[0002] Each chip includes multiple functional units, such as computing units, cache units, and image processing units. Each functional unit, when executing its corresponding function, needs to access external memory to varying degrees. Before accessing external memory, the virtual address corresponding to the functional unit needs to be translated into a physical address by the virtual memory management system and then sent to the external storage device. In this process, the functional unit first needs to query the first-level page table cache. If the first-level page table cache does not contain the corresponding page table storing the physical address, the functional unit needs to send a request to the second-level page table cache for querying. Since a large number of functional units in the chip need to access the second-level page table cache from the first-level page table cache, the chip needs to use a bus structure to support access from the first-level page table cache to the second-level page table cache.

[0003] Currently, large-scale chips generally use traditional bus network structures. For example, in multi-core CPU chips, mesh networks are a widely used on-chip bus, and in GPU chip design, crossbar is a commonly used on-chip bus structure. Mesh networks connect each node to all adjacent nodes, offering advantages such as high speed, a regular structure, and ease of layout. Crossbar bus networks, on the other hand, interconnect each device node with all user nodes, unlike mesh networks where there are connections between device nodes and between user nodes. Mesh, crossbar, and other traditional bus networks all require significant logic circuit resources and wiring resources, and they struggle to flexibly support the irregular distribution of functional units within the chip.

[0004] As the number of functional units in a chip continues to increase and their distribution within the chip becomes more dispersed, the use of these traditional bus structures inevitably increases access latency. Summary of the Invention

[0005] The purpose of this invention is to provide a bus structure, data transmission method, and chip that can reduce access latency caused by the bus structure.

[0006] In a first aspect, the present invention provides a bus structure disposed on a chip, the chip including a plurality of first functional unit groups and a plurality of second functional unit groups, the first functional unit groups including a plurality of functional units conforming to a first preset positional distribution rule, and the second functional unit groups including a plurality of functional units conforming to a second preset positional distribution rule. The bus structure includes: a plurality of first processing units, wherein the plurality of functional units in each of the first functional unit groups are connected to one of the first processing units, the sum of the distances between each of the first processing units and the plurality of functional units in the first functional unit group is less than a first preset threshold, and the first processing unit is used to collect a first data request from the functional units in the first functional unit group; and a plurality of second processing units, wherein each of the second functional unit groups includes a plurality of first processing units, wherein the plurality of first processing units in each of the second functional unit groups is connected to one of the first processing units, and the sum of the distances between each of the first processing units and the plurality of functional units in the first functional unit group is less than a first preset threshold. The first processing unit is used to collect a first data request from the functional units in the first functional unit group; and a plurality of second processing units, wherein the plurality of first processing units in each of the second functional unit groups are connected to one of the first processing units. Multiple functional units are connected to a second processing unit, and the sum of the distances between each second processing unit and multiple functional units in the second functional unit group is less than a second preset threshold. The second processing unit is used to collect second data requests from the functional units in the second functional unit group. A third processing unit is used to receive the first data request collected by the first processing unit and the second data request collected by the second processing unit. The third processing unit is used to send the first data request and / or the second data request to the target device. The third processing unit is also used to receive the response data returned by the target device and send the response data to the functional unit via the first processing unit and / or the second processing unit.

[0007] Compared with the prior art, the bus structure provided in this embodiment of the invention divides the functional units in the chip into multiple functional unit groups, including a first functional unit group and a second functional unit group, according to their positions. A first processing unit is set up for each first functional unit group. The first processing unit acquires data from each functional unit in the first functional unit group. The sum of the distances between each first processing unit and the multiple functional units in the first functional unit group is less than a first preset threshold. At the same time, a second processing unit is set up for each second functional unit group. The second processing unit acquires data from each functional unit in the second functional unit group. The sum of the distances between each second processing unit and the multiple functional units in the second functional unit group is less than a second preset threshold, thereby reducing the data transmission distance when acquiring data requests from functional units and sending reply data to functional units. Meanwhile, a third processing unit is set up to receive the first data requests and second data requests acquired by the first and second processing units and to uniformly send the first data requests and second data requests to the external target device through the third processing unit. The third processing unit also uniformly receives the reply data returned by the target device and sends the reply data to the functional unit through the first processing unit and / or the second processing unit. It is not necessary to build a data channel for data transmission between each functional unit and the external target device, which can also reduce the data transmission distance. Reducing the data transmission distance can effectively reduce the latency during data transmission, thereby reducing the overall access latency of the bus structure.

[0008] In an optional implementation, the first processing unit is connected to the second processing unit, and the second processing unit is connected to the third processing unit. The second processing unit is used to obtain the first data request from the first processing unit; the third processing unit is used to obtain both the first data request and the second data request from the second processing unit. The first processing unit sends the collected first data request to the second processing unit, and the second processing unit then sends the first data request to the third processing unit. This allows for the reuse of the data channel between the second and third processing units, eliminating the need to construct a separate data transmission channel between them and reducing manufacturing costs.

[0009] In an optional implementation, the first processing unit is connected to the third processing unit, and the second processing unit is connected to the third processing unit; the third processing unit is used to obtain the first data request from the first processing unit; the third processing unit is used to obtain the second data request from the second processing unit. The third processing unit obtaining the first data request from the first processing unit and the second data request from the second processing unit can reduce signal interference during data transmission and improve the reliability of data transmission in the bus structure.

[0010] In an optional embodiment, the chip further includes: multiple third functional unit groups; the bus structure further includes multiple fourth processing units; each third functional unit group includes multiple functional units conforming to a third preset positional distribution pattern; multiple functional units in each third functional unit group are connected to one or more fourth processing units; the fourth processing unit is used to collect third data requests from the functional units in the third functional unit group; the third processing unit is used to receive the third data requests collected by the fourth processing unit. Further dividing the functional units in the chip into third functional unit groups according to their positional distribution, and setting fourth functional units for each third functional unit group, further reduces the transmission distance when transmitting third data requests from each functional unit in the third functional unit group, and further reduces the overall data transmission latency of the bus structure.

[0011] In an optional implementation, the bus structure further includes: a plurality of repeaters; the first processing unit, the second processing unit, and the third processing unit are connected via the repeaters.

[0012] In an optional implementation, the plurality of third processing units are connected sequentially via the repeater.

[0013] In an optional implementation, the third processing unit includes a buffer for storing the first data request, the second data request, and the response data.

[0014] Secondly, the present invention provides a data transmission method applied to a bus structure as described in any of the foregoing embodiments. The data transmission method includes: a first processing unit acquiring a first data request from a functional unit in a first functional unit group; a second processing unit acquiring a second data request from a functional unit in a second functional unit group; a third processing unit receiving the first data request acquired by the first processing unit and the second data request acquired by the second processing unit; the third processing unit sending the first data request and / or the second data request to a target device; and the third processing unit receiving response data returned by the target device and sending the response data to the functional unit via the first processing unit and / or the second processing unit.

[0015] In an optional implementation, the third processing unit receiving the first data request collected by the first processing unit and the second data request collected by the second processing unit includes: the first processing unit sending the first data request to the second processing unit; the second processing unit assigning a target weight value to the first data request according to the number of functional units connected to the first processing unit; the second processing unit collecting the second data request and assigning a preset weight value to the second data request; and the second processing unit obtaining a target data request according to the target weight value and the preset weight value, and sending the target data request to the third processing unit.

[0016] Thirdly, the present invention provides a chip comprising: a plurality of first functional unit groups and a plurality of second functional unit groups, wherein the first functional unit groups include a plurality of functional units conforming to a first preset position distribution rule, and the second functional unit groups include a plurality of functional units conforming to a second preset position distribution rule; and a bus structure as described in any of the foregoing embodiments. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the bus structure provided in Embodiment 1 of the present invention;

[0019] Figure 2 This is a schematic diagram of the structure of a chip that includes the bus structure provided in Embodiment 1 of the present invention;

[0020] Figure 3 This is a schematic diagram of the structure of the first processing unit and the second processing unit in the bus structure provided in Embodiment 1 of the present invention;

[0021] Figure 4 This is a schematic diagram of the third processing unit in the bus structure provided in Embodiment 1 of the present invention;

[0022] Figure 5 This is a schematic diagram of the data transmission method provided in Embodiment 2 of the present invention. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0024] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0025] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0026] In the description of this invention, it should be noted that if terms such as "upper," "lower," "inner," or "outer" are used to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of this invention is usually placed, they are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.

[0027] Furthermore, the terms "first" and "second" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0028] It should be noted that, where there is no conflict, the features in the embodiments of the present invention can be combined with each other.

[0029] Please refer to Figure 1 and Figure 2 Embodiment 1 of the present invention provides a bus structure, wherein the bus structure is disposed on a chip, wherein, Figure 1 The diagram shown is a schematic diagram of the bus structure provided in Embodiment 1 of this application. Figure 2 This refers to a chip configured with the bus structure provided in Embodiment 1 of this application. Wherein, as... Figure 1 As shown, the bus structure provided in Embodiment 1 of the present invention includes: multiple first processing units 101, multiple second processing units 102, and a third processing unit 103. The first processing units 101 and the third processing unit 103 are connected, and the second processing units 102 are also connected to the third processing unit 103. Figure 2The diagram shows a chip with the bus structure provided in Embodiment 1 of this application. The chip includes multiple functional units, such as computing units, cache units, and other units within the chip that perform different functions. These multiple functional units can be divided into multiple first functional unit groups 201 and multiple second functional unit groups 202 according to their positional distribution. The first functional unit group 201 includes multiple first functional units 2011 conforming to a first preset positional distribution rule, and the second functional unit group 202 includes multiple second functional unit groups 2021 conforming to a second preset positional distribution rule. The first and second preset positional distribution rules are preset positional distribution conditions. For example, the first preset positional distribution rule can be preset to an array arrangement, and the second preset positional distribution rule can be preset to a point set arrangement. Alternatively, the first preset positional distribution rule can be preset to an axially symmetric distribution, and the second preset positional distribution rule can be preset to not satisfy the first preset positional distribution rule and have an overall distribution area smaller than a preset area. The specific settings can be flexibly configured according to actual needs.

[0030] In this embodiment, multiple functional units in each first functional unit group 201 are connected to a first processing unit 101. The sum of the distances between each first processing unit 101 and the multiple functional units in the first functional unit group 201 is less than a first preset threshold. The first processing unit 101 is used to collect first data requests from the functional units in the first functional unit group 201. Similarly, multiple functional units in each second functional unit group 202 are connected to a second processing unit 102. The sum of the distances between each second processing unit 102 and the multiple functional units in the second functional unit group 202 is less than a second preset threshold. The second processing unit 102 is used to collect second data requests from the functional units in the second functional unit group 202. The first and second preset thresholds are pre-set distance thresholds. The placement of the first and second processing units 101 and 102 can be determined based on these thresholds, resulting in a shorter data transmission distance when the first processing unit 101 collects first data requests from multiple first functional units, and similarly, a shorter data transmission distance when the second processing unit 102 collects second data requests from multiple second functional units.

[0031] Furthermore, in some embodiments of the present invention, a first preset threshold requirement can be added to the first preset position distribution rule. That is, when dividing the first functional unit group 201, if it is impossible to find a position to set the first processing unit 101 such that the sum of the distances between the first processing unit 101 and the multiple first functional units in the first functional unit group 201 is less than the first preset threshold, then the first preset position distribution rule is not satisfied. Specifically, it can be set according to actual needs.

[0032] likeFigure 1 This paper illustrates a specific connection method between the first processing unit 101 and the third processing unit 103, where each first processing unit 101 is connected to the third processing unit 103. In other embodiments of the invention, the connection can be configured based on the placement of the first and third processing units 101. For example, some of the first processing units 101 can be connected to adjacent first processing units 101, and then connected to the third processing unit 103. The specific configuration can be tailored to the actual placement and needs. Similarly, the second processing unit 102 and the third processing unit 103 can be connected in other ways. With this configuration, the third processing unit 103 can directly obtain the first data request from the first processing unit 101 and the second data request from the second processing unit 102, reducing signal interference during data transmission and improving the reliability of data transmission in the bus structure.

[0033] Furthermore, such as Figure 1 The connection between the first processing unit 101 and the third processing unit 103, and the connection between the second processing unit 102 and the third processing unit 103 shown, are merely specific examples in this embodiment of the invention and do not constitute a limitation. In some other embodiments of the invention, the connection may also be as follows. Figure 2 The diagram shows a first processing unit 101 connected to a second processing unit 102, and then the second processing unit 102 connected to a third processing unit 103. After acquiring a first data request from the first functional unit group 201, the first processing unit 101 transmits the first data request to the second processing unit 102. The first data request is then indirectly transmitted to the third processing unit 103 via the second processing unit 102. The first processing unit 101 sends the acquired first data request to the second processing unit 102, and the second processing unit 102 then sends the first data request to the third processing unit 103. This reuses the data channel between the second processing unit 102 and the third processing unit 103, eliminating the need to construct a separate data transmission channel between them and reducing manufacturing costs.

[0034] In some embodiments of the present invention, such as Figure 3 As shown, the second processing unit 102 includes a router 100 and a weighted arbitrator 200. The router 100 receives a first data request from the first functional unit group 201, and the weighted arbitrator 200 sends the first data request sequentially to the third processing unit 103 or the second processing unit 102 according to the weight value of the first data request. The weight value can be set based on factors such as the amount of data requested, the importance of the data, and the urgency of the data. Similarly, as... Figure 3As shown, the response data returned by the third processing unit 103 or the second processing unit 102 can also be transmitted in the same reverse direction to each of the first functional units through the weighted arbitrator 200 and the router 100.

[0035] In some embodiments of the present invention, such as Figure 3 As shown, the second processing unit 102 includes a router 100 and a weighted arbitrator 200. The router 100 receives a first data request from the first processing unit 101 and / or receives second data requests from each functional unit in the second functional unit group 202. The weighted arbitrator 200 sequentially sends the first data request and / or the second data request to the third processing unit 103 according to the weight values ​​of the first data request and / or the second data request. The weight values ​​can be set based on factors such as the amount of data requested, the importance of the data, and the urgency of the data. For example, the weight of the first data request can be set to M based on the number M of functional units in the first functional unit group 201, while the weight of each second data request can be set to 1, etc. The specific settings can be flexibly configured according to actual needs. Similarly, as... Figure 3 As shown, the response data returned by the third processing unit 103 can also be transmitted in the same reverse direction to each of the second functional units or the first processing unit 101 through the weighted arbitrator 200 and the router 100.

[0036] In some embodiments of the present invention, the third processing unit 103 is used to send the acquired first data request and / or second data request to an external target device. For example, the first data request may be a request from a computing unit to request computing data stored in an external storage unit. In this case, the third processing unit 103 sends the first data request to the corresponding external storage unit. The external storage unit returns corresponding response data to the third processing unit 103 based on the first request data. The third processing unit 103 can then transmit the received response data back to the corresponding functional unit via the first processing unit 101 and / or the second processing unit 102. Specifically, for example, the first data request may include the user identification number of the functional unit that sent the first data request. The response data returned by the external target device also includes the user identification number, which is then returned to the third processing unit 103. The third processing unit 103, the second processing unit 102, and the first processing unit 101 then transmit the response data to the functional unit that sent the first data request step by step based on the user identification number.

[0037] In some embodiments of the present invention, such as Figure 2As shown, there can be multiple third processing units 103. These third processing units 103 can be interconnected or independent of each other, depending on the distribution of functional units in the chip and functional requirements. Interconnected third processing units 103 can transmit data to each other. For example... Figure 4 As shown, the third processing unit 103 includes a router 100, a buffer 300 connected to the router 100, and a weighted arbitrator 200 connected to the buffer 300. Taking the third processing unit 103 numbered 1 as an example, it is connected to the third processing units 103 numbered 0 and 2. The router 100 can simultaneously receive first data requests and second data requests from the third processing units 103 numbered 0 and 2, as well as the second processing unit 102. For the received first and second data requests, the router 100 can transmit them to the buffer 300 for buffering, and then, after the weighted arbitrator 200 arbitrates the transmission order, send them sequentially to the third processing unit 103 numbered 0, the third processing unit 103 numbered 2, or an external target device. Similarly, response data from external target devices can be received by router 100, buffered by buffer 300, and arbitrated by weighted arbitrator 200 before being sent sequentially to the third processing unit 103 (numbered 0), the third processing unit 103 (numbered 2), or the second processing unit 102. The weighted arbitrator 200 can assign weight values ​​to each of the first request data, second request data, and response data based on factors such as data volume, importance, and urgency. Then, it randomly selects the first request data, second request data, or response data based on the different weight values ​​and sends it to the corresponding device or processing unit.

[0038] Furthermore, such as Figure 2 As shown, the bus structure also includes multiple repeaters 104, through which the first processing unit 101, the second processing unit 102, and the third processing unit 103 are connected. That is, based on the connection relationship between the first processing unit 101, the second processing unit 102, and the third processing unit 103, the repeaters 104 are used to connect them. For example, the repeaters 104 can connect the first processing unit 101 and the second processing unit 102, or connect the second processing unit 102 and the third processing unit 103, or sequentially connect multiple third processing units 103, etc.

[0039] In some embodiments of the present invention, the chip may include multiple third functional unit groups, and the bus structure may include a fourth processing unit. Each third functional unit group includes multiple functional units distributed according to a third preset positional distribution rule. Multiple functional units in each third functional unit group are connected to one or more fourth processing units. The fourth processing unit is used to collect third data requests from the functional units in the third functional unit group. The third processing unit 103 is used to receive the third data requests collected by the fourth processing unit. Further dividing the functional units in the chip into third functional unit groups according to their positional distribution and setting a fourth functional unit for each third functional unit group further reduces the transmission distance of the third request data in each functional unit within the third functional unit group, and further reduces the overall data transmission latency of the bus structure. It is understood that more classification methods can be used to divide the functional units and more processing units can be set according to actual needs. Specifically, the settings can be configured according to actual requirements.

[0040] Compared with the prior art, the bus structure provided in Embodiment 1 of the present invention divides the functional units in the chip into multiple functional unit groups, including a first functional unit group 201 and a second functional unit group 202, according to their positions. A first processing unit 101 is provided for each first functional unit group 201. The first processing unit 101 obtains data from each functional unit in the first functional unit group 201. The sum of the distances between each first processing unit 101 and the multiple functional units in the first functional unit group 201 is less than a first preset threshold. Simultaneously, a second processing unit 102 is provided for each second functional unit group 202. The second processing unit 102 obtains data from each functional unit in the second functional unit group 202. The distances between each second processing unit 102 and the second functional unit group 202 are... The sum of the distances between the multiple functional units in step 2 is less than a second preset threshold, thereby reducing the data transmission distance when collecting request data from the functional units and sending response data to the functional units. Simultaneously, a third processing unit 103 is configured to receive the first and second request data collected by the first processing unit 101 and the second processing unit 102, and uniformly send the first and second request data to the external target device through the third processing unit 103. The third processing unit 103 also uniformly receives the response data returned by the target device and sends the response data to the functional units via the first processing unit 101 and / or the second processing unit 102. This eliminates the need to build a data channel for data transmission between each functional unit and the external target device, thus reducing the data transmission distance. The reduction in data transmission distance effectively reduces latency during data transmission, thereby reducing the overall access latency of the bus structure.

[0041] Embodiment 2 of the present invention relates to a data transmission method, applied to the bus structure provided in the foregoing embodiments, such as...Figure 5 As shown, the data transmission method includes the following steps:

[0042] Step S101: The first processing unit collects the first data request from the functional unit in the first functional unit group.

[0043] Step S102: The second processing unit collects the second data request from the functional unit in the second functional unit group.

[0044] Step S103: The third processing unit receives the first data request collected by the first processing unit and the second data request collected by the second processing unit.

[0045] Specifically, in this step, depending on the different connection relationships between the first processing unit, the second processing unit, and the third processing unit, the first processing unit may send a first data request to the second processing unit; the second processing unit may assign a target weight value to the first data request based on the number of functional units connected to the first processing unit; the second processing unit may collect a second data request and assign a preset weight value to the second data request; the second processing unit may obtain target request data based on the target weight value and the preset weight value, and send the target request data to the third processing unit. The preset weight value and the target weight value can be set as described in the foregoing embodiments, and will not be repeated here.

[0046] Step S104: The third processing unit sends the first data request and / or the second data request to the target device.

[0047] Step S105: The third processing unit receives the response data returned by the target device and sends the response data to the functional unit via the first processing unit and / or the second processing unit.

[0048] Compared with the prior art, the data transmission method provided in Embodiment 2 of the present invention is applied to the bus structure provided in the foregoing embodiments, and therefore has the same technical effects as those in the foregoing embodiments. For details, please refer to the specific description in the foregoing embodiments, which will not be repeated here.

[0049] Embodiment 3 of the present invention relates to a chip, such as Figure 2 As shown, it includes: multiple functional units, which are divided into multiple first functional unit groups and multiple second functional unit groups. The first functional unit groups include multiple functional units that conform to a first preset position distribution rule, and the second functional unit groups include multiple functional units that conform to a second preset position distribution rule; and a bus structure as provided in the foregoing embodiments.

[0050] Compared with the prior art, the chip provided in Embodiment 3 of the present invention includes the bus structure provided in the foregoing embodiments, and therefore has the same technical effects as those in the foregoing embodiments. For details, please refer to the specific description in the foregoing embodiments, which will not be repeated here.

[0051] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A bus structure, characterized in that, Located on a chip, the chip includes multiple first functional unit groups and multiple second functional unit groups. The first functional unit groups include multiple functional units that conform to a first preset positional distribution pattern, and the second functional unit groups include multiple functional units that conform to a second preset positional distribution pattern. The bus structure includes: Multiple first processing units, each of the multiple functional units in the first functional unit group is connected to one first processing unit, the sum of the distances between each first processing unit and the multiple functional units in the first functional unit group is less than a first preset threshold, and the first processing unit is used to collect the first data request from the functional units in the first functional unit group. Multiple second processing units, each of the multiple functional units in the second functional unit group is connected to one second processing unit, the sum of the distances between each second processing unit and the multiple functional units in the second functional unit group is less than a second preset threshold, and the second processing unit is used to collect the second data requests of the functional units in the second functional unit group; The third processing unit is configured to receive the first data request collected by the first processing unit and the second data request collected by the second processing unit, and to send the first data request and / or the second data request to the target device. The third processing unit is also configured to receive the response data returned by the target device and send the response data to the functional unit via the first processing unit and / or the second processing unit.

2. The bus structure according to claim 1, characterized in that, The first processing unit is connected to the second processing unit, and the second processing unit is connected to the third processing unit; The second processing unit is used to obtain the first data request from the first processing unit; The third processing unit is used to obtain the first data request and the second data request from the second processing unit.

3. The bus structure according to claim 1, characterized in that, The first processing unit is connected to the third processing unit, and the second processing unit is connected to the third processing unit; The third processing unit is used to obtain the first data request from the first processing unit; The third processing unit is used to obtain the second data request from the second processing unit.

4. The bus structure according to claim 1, characterized in that, The chip further includes: multiple third functional unit groups; the bus structure further includes multiple fourth processing units; the third functional unit groups include multiple functional units that conform to a third preset position distribution rule. Multiple functional units in each of the third functional unit groups are connected to one or more of the fourth processing units, and the fourth processing units are used to collect third data requests from the functional units in the third functional unit groups. The third processing unit is used to receive the third data request collected by the fourth processing unit.

5. The bus structure according to claim 1, characterized in that, The bus structure also includes: multiple repeaters; The first processing unit, the second processing unit, and the third processing unit are connected via the repeater.

6. The bus structure according to claim 5, characterized in that, Multiple third processing units are connected sequentially via the repeater.

7. The bus structure according to any one of claims 1 to 6, characterized in that, The third processing unit includes a cache for storing the first data request, the second data request, and the response data.

8. A data transmission method, characterized in that, Applied to the bus structure as described in any one of claims 1-7, the data transmission method includes: The first processing unit collects the first data request from the functional unit in the first functional unit group; The second processing unit collects the second data requests from the functional units in the second functional unit group; The third processing unit receives the first data request collected by the first processing unit and the second data request collected by the second processing unit. The third processing unit sends the first data request and / or the second data request to the target device. The third processing unit receives the response data returned by the target device and sends the response data to the functional unit via the first processing unit and / or the second processing unit.

9. The data transmission method according to claim 8, characterized in that, The third processing unit receives the first data request collected by the first processing unit and the second data request collected by the second processing unit, including: The first processing unit sends the first data request to the second processing unit, and the second processing unit assigns a target weight value to the first data request according to the number of functional units connected to the first processing unit; The second processing unit collects the second data request and assigns a preset weight value to the second data request; The second processing unit obtains the target data request based on the target weight value and the preset weight value, and sends the target data request to the third processing unit.

10. A chip, characterized in that, include: Multiple first functional unit groups and multiple second functional unit groups, wherein the first functional unit groups include multiple functional units that conform to a first preset position distribution pattern, and the second functional unit groups include multiple functional units that conform to a second preset position distribution pattern; And the bus structure as described in any one of claims 1 to 7.

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