Gate driving circuit, driving method of gate driving circuit, and display substrate

Abstract

Embodiments of the present application provide a gate drive circuit, a driving method of the gate drive circuit and a display substrate. The gate drive circuit comprises a second input sub-circuit, a gate control sub-circuit, a first input sub-circuit, an output control sub-circuit, a first output sub-circuit and a second output sub-circuit. The second input sub-circuit is configured to control the on-off of the gate control sub-circuit and the input of the second voltage of the output control sub-circuit. The first input sub-circuit is configured to control the input of the third voltage of the output control sub-circuit. The gate control sub-circuit is configured to pull down the voltage of the control end of the second output sub-circuit. The output control sub-circuit is configured to control the voltage of the control end of the first output sub-circuit and the second output sub-circuit. The second output sub-circuit is configured to output a second signal when turned on. The second output sub-circuit can stably output the second signal under the control of the gate control sub-circuit, and the stability of the gate drive circuit when outputting a signal can be improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a gate driving circuit, a driving method for the gate driving circuit, and a display substrate. Background Technology

[0002] In current display devices, the gate driving circuit usually adopts the array substrate row driving circuit (Gate Driven on Array, or GOA for short). However, due to factors such as process deviations, the stability of the gate driving circuit output signal is low. Summary of the Invention

[0003] The purpose of this application is to provide a gate driving circuit, a driving method for the gate driving circuit, and a display substrate to improve the stability of the gate driving circuit output signal. The specific technical solution is as follows:

[0004] In a first aspect, embodiments of this application provide a gate driving circuit, the circuit comprising:

[0005] Second input sub-circuit, gate control sub-circuit, first input sub-circuit, output control sub-circuit, first output sub-circuit, second output sub-circuit;

[0006] The second input sub-circuit is connected to the output control sub-circuit and the gate control sub-circuit respectively; the first input sub-circuit is connected to the output control sub-circuit; the output control sub-circuit is connected to the first output sub-circuit and the second output sub-circuit respectively; the gate control sub-circuit is connected to the second output circuit.

[0007] The second input sub-circuit is used to control the on / off state of the gate control sub-circuit and to control the input of the second voltage of the output control sub-circuit.

[0008] The first input sub-circuit is used to control the input of the third voltage of the output control sub-circuit;

[0009] The gate control sub-circuit is used to control the on / off state of the second output sub-circuit;

[0010] The output control sub-circuit is used to control the voltage at the control terminals of the first output sub-circuit and the second output sub-circuit;

[0011] The first output sub-circuit is used to output a first signal when it is turned on;

[0012] The second output sub-circuit is used to output a second signal when it is turned on.

[0013] In one possible implementation, the second input sub-circuit includes a first transistor;

[0014] The control terminal of the first transistor is connected to the first clock signal terminal, the first terminal of the first transistor is connected to the second voltage input terminal, and the second terminal of the first transistor is connected to the output control sub-circuit and the gate control sub-circuit, respectively.

[0015] In one possible implementation, the first input sub-circuit includes a third transistor and a fourth transistor;

[0016] The control terminal of the third transistor is connected to the control signal terminal, the first terminal of the third transistor is connected to the output control sub-circuit, and the second terminal of the third transistor is connected to the first terminal of the fourth transistor.

[0017] The control terminal of the fourth transistor is connected to the second clock signal terminal, and the second terminal of the fourth transistor is connected to the third voltage input terminal.

[0018] In one possible implementation, the output control sub-circuit includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor;

[0019] The control terminal of the fifth transistor is connected to the second terminal of the first transistor and the first terminal of the third transistor, the first terminal of the fifth transistor is connected to the second clock signal terminal, and the second terminal of the fifth transistor is connected to the first terminal of the sixth transistor.

[0020] The control terminal of the sixth transistor is connected to the second clock signal terminal, and the second terminal of the sixth transistor is connected to the first terminal of the seventh transistor, the control terminal of the eighth transistor, and the first output sub-circuit, respectively.

[0021] The control terminal of the seventh transistor is connected to the second terminal of the eighth transistor, and the second terminal of the seventh transistor is connected to the third voltage input terminal;

[0022] The first terminal of the eighth transistor is connected to the third voltage input terminal, and the second terminal of the eighth transistor is connected to the second output sub-circuit.

[0023] In one possible implementation, the output control sub-circuit includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor;

[0024] The control terminal of the fifth transistor is connected to the second terminal of the first transistor and the first terminal of the third transistor, the first terminal of the fifth transistor is connected to the second clock signal terminal, and the second terminal of the fifth transistor is connected to the first terminal of the sixth transistor.

[0025] The control terminal of the sixth transistor is connected to the second clock signal terminal, and the second terminal of the sixth transistor is connected to the first terminal of the seventh transistor, the control terminal of the eighth transistor, and the first output sub-circuit, respectively.

[0026] The control terminal of the seventh transistor is connected to the second terminal of the eighth transistor, and the second terminal of the seventh transistor is connected to the fourth voltage input terminal;

[0027] The first terminal of the eighth transistor is connected to the fourth voltage input terminal, and the second terminal of the eighth transistor is connected to the second output sub-circuit.

[0028] In one possible implementation, the first output sub-circuit includes a ninth transistor and a first capacitor;

[0029] The control terminal of the ninth transistor is connected to the second terminal of the sixth transistor, the first terminal of the seventh transistor, the control terminal of the eighth transistor, and the second terminal of the first capacitor. The first terminal of the ninth transistor is connected to the first terminal of the first capacitor and the third voltage input terminal. The second terminal of the ninth transistor is connected to the signal output terminal.

[0030] In one possible implementation, the second output sub-circuit includes a tenth transistor;

[0031] The control terminal of the tenth transistor is connected to the gate control sub-circuit and the second terminal of the eighth transistor, the first terminal of the tenth transistor is connected to the signal output terminal, and the second terminal of the tenth transistor is connected to the first voltage input terminal.

[0032] In one possible implementation, the second output sub-circuit further includes a second capacitor; a first terminal of the second capacitor is connected to a first terminal of the tenth transistor, and a second terminal of the second capacitor is connected to a control terminal of the tenth transistor.

[0033] In one possible implementation, the output control sub-circuit further includes an eleventh transistor, the control terminal of which is connected to the first voltage input terminal, the first terminal of which is connected to the second terminal of the first transistor and the first terminal of the third transistor, and the second terminal of which is connected to the control terminal of the fifth transistor.

[0034] In one possible implementation, the gate control sub-circuit includes a second transistor;

[0035] The control terminal of the second transistor is connected to the second terminal of the first transistor, the first terminal of the second transistor is connected to the second voltage input terminal, and the second terminal of the second transistor is connected to the control terminal of the tenth transistor, the control terminal of the seventh transistor, and the second terminal of the eighth transistor, respectively.

[0036] In one possible implementation, the second transistor is an oxide transistor, and the remaining transistors are low-temperature polysilicon transistors.

[0037] In one possible implementation, the second signal is a clock signal or a first voltage.

[0038] Secondly, embodiments of this application provide a driving method for a gate driving circuit, used to drive any of the gate driving circuits described in the first aspect above, the method comprising:

[0039] In the first stage, the control signal terminal outputs a first-level signal; the first clock signal terminal outputs a second-level signal; the second clock signal terminal outputs a first-level signal; and the first voltage input terminal outputs a second-level signal.

[0040] In the second stage, the control signal terminal outputs a first-level signal; the first clock signal terminal outputs a first-level signal; the second clock signal terminal outputs a second-level signal; and the first voltage input terminal outputs a second-level signal.

[0041] In the third stage, the control signal terminal outputs a second-level signal; the first clock signal terminal outputs a second-level signal; the second clock signal terminal outputs a first-level signal; and the first voltage input terminal outputs a second-level signal.

[0042] In the fourth stage, the control signal terminal outputs a second-level signal; the first clock signal terminal outputs a first-level signal; the second clock signal terminal outputs a second-level signal; and the first voltage input terminal outputs a second-level signal.

[0043] The first level signal and the second level signal are signals with opposite high and low levels.

[0044] In one possible implementation, the second transistor is an N-type transistor, and the remaining transistors are P-type transistors;

[0045] The first level signal is high level, and the second level signal is low level.

[0046] Thirdly, embodiments of this application provide a display substrate, the display substrate including any of the gate driving circuits described in the first aspect above.

[0047] Fourthly, embodiments of this application provide a display device, the display device including the display substrate as described in the third aspect above.

[0048] Beneficial effects of the embodiments in this application:

[0049] This application provides a gate driving circuit, a driving method for the gate driving circuit, and a display substrate. The gate driving circuit includes: a second input sub-circuit, a gate control sub-circuit, a first input sub-circuit, an output control sub-circuit, a first output sub-circuit, and a second output sub-circuit. The second input sub-circuit is connected to the output control sub-circuit and the gate control sub-circuit, respectively. The first input sub-circuit is connected to the output control sub-circuit. The output control sub-circuit is connected to the first output sub-circuit and the second output sub-circuit, respectively. The gate control sub-circuit is connected to the second output sub-circuit. The second input sub-circuit is used to control the on / off state of the gate control sub-circuit and to control the input of a second voltage to the output control sub-circuit. The first input sub-circuit is used to control the input of a third voltage to the output control sub-circuit. The gate control sub-circuit is used to control the on / off state of the second output sub-circuit. The output control sub-circuit is used to control the voltages at the control terminals of the first and second output sub-circuits. The first output sub-circuit is used to output a first signal when it is on. The second output sub-circuit is used to output a second signal when it is on. By controlling the on / off state of the control terminal of the second output sub-circuit through the gate control sub-circuit, the second output sub-circuit can stably output the second signal under the control of the gate control sub-circuit, thereby reducing the step when the second output sub-circuit outputs the second signal and improving the stability of the gate drive circuit output signal.

[0050] Of course, implementing any product or method of this application does not necessarily require achieving all of the advantages described above at the same time. Attached Figure Description

[0051] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other embodiments can be obtained based on these drawings.

[0052] Figure 1 This is a schematic diagram of a first structure of the gate driving circuit provided in an embodiment of this application;

[0053] Figure 2 This is a schematic diagram of a second structure of the gate drive circuit provided in an embodiment of this application;

[0054] Figure 3 This is a schematic diagram of a third structure of the gate drive circuit provided in an embodiment of this application;

[0055] Figure 4 This is a schematic diagram of a fourth structure of the gate drive circuit provided in the embodiments of this application;

[0056] Figure 5 A schematic diagram of a fifth structure of the gate drive circuit provided in an embodiment of this application;

[0057] Figure 6 A schematic diagram of a sixth structure of the gate drive circuit provided in an embodiment of this application;

[0058] Figure 7 A seventh structural schematic diagram of the gate drive circuit provided in the embodiments of this application;

[0059] Figure 8 A schematic diagram of an eighth structure of the gate drive circuit provided in an embodiment of this application;

[0060] Figure 9 A ninth structural schematic diagram of the gate drive circuit provided in the embodiments of this application;

[0061] Figure 10 A schematic diagram of the tenth structure of the gate driving circuit provided in the embodiments of this application;

[0062] Figure 11 Based on Figure 10 The diagram shows a schematic of the gate drive circuit in the first stage.

[0063] Figure 12 Based on Figure 10 The diagram shows the signal timing sequence of the gate drive circuit in the first stage.

[0064] Figure 13 Based on Figure 10 The diagram shows a gate drive circuit in the second stage.

[0065] Figure 14 Based on Figure 10 The diagram shows the signal timing of the gate drive circuit in the second stage.

[0066] Figure 15 Based on Figure 10 The diagram shows a gate drive circuit in the third stage.

[0067] Figure 16 Based on Figure 10 The diagram shows the signal timing of the gate drive circuit in the third stage.

[0068] Figure 17 Based on Figure 10 The diagram shows a gate drive circuit in the fourth stage.

[0069] Figure 18 Based on Figure 10 The diagram shows the signal timing of the gate drive circuit in the fourth stage.

[0070] Figure 19a This is a schematic diagram of the threshold voltage VTH process margin (amplitude) of the GOA circuit in related technologies;

[0071] Figure 19b A schematic diagram of the threshold voltage VTH process margin of the gate drive circuit provided in the embodiments of this application;

[0072] Figure 20 This is a schematic diagram of a display substrate provided in an embodiment of this application;

[0073] Figure 21 This is a schematic diagram of a display device provided in an embodiment of this application. Detailed Implementation

[0074] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art based on this application are within the scope of protection of this application.

[0075] In current display devices, the gate driving circuit usually adopts the array substrate row driving circuit (Gate Driven on Array, or GOA for short). However, due to factors such as process deviations, the stability of the gate driving circuit output signal is low.

[0076] To improve the stability of the gate drive circuit output signal, embodiments of this application provide a gate drive circuit, a driving method for the gate drive circuit, and a display substrate.

[0077] Next, a gate driving circuit 1 provided in the embodiments of this application will be described in detail, see [link to relevant documentation]. Figure 1 The circuit includes:

[0078] Second input sub-circuit 11, gate control sub-circuit 12, first input sub-circuit 13, output control sub-circuit 14, first output sub-circuit 15, second output sub-circuit 16;

[0079] The second input sub-circuit 11 is connected to the output control sub-circuit 14 and the gate control sub-circuit 12 respectively; the first input sub-circuit 13 is connected to the output control sub-circuit 14; the output control sub-circuit 14 is connected to the first output sub-circuit 15 and the second output sub-circuit 16 respectively; the gate control sub-circuit 12 is connected to the second output sub-circuit 16.

[0080] The second input sub-circuit 11 is used to control the on / off state of the gate control sub-circuit 12 and to control the input of the second voltage of the output control sub-circuit 14.

[0081] The first input sub-circuit 13 is used to control the input of the third voltage to the output control sub-circuit 14;

[0082] The gate control sub-circuit 12 is used to control the on / off state of the second output sub-circuit 16;

[0083] The output control sub-circuit 14 is used to control the voltage at the control terminals of the first output sub-circuit 15 and the second output sub-circuit 16;

[0084] The first output sub-circuit 15 is used to output a first signal when it is turned on;

[0085] The second output sub-circuit 16 is used to output a second signal when it is turned on.

[0086] The second voltage can be either high or low, the third voltage can be either high or low, the first signal can be either high or low, and the second signal can be either high or low. These four can be customized according to actual conditions, but it is necessary to ensure that the first signal and the second signal are signals with opposite high and low levels. In one example, the second input sub-circuit is a low-voltage input sub-circuit, and the first input sub-circuit is a high-voltage input sub-circuit; the second voltage is a second low-voltage signal, and the third voltage is a first high-voltage signal; the first signal is a first high-voltage signal, and the second signal can be a clock signal or a low-voltage signal. The second output sub-circuit responds to the control of both the gate control sub-circuit and the output control sub-circuit by turning the second voltage on or off. When the gate control sub-circuit is on, it outputs the second low-voltage signal to the control terminal of the second output sub-circuit. In this case, the second output sub-circuit is on, stably outputting the second signal.

[0087] In this embodiment, the second output sub-circuit control terminal is switched on and off by the gate control sub-circuit, so that the second output sub-circuit can stably output the second signal under the control of the gate control sub-circuit. This reduces the step when the second output sub-circuit outputs the second signal and improves the stability of the gate drive circuit outputting the signal.

[0088] In one possible implementation, see Figure 2 The second input sub-circuit 11 includes a first transistor T1;

[0089] The control terminal of the first transistor T1 is connected to the first clock signal terminal ECK, the first terminal of the first transistor T1 is connected to the second voltage input terminal VGL2, and the second terminal of the first transistor T1 is connected to the output control sub-circuit 14 and the gate control sub-circuit 12 respectively.

[0090] In one example, the second voltage input terminal VGL2 is the second low voltage signal input terminal. In the embodiments of this application, the first transistor controls the on / off state of the gate control sub-circuit and controls the input of the second low voltage signal to the output control sub-circuit.

[0091] In one possible implementation, see Figure 3 The first input sub-circuit 13 includes a third transistor T3 and a fourth transistor T4;

[0092] The control terminal of the third transistor T3 is connected to the control signal terminal ESTV, the first terminal of the third transistor T3 is connected to the output control sub-circuit 14, and the second terminal of the third transistor T3 is connected to the first terminal of the fourth transistor T4.

[0093] The control terminal of the fourth transistor T4 is connected to the second clock signal terminal ECB, and the second terminal of the fourth transistor T4 is connected to the third voltage input terminal VGH.

[0094] The third voltage input terminal VGH is the first high voltage signal input terminal. VGH can be used to turn on or off the TFT (Thin Film Transistor) in the display area of ​​the display panel.

[0095] In some embodiments, the control signal terminal ESTV is used as the frame start signal of the gate drive circuit. Under the control of the second clock signal terminal ECB and ESTV, the first input sub-circuit can quickly input the first high voltage signal to the control terminal of the output control sub-circuit 14, and timely control the shutdown of the output control sub-circuit 14, thereby controlling the erroneous output of the first output sub-circuit 15.

[0096] In this embodiment, the input of the first high-voltage signal to the output control sub-circuit is controlled by the third transistor and the fourth transistor.

[0097] In one possible implementation, see Figure 4 The output control sub-circuit 14 includes a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8;

[0098] The control terminal of the fifth transistor T5 is connected to the second terminal of the first transistor T1 and the first terminal of the third transistor T3, respectively. The first terminal of the fifth transistor T5 is connected to the second clock signal terminal ECB, and the second terminal of the fifth transistor T5 is connected to the first terminal of the sixth transistor T6.

[0099] The control terminal of the sixth transistor T6 is connected to the second clock signal terminal ECB, and the second terminal of the sixth transistor T6 is connected to the first terminal of the seventh transistor T7, the control terminal of the eighth transistor T8, and the first output sub-circuit 15, respectively.

[0100] The control terminal of the seventh transistor T7 is connected to the second terminal of the eighth transistor T8, and the second terminal of the seventh transistor T7 is connected to the third voltage input terminal VGH.

[0101] The first terminal of the eighth transistor T8 is connected to the third voltage input terminal VGH, and the second terminal of the eighth transistor T8 is connected to the second output sub-circuit 16.

[0102] In the embodiments of this application, the voltages of the control terminals of the first output sub-circuit and the second output sub-circuit are controlled by the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor.

[0103] In one possible implementation, see Figure 5 The output control sub-circuit 14 includes a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8;

[0104] The control terminal of the fifth transistor T5 is connected to the second terminal of the first transistor T1 and the first terminal of the third transistor T3, respectively. The first terminal of the fifth transistor T5 is connected to the second clock signal terminal ECB, and the second terminal of the fifth transistor T5 is connected to the first terminal of the sixth transistor T6.

[0105] The control terminal of the sixth transistor T6 is connected to the second clock signal terminal ECB, and the second terminal of the sixth transistor T6 is connected to the first terminal of the seventh transistor T7, the control terminal of the eighth transistor T8, and the first output sub-circuit 15, respectively.

[0106] The control terminal of the seventh transistor T7 is connected to the second terminal of the eighth transistor T8, and the second terminal of the seventh transistor T7 is connected to the fourth voltage input terminal VGH2.

[0107] The first terminal of the eighth transistor T8 is connected to the fourth voltage input terminal VGH2, and the second terminal of the eighth transistor T8 is connected to the second output sub-circuit 16.

[0108] The fourth voltage input terminal, VGH2, is the second high-voltage signal input terminal. In one example, the voltage value of VGH2 is higher than the voltage value of VGH, thus ensuring that the first output sub-circuit will not output VGH after VGH2 pulls up the gate voltage of the first output sub-circuit.

[0109] In this embodiment, the voltages of the control terminals of the first and second output sub-circuits are controlled by the fifth, sixth, seventh, and eighth transistors. The third voltage input terminal VGH is changed to the fourth voltage input terminal VGH2, and two different signal sources, VGH and VGH2, are set to ensure that the first output sub-circuit will not output VGH after VGH2 pulls up the gate voltage of the first output sub-circuit, thus satisfying the GOA driving requirement.

[0110] In some embodiments, under the control of the gate control sub-circuit 12, the seventh transistor T7 can quickly output the fourth voltage input terminal VGH2 to the first output sub-circuit 15 and turn off the first output sub-circuit 15; thereby ensuring that under the control of the gate control sub-circuit 12, the second output sub-circuit 16 is turned on and the first output sub-circuit 15 is turned off, so as to achieve stable output of the GOA signal.

[0111] In one possible implementation, see Figure 6 ,based on Figure 4 The gate drive circuit shown includes a ninth transistor T9 and a first capacitor C1 in the first output sub-circuit 15.

[0112] The control terminal of the ninth transistor T9 is connected to the second terminal of the sixth transistor T6, the first terminal of the seventh transistor T7, the control terminal of the eighth transistor T8, and the second terminal of the first capacitor C1. The first terminal of the ninth transistor T9 is connected to the first terminal of the first capacitor C1 and the third voltage input terminal VGH. The second terminal of the ninth transistor T9 is connected to the signal output terminal EOUT.

[0113] In one possible embodiment, it can also be based on Figure 5 The gate drive circuit shown includes a first output sub-circuit 15 comprising a ninth transistor T9 and a first capacitor C1, which will not be described in detail here.

[0114] In this embodiment, a first high-voltage signal is output by the ninth transistor when it is turned on.

[0115] In one possible implementation, see Figure 7 ,based on Figure 6 The gate drive circuit shown includes a second output sub-circuit 16, which includes a tenth transistor T10.

[0116] The control terminal of the tenth transistor T10 is connected to the gate control sub-circuit 12 and the second terminal of the eighth transistor T8, respectively. The first terminal of the tenth transistor T10 is connected to the signal output terminal EOUT, and the second terminal of the tenth transistor T10 is connected to the first voltage input terminal VGL.

[0117] The first voltage input terminal VGL is the first low voltage signal input terminal. VGL can be used to turn on or off the TFT (Thin Film Transistor) in the display area of ​​the display panel. In one example, the voltage value of VGL2 is less than the voltage value of VGL, and the difference between the voltage values ​​of VGL2 and VGL is sufficient to enable T10.

[0118] In one possible embodiment, Figure 7 In the gate drive circuit shown, the second terminal of the seventh transistor T7 can be connected to the fourth voltage input terminal VGH2, and the first terminal of the eighth transistor T8 can be connected to the fourth voltage input terminal VGH2. This will not be elaborated further.

[0119] In this embodiment, a first low voltage signal or a clock signal is output when the tenth transistor is turned on.

[0120] In one possible implementation, the control terminal of the tenth transistor T10 is connected to the gate control sub-circuit 12 and the second terminal of the eighth transistor T8, the first terminal of the tenth transistor T10 is connected to the signal output terminal EOUT, and the second terminal of the tenth transistor T10 is connected to the second clock signal ECB.

[0121] In one possible implementation, see Figure 8 ,based on Figure 7 The gate drive circuit shown includes a second output sub-circuit 16, which further includes a second capacitor C2. The first end of the second capacitor C2 is connected to the first end of the tenth transistor T10, and the second end of the second capacitor C2 is connected to the control terminal of the tenth transistor T10.

[0122] In this embodiment of the application, the second capacitor can stabilize the system. Figure 8 The potential at point N1 shown in the figure.

[0123] In one possible embodiment, Figure 8 In the gate drive circuit shown, the second terminal of the seventh transistor T7 can be connected to the fourth voltage input terminal VGH2, and the first terminal of the eighth transistor T8 can be connected to the fourth voltage input terminal VGH2. This will not be elaborated further.

[0124] In one possible implementation, see Figure 9 ,based on Figure 8 The gate drive circuit shown includes an output control sub-circuit that further includes an eleventh transistor T11. The control terminal of the eleventh transistor T11 is connected to the first voltage input terminal VGL. The first terminal of the eleventh transistor T11 is connected to the second terminal of the first transistor T1 and the first terminal of the third transistor T3, respectively. The second terminal of the eleventh transistor T11 is connected to the control terminal of the fifth transistor T5.

[0125] In one possible embodiment, Figure 9 In the gate drive circuit shown, the second terminal of the seventh transistor T7 can be connected to the fourth voltage input terminal VGH2, and the first terminal of the eighth transistor T8 can be connected to the fourth voltage input terminal VGH2. This will not be elaborated further.

[0126] The control terminal of the eleventh transistor T11 is connected to the first voltage input terminal VGL. When the eleventh transistor T11 is a P-type transistor, the eleventh transistor T11 is normally open. In the embodiments of this application, the eleventh transistor T11 can prevent the disturbance current at the gate terminal of T5 from flowing back into T1, T2 and T3, and the eleventh transistor can protect the first transistor, the second transistor and the third transistor.

[0127] In one possible implementation, see Figure 10 ,based on Figure 7 The pixel circuit shown includes a second transistor T2 in the gate control sub-circuit 12.

[0128] The control terminal of the second transistor T2 is connected to the second terminal of the first transistor T1, the first terminal of the second transistor T2 is connected to the second voltage input terminal VGL2, and the second terminal of the second transistor T2 is connected to the control terminal of the tenth transistor T10, the control terminal of the seventh transistor T7, and the second terminal of the eighth transistor T8, respectively.

[0129] In one possible embodiment, it can also be based on Figure 8 The gate drive circuit shown includes a gate control sub-circuit 12 comprising a second transistor T2; it can also be based on... Figure 9 The gate drive circuit shown includes a second transistor T2 in the gate control sub-circuit 12, which will not be described in detail here.

[0130] In this embodiment, the voltage at the control terminal of the tenth transistor is pulled down by the second transistor.

[0131] In one possible implementation, the second transistor T2 is an oxide transistor, and the remaining transistors are low-temperature polysilicon transistors.

[0132] LTPO (Low Temperature Polycrystalline Oxide) screen technology can achieve a minimum refresh rate of 1Hz. A lower refresh rate results in lower power consumption, which can save a significant amount of power.

[0133] In some embodiments, the gate control sub-circuit 12 is connected to the same second voltage input terminal VGL2, and the second transistor T2 is an oxide transistor to control the transmission of VGL2 to the tenth transistor T10 of the second output sub-circuit 16 (typically the second transistor T2 is a low temperature polysilicon transistor) to control the frequency of the gate drive circuit, thereby saving a lot of power by reducing the refresh rate.

[0134] The gate driving circuit provided in this application for LTPO screens can drive oxide pixel electrodes and can be composed of 9 LTPS (Low Temperature Poly-Silicon) transistors, 1 oxide transistor, and 1 capacitor. Compared with current gate driving circuits, the gate driving circuit provided in this application can meet the pixel driving requirements while simplifying the device.

[0135] In one possible implementation, the second signal is a clock signal or a first voltage.

[0136] The second signal can be either a clock signal or the first low-voltage signal.

[0137] This application embodiment also provides a driving method for a gate driving circuit, used to drive any of the gate driving circuits 1 described in the above embodiments, the method comprising:

[0138] In the first stage, the control signal terminal ESTV outputs a first-level signal; the first clock signal terminal ECK outputs a second-level signal; the second clock signal terminal ECB outputs a first-level signal; and the first voltage input terminal VGL outputs a second-level signal.

[0139] In the second stage, the control signal terminal ESTV outputs a first-level signal; the first clock signal terminal ECK outputs a first-level signal; the second clock signal terminal ECB outputs a second-level signal; and the first voltage input terminal VGL outputs a second-level signal.

[0140] In the third stage, the control signal terminal ESTV outputs a second-level signal; the first clock signal terminal ECK outputs a second-level signal; the second clock signal terminal ECB outputs a first-level signal; and the first voltage input terminal VGL outputs a second-level signal.

[0141] In the fourth stage, the control signal terminal ESTV outputs a second-level signal; the first clock signal terminal ECK outputs a first-level signal; the second clock signal terminal ECB outputs a second-level signal; and the first voltage input terminal VGL outputs a second-level signal.

[0142] The first level signal and the second level signal are signals with opposite high and low levels.

[0143] In the embodiments of this application, the working state of the gate drive circuit at different stages is controlled by outputting different level signals at different stages.

[0144] It is understood that any transistor in the circuit of this application can be an N-type transistor or a P-type transistor, whichever can be selected according to the actual situation; the control terminal of the transistor is the gate, the first terminal of the transistor is the source or drain, and the second terminal of the transistor is the drain or source corresponding to the first terminal. In one possible implementation, the second transistor T2 is an N-type transistor, and the remaining transistors are P-type transistors;

[0145] The first level signal is high level, and the second level signal is low level.

[0146] It is understood that the transistor can be either a P-type transistor or an N-type transistor, and the specific choice can be made according to the actual situation. However, the connection method of the circuit components needs to be adjusted accordingly, and the alternative solution is still within the protection scope of this application.

[0147] It is understood that the transistors used in the circuit of this application may be MOS transistors (metal-oxide-semiconductor field-effect transistors), TFT transistors (thin film transistors), or other types of transistors. The specific choice can be made according to the actual situation, and the alternative solutions are still within the protection scope of this application.

[0148] In the above embodiments, the switching of each transistor is controlled by different level signals, so as to control the working state of the gate drive circuit at different stages.

[0149] The following describes the driving method of gate drive circuit 1 in detail, taking the second transistor T2 as an N-type transistor and the other transistors as P-type transistors as an example:

[0150] See Figure 11 and Figure 12 , Figure 11 For based on Figure 10 The diagram shows the gate drive circuit in the first stage. Figure 12 For based on Figure 10 The diagram shows the signal timing of the gate drive circuit in the first stage. In the first stage, the control signal terminal ESTV (STV) is high, and the third transistor T3 is off; the first clock signal terminal ECK (CK) is low, and the first transistor T1 is on, with the potential at point N2 being VGL2. Since the gate and drain potentials of the second transistor T2 are both VGL2, T2 is on, and the potential at N1 is VGL2. The seventh transistor T7 is on, the potential at N4 is VGH, and the ninth transistor T9 and the eighth transistor T8 are off. The second clock signal terminal ECB (CB) is high, and the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are off. The potential at N1 is VGL2, which is less than VGL, so the tenth transistor T10 is on, and the signal output terminal EOUT outputs VGL.

[0151] See Figure 13 and Figure 14 , Figure 13 For based on Figure 10 The diagram shows the gate drive circuit in the second stage. Figure 14 For based on Figure 10 The diagram shows the signal timing of the gate drive circuit in the second stage. In the second stage, the control signal terminal ESTV is high, and the third transistor T3 is off; the first clock signal terminal ECK is high, and the first transistor T1 is off; the second clock signal terminal ECB is low, and the fourth transistor T4 and the sixth transistor T6 are on; the potential at ECB is lower than the potential at point N2, so the fifth transistor T5 is on; the potential at N4 is the low level of ECB, so the eighth transistor T8 is on; the potential at N1 is VGH; the seventh transistor T7 is off; VGH is greater than VGL, so the tenth transistor T10 is off. Capacitor C1 begins to charge; after capacitor C1 is charged, the ninth transistor T9 is on, and the signal output terminal EOUT outputs VGH; see [link to relevant documentation]. Figure 15 and Figure 16 , Figure 15 For based on Figure 10 The diagram shown is a schematic of the gate drive circuit in the third stage. Figure 16 For based on Figure 10 The signal timing diagram of the gate drive circuit in the third stage is shown. In the third stage, the control signal terminal ESTV is low, and the third transistor T3 is turned on; the second clock signal terminal ECB is high, and T4 and T6 are turned off; due to the effect of capacitor C1, point N4 is at a low potential, and T8 and T9 are turned on; point N1 is VGH, and T7 and T10 are turned off.

[0152] In some embodiments, the gate drive circuit can repeat the second stage multiple times between the second and third stages to ensure voltage stability at multiple nodes, thereby ensuring stable output at the output terminal. For example, if the high-level time of STV is greater than or equal to 3 to 5 cycles of the first clock signal ECB or ECK, the potentials of node N1 (controlling T10) and node N4 (controlling T9) can be made more stable.

[0153] See Figure 17 and Figure 18 , Figure 17 For based on Figure 10 The diagram shown is a schematic of the gate drive circuit in the fourth stage. Figure 18 For based on Figure 10 The diagram shows the signal timing of the gate drive circuit in the fourth stage. In the fourth stage, the control signal terminal ESTV outputs a low-level signal; the first clock signal terminal ECK outputs a high-level signal; and the second clock signal terminal ECB outputs a low-level signal.

[0154] The first voltage input terminal VGL outputs a second-level signal, which is for the above... Figure 9 Supplementary explanation of the timing of the first voltage input signal in the driving method of the gate drive circuit shown. In the fourth stage, the control signal terminal ESTV is low, and the third transistor T3 is turned on; the first clock signal terminal ECK is high, T1 is turned off; the second clock signal terminal ECB is low, T4 is turned on; the potential of N2 is high, T5 is turned off, and T2 is turned on; when T2 is turned on, point N1 is VGL2, T7 is turned on, and T10 is turned on; when T7 is turned on, point N4 is VGH, capacitor C1 starts charging, and T9 is turned off.

[0155] In this embodiment, by lowering the potential of point N1 through VGL2, the step at which the tenth transistor outputs VGL is reduced, thereby improving the stability of the gate drive circuit output signal. In the prior art, a capacitor is used to lower the gate potential of the buffer TFT, which can lead to bias voltage. However, in this embodiment, lowering the potential of point N1 through VGL2 reduces the occurrence of bias voltage, thereby protecting the gate potential of the buffer TFT and improving the driving capability of the gate drive circuit.

[0156] See Figure 19a and Figure 19bThis paper compares the threshold voltage VTH process margin of the gate drive circuit provided in this application with that of current GOA circuits. Current GOA circuits typically have a process range of -2V to 2V (where the rise time Tr is 4.4µs, which is too long and does not meet display requirements). The gate drive circuit provided in this application has a process range of -2V to 3V. Compared to current GOA circuits, the gate drive circuit provided in this application has a larger process margin while maintaining comparable driving capability. Here, Tf is the fall time, Tr is the rise time, and Tf and Tr < 2µs meet display requirements.

[0157] This application also provides a display substrate, see [link to relevant documentation] Figure 20 The display substrate includes the gate driving circuit 1 described in any of the above embodiments.

[0158] This application also provides a display device, see [link to relevant documentation] Figure 21 The display device includes a display substrate as described in the above embodiments.

[0159] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0160] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0161] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application are included within the scope of protection of this application.

Claims

1. A gate driving circuit, characterized in that, The circuit includes: A second input sub-circuit, a gate control sub-circuit, a first input sub-circuit, an output control sub-circuit, a first output sub-circuit, and a second output sub-circuit; the second input sub-circuit includes a first transistor; the first input sub-circuit includes a third transistor and a fourth transistor; the output control sub-circuit includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; the first output sub-circuit includes a ninth transistor and a first capacitor; the second output sub-circuit includes a tenth transistor; and the gate control sub-circuit includes a second transistor. The control terminal of the first transistor is connected to the first clock signal terminal; the first terminal of the first transistor is connected to the second voltage input terminal and the first terminal of the second transistor; the second terminal of the first transistor is connected to the control terminal of the fifth transistor, the control terminal of the second transistor, and the first terminal of the third transistor; the second terminal of the second transistor is connected to the control terminal of the seventh transistor, the second terminal of the eighth transistor, and the control terminal of the tenth transistor. The control terminal of the third transistor is connected to the control signal terminal, and the second terminal of the third transistor is connected to the first terminal of the fourth transistor; the control terminal of the fourth transistor is connected to the second clock signal terminal, and the second terminal of the fourth transistor is connected to the third voltage input terminal. The first terminal of the fifth transistor is connected to the second clock signal terminal, and the second terminal of the fifth transistor is connected to the first terminal of the sixth transistor; The control terminal of the sixth transistor is connected to the second clock signal terminal, and the second terminal of the sixth transistor is connected to the first terminal of the seventh transistor, the control terminal of the eighth transistor, the control terminal of the ninth transistor, and the second terminal of the first capacitor, respectively. The second terminal of the seventh transistor is connected to the third voltage input terminal; or the second terminal of the seventh transistor is connected to the fourth voltage input terminal; The first terminal of the eighth transistor is connected to the third voltage input terminal, or the first terminal of the eighth transistor is connected to the fourth voltage input terminal; The first terminal of the ninth transistor is connected to the first terminal of the first capacitor and the third voltage input terminal, respectively, and the second terminal of the ninth transistor is connected to the signal output terminal. The first terminal of the tenth transistor is connected to the signal output terminal, and the second terminal of the tenth transistor is connected to the first voltage input terminal; The second voltage is less than the first voltage; The second input sub-circuit is used to control the on / off state of the gate control sub-circuit and to control the input of the second voltage of the output control sub-circuit. The first input sub-circuit is used to control the input of the third voltage of the output control sub-circuit; The gate control sub-circuit is used to control the on / off state of the second output sub-circuit; The output control sub-circuit is used to control the voltage at the control terminals of the first output sub-circuit and the second output sub-circuit; The first output sub-circuit is used to output a first signal when it is turned on; The second output sub-circuit is used to output a second signal when it is turned on.

2. The circuit according to claim 1, characterized in that, The second output sub-circuit also includes a second capacitor; the first terminal of the second capacitor is connected to the first terminal of the tenth transistor, and the second terminal of the second capacitor is connected to the control terminal of the tenth transistor.

3. The circuit according to claim 2, characterized in that, The output control sub-circuit further includes an eleventh transistor, the control terminal of which is connected to the first voltage input terminal, the first terminal of which is connected to the second terminal of the first transistor and the first terminal of the third transistor, and the second terminal of which is connected to the control terminal of the fifth transistor.

4. The circuit according to claim 1, characterized in that, The second transistor is an oxide transistor, and the remaining transistors are low-temperature polysilicon transistors.

5. The circuit according to claim 1, characterized in that, The second signal is either a clock signal or a first voltage.

6. A driving method for a gate driving circuit, characterized in that, The method for driving the gate driving circuit according to any one of claims 1-5 includes: In the first stage, the control signal terminal outputs a first-level signal; the first clock signal terminal outputs a second-level signal; the second clock signal terminal outputs a first-level signal; and the first voltage input terminal outputs a second-level signal. In the second stage, the control signal terminal outputs a first-level signal; the first clock signal terminal outputs a first-level signal; the second clock signal terminal outputs a second-level signal; and the first voltage input terminal outputs a second-level signal. In the third stage, the control signal terminal outputs a second-level signal; the first clock signal terminal outputs a second-level signal; the second clock signal terminal outputs a first-level signal; and the first voltage input terminal outputs a second-level signal. In the fourth stage, the control signal terminal outputs a second-level signal; the first clock signal terminal outputs a first-level signal; the second clock signal terminal outputs a second-level signal; and the first voltage input terminal outputs a second-level signal. The first level signal and the second level signal are signals with opposite high and low levels.

7. The method according to claim 6, characterized in that, The second transistor is an N-type transistor, and the remaining transistors are P-type transistors; The first level signal is high level, and the second level signal is low level.

8. A display substrate, characterized in that, The display substrate includes the gate driving circuit described in any one of claims 1-5.

Images