Flash memory and method of programming voltage control thereof

Abstract

The application discloses a flash memory, each memory cell in the same column is connected in parallel between two adjacent bit lines. When programming operation is performed on a selected memory bit, three stages are set as follows: a first programming stage is used to implement first programming, a bit line programming voltage of a bit line close to the selected memory bit is set as a first positive voltage; a second verifying stage is used to perform verifying; and a third programming stage is used to implement second programming, the bit line programming voltage is set as a second positive voltage. The third programming stage is performed when a verifying result is abnormal, the first positive voltage is less than the second positive voltage; the first positive voltage meets programming needs of a first part of memory cells in an array structure, and the second positive voltage meets programming needs of a second part of memory cells. The number of the second part is less than the number of the first part. The application further discloses a programming voltage control method of the flash memory. The application can reduce or eliminate programming interference while maintaining programming efficiency.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuits, and in particular to a flash memory. This invention also relates to a method for controlling the programming voltage of flash memory. Background Technology

[0002] like Figure 1 The diagram shown is a schematic diagram of the circuit structure of a conventional flash memory storage cell 101; as shown... Figure 2 The diagram shown is a cross-sectional view of a conventional flash memory storage cell 101; as shown... Figure 3 The diagram shown is an array structure diagram of an existing flash memory; the existing flash memory includes multiple storage cells 101, the multiple storage cells 101 form an array cell 301, and the multiple array cells 301 are arranged to form an array structure of the flash memory.

[0003] Each of the aforementioned storage cells 101 employs a discrete-gate floating-gate device.

[0004] like Figure 2 As shown, the split-gate floating gate device includes: a symmetrical first source / drain region 205a and a second source / drain region 206, a plurality of split first gate structures with floating gates 104 located between the first source / drain region 205a and the second source / drain region 205b, and a second gate structure 103 located between the first gate structures; the first gate structure has a control gate 105 located on top of the floating gates 104.

[0005] The split-gate floating gate device is a dual split-gate floating gate device, and the number of the first gate structures is two, which are denoted by 102a and 102b respectively.

[0006] The separated gate floating gate device is an N-type device, and both the first source / drain region 205a and the second source / drain region 205b are composed of N+ regions.

[0007] The P-type doped channel region is located between the first source / drain region 205a and the second source / drain region 205b and is covered by each of the first gate structure and the second gate structure 103. The first source / drain region 205a and the second source / drain region 205b are both formed on the P-type semiconductor substrate 201 and are self-aligned with the outer surfaces of the corresponding two first gate structures. The channel regions are formed by the P-type semiconductor substrate 201 between the first source / drain region 205a and the second source / drain region 205b or by further doping on the P-type semiconductor substrate 201.

[0008] The second source / drain region 205b of the memory cell 101 is connected to the second source / drain electrode, which is connected to the bit line BL1.

[0009] The first source-drain region 205a of the memory cell 101 is connected to the first source-drain electrode, which is connected to the bit line BL0.

[0010] Each of the first gate structures is formed by stacking the tunneling dielectric layer 202, the floating gate 104, the control gate dielectric layer 203, and the control gate 105.

[0011] Each of the second gate structures 103 is formed by stacking a word line gate dielectric layer 204 and a word line gate 106.

[0012] The control gate 105 is connected to the corresponding control gate line, and the word line gate 106 is connected to the word line WL. Figure 1 In the above, the memory cell 101 includes two first gate structures, so the control gate line also includes two lines, denoted by CG0 and CG1 respectively. The control gate 105 of the first gate structure 102a is connected to the control gate line CG0, and the control gate 105 of the first gate structure 102b is connected to the control gate line CG1.

[0013] When programming selected storage bits of the storage unit 101, in order to... Figure 2 Taking the storage bit 'a' corresponding to the floating gate 104 in the first gate structure 102a as an example, where the storage bit is selected, the applied voltages are shown in Table 1, including: The control gate line CG1 is connected to 6V and is used to open, i.e., conduct, the region segment of the channel controlled by the first gate structure 102b. The word line WL is connected to 1.5V and is used to open the region segment of the channel region controlled by the second gate structure 103; Bit line BL1 is connected to the programming current Idp.

[0014] The control gate line CG0 is connected to a 9V high voltage, and the bit line BL0 is connected to a 4.5V high voltage. In this way, after the programming current passes through the channel region controlled by the first gate structure 102b and the second gate structure 103 and reaches the bottom of the first gate structure 102a, the source-side hot electron injection programming can be realized because both the control gate line CG0 and the bit line BL1 are high voltage.

[0015] Table 1

[0016] like Figure 3 As shown, in the array structure, each of the storage cells 101 is arranged in rows and columns.

[0017] The first source-drain region 205a and the second source-drain region 205b of each of the memory cells 101 are connected to the corresponding bit lines, and each bit line is shared by two adjacent columns of memory cells 101.

[0018] Each of the memory cells 101 in the same column is connected in parallel between two adjacent bit lines. Figure 3 The image shows four adjacent memory cells 101 in the same column. The four memory cells are labeled 101a, 101b, 101c and 101d respectively. It can be seen that the first source-drain region 205a of each memory cell 101 in the same column is connected to the first source-drain region 205a of the adjacent memory cell 101 and connected to the bit line BL0. The second source-drain region 205b of each memory cell 101 in the same column is connected to the second source-drain region 205b of the adjacent memory cell 101 and connected to the bit line BL1.

[0019] Let the selected memory cell be memory cell 101a, and the selected memory bit be the memory bit 'a' in memory cell 101a that is close to bit line BL0. Then, the voltage applied when programming the selected memory bit 'a' is as described above, i.e., the voltage is applied according to Table 1.

[0020] However, by Figure 3 As shown, bit line BL0 requires a bit line programming voltage of 4.5V. However, bit line BL0 is not only connected to the first source-drain region 205a of the selected memory cell 101a, but also to the first source-drain region 205a of other memory cells 101 in the same column. Figure 3 The first source-drain region 205a of memory cells 101b, 101c and 101d are all connected to bit line BL0.

[0021] When bit line BL0 is high, it will cause programming interference to the memory bits of each memory cell 101 in the same column that are close to bit line BL0, such as... Figure 3 The storage bits 'b', 'c', and 'd' in the memory will be affected by the programming interference of the bit line BL0.

[0022] To reduce programming interference caused by bit line BL0, the voltage of bit line BL0 needs to be reduced. However, reducing the voltage of bit line BL0 will reduce programming efficiency and make the selected memory bit 'a' more susceptible to weak programming.

[0023] Therefore, in existing programming methods, the voltage of bit line BL0 needs to balance programming efficiency and programming interference. However, the voltage requirements of bit line BL0 for improving programming efficiency and reducing programming interference are contradictory, making it difficult to set the voltage of bit line BL0. Summary of the Invention

[0024] The technical problem to be solved by this invention is to provide a flash memory that can reduce or eliminate programming interference while maintaining programming efficiency. To this end, this invention also provides a method for controlling the programming voltage of a flash memory.

[0025] Therefore, the flash memory provided by the present invention includes a plurality of storage cells, and the plurality of storage cells are arranged to form an array structure of the flash memory, wherein the storage cells are arranged in rows and columns in the array structure.

[0026] Each of the memory cells in the same column is connected in parallel between two adjacent bit lines.

[0027] For a selected memory cell, the two bit lines connected to the selected memory cell are the first bit line and the second bit line, respectively. The first bit line is the bit line located on the side of the selected memory bit closer to the selected memory cell.

[0028] When programming a selected memory bit of the selected memory cell, the first bit line is connected to the bit line programming voltage. The programming operation has the following three stages: The first programming stage is used to perform the first programming of the selected memory bit, wherein the bit line programming voltage in the first programming stage is set to a first positive voltage.

[0029] The second verification stage is used to verify the state of the selected memory bit, and the bit line programming voltage is set to 0V.

[0030] The third programming stage is used to perform a second programming of the selected memory bit, wherein the bit line programming voltage is set to a second positive voltage in the third programming stage.

[0031] In the second verification stage, if the verification result is normal, the third programming stage is omitted; if the verification result is abnormal, the third programming stage is performed.

[0032] In the array structure, the bit line programming voltage required for normal programming of each memory cell has a deviation.

[0033] The first positive voltage is less than the second positive voltage. The first positive voltage satisfies the programming requirements of the memory cells in the first part of the array structure. Programming interference is reduced by lowering the first positive voltage.

[0034] The memory cells that cannot be programmed normally under the first positive voltage constitute the memory cells of the second part. The second positive voltage satisfies the programming requirements of the memory cells of the second part. The number of the second part is less than the number of the first part. By reducing the number of the second part, the cumulative effect of programming interference of the second positive voltage is reduced.

[0035] A further improvement is that each of the aforementioned memory cells employs a discrete-gate floating-gate device.

[0036] The split-gate floating gate device includes: a first source-drain region and a second source-drain region symmetrically arranged, a plurality of split first gate structures with floating gates located between the first source-drain region and the second source-drain region, and a second gate structure located between the first gate structures; the first gate structure has a control gate located on top of the floating gate.

[0037] The first source-drain region and the second source-drain region of each of the memory cells are connected to the corresponding bit lines.

[0038] The first source-drain regions of each of the memory cells in the same column and the first source-drain regions of adjacent memory cells are connected together, and the second source-drain regions of each of the memory cells in the same column and the second source-drain regions of adjacent memory cells are connected together.

[0039] A further improvement is that the split-gate floating gate device is a dual split-gate floating gate device, and the number of the first gate structures is two.

[0040] A further improvement is that the separated gate floating gate device is an N-type device, and both the first source / drain region and the second source / drain region are composed of N+ regions.

[0041] The P-type doped channel region is located between the first source / drain region and the second source / drain region and is covered by each of the first gate structure and the second gate structure, each of the first gate structure and the second gate structure controlling the region segment of the covered channel region respectively.

[0042] A further improvement is that, in the array structure, the second gate structures of each memory cell in the same row are all connected to the word line of the same row, and the control gates of the first gate structures of each memory cell in the same row are all connected to the control gate line of the same row.

[0043] When programming the selected memory bit of the selected memory cell, the word line corresponding to the selected memory cell is connected to the word line programming voltage, and the control gate line corresponding to the selected memory bit in the selected memory cell is connected to the control gate programming voltage.

[0044] In the programming operation, the word line programming voltage and the control gate programming voltage are set as follows: In the first programming stage, the control gate programming voltage is set to a third positive voltage, and the word line programming voltage is set to a fourth positive voltage.

[0045] In the third programming stage, the control gate programming voltage is set to the fifth positive voltage, and the word line programming voltage is set to the sixth positive voltage.

[0046] The third positive voltage is greater than the fifth positive voltage and the fourth positive voltage is less than the sixth positive voltage, so as to improve the programming efficiency in the first programming stage.

[0047] A further improvement is that, in the second verification stage, the control gate programming voltage is set to 0V, the word line programming voltage is connected to a sixth positive voltage, and the sixth positive voltage is greater than the fifth positive voltage.

[0048] A further improvement is that each of the first gate structures is formed by stacking a tunneling dielectric layer, the floating gate, the control gate dielectric layer, and the control gate.

[0049] Each of the second gate structures is formed by stacking a word line gate dielectric layer and a word line gate.

[0050] A further improvement is that the three stages of the programming operation are controlled by a first programming signal, which includes two pulses. The first pulse defines the first programming stage, the second pulse defines the third programming stage, and the interval between the first pulse and the second pulse defines the second verification stage.

[0051] A further improvement is that the proportion of the storage units in the first part is more than 90%.

[0052] To solve the above-mentioned technical problems, the present invention provides a flash memory programming voltage control method in which the flash memory includes multiple storage cells, and the multiple storage cells are arranged to form an array structure of the flash memory, wherein the storage cells are arranged in rows and columns in the array structure.

[0053] Each of the memory cells in the same column is connected in parallel between two adjacent bit lines.

[0054] For a selected memory cell, the two bit lines connected to the selected memory cell are the first bit line and the second bit line, respectively. The first bit line is the bit line located on the side of the selected memory bit closer to the selected memory cell.

[0055] When programming a selected memory bit of the selected memory cell, the first bit line is connected to the bit line programming voltage.

[0056] In the programming operation, the programming voltage control method includes the following steps: A first programming stage is set up, and the selected memory bit is programmed for the first time in the first programming stage, wherein the bit line programming voltage in the first programming stage is set to a first positive voltage.

[0057] A second verification phase is set up, and the state of the selected memory bit is verified in the second verification phase, with the bit line programming voltage set to 0V.

[0058] A third programming stage is set up, and the selected memory bit is programmed a second time in the third programming stage, wherein the bit line programming voltage is set to a second positive voltage.

[0059] In the second verification stage, if the verification result is normal, the third programming stage is omitted; if the verification result is abnormal, the third programming stage is performed.

[0060] In the array structure, the bit line programming voltage required for normal programming of each memory cell has a deviation.

[0061] The first positive voltage is less than the second positive voltage. The first positive voltage satisfies the programming requirements of the memory cells in the first part of the array structure. Programming interference is reduced by lowering the first positive voltage.

[0062] The memory cells that cannot be programmed normally under the first positive voltage constitute the memory cells of the second part. The second positive voltage satisfies the programming requirements of the memory cells of the second part. The number of the second part is less than the number of the first part. By reducing the number of the second part, the cumulative effect of programming interference of the second positive voltage is reduced.

[0063] A further improvement is that each of the aforementioned memory cells employs a discrete-gate floating-gate device.

[0064] The split-gate floating gate device includes: a first source-drain region and a second source-drain region symmetrically arranged, a plurality of split first gate structures with floating gates located between the first source-drain region and the second source-drain region, and a second gate structure located between the first gate structures; the first gate structure has a control gate located on top of the floating gate.

[0065] The first source-drain region and the second source-drain region of each of the memory cells are connected to the corresponding bit lines.

[0066] The first source-drain regions of each of the memory cells in the same column and the first source-drain regions of adjacent memory cells are connected together, and the second source-drain regions of each of the memory cells in the same column and the second source-drain regions of adjacent memory cells are connected together.

[0067] A further improvement is that the split-gate floating gate device is a dual split-gate floating gate device, and the number of the first gate structures is two.

[0068] A further improvement is that the separated gate floating gate device is an N-type device, and both the first source / drain region and the second source / drain region are composed of N+ regions.

[0069] The P-type doped channel region is located between the first source / drain region and the second source / drain region and is covered by each of the first gate structure and the second gate structure, each of the first gate structure and the second gate structure controlling the region segment of the covered channel region respectively.

[0070] A further improvement is that, in the array structure, the second gate structures of each memory cell in the same row are all connected to the word lines of the same row, and the control gates of the first gate structures of each memory cell in the same row are all connected to the control gate lines of the same row.

[0071] When programming the selected memory bit of the selected memory cell, the word line corresponding to the selected memory cell is connected to the word line programming voltage, and the control gate line corresponding to the selected memory bit in the selected memory cell is connected to the control gate programming voltage.

[0072] The programming voltage control method further includes setting the word line programming voltage and the control gate programming voltage, including: In the first programming stage, the control gate programming voltage is set to a third positive voltage, and the word line programming voltage is set to a fourth positive voltage.

[0073] In the third programming stage, the control gate programming voltage is set to the fifth positive voltage, and the word line programming voltage is set to the sixth positive voltage.

[0074] The third positive voltage is greater than the fifth positive voltage and the fourth positive voltage is less than the sixth positive voltage, so as to improve the programming efficiency in the first programming stage.

[0075] A further improvement is that, in the second verification stage, the control gate programming voltage is set to 0V, the word line programming voltage is connected to a sixth positive voltage, and the sixth positive voltage is greater than the fifth positive voltage.

[0076] A further improvement is that each of the first gate structures is formed by stacking a tunneling dielectric layer, the floating gate, the control gate dielectric layer, and the control gate.

[0077] Each of the second gate structures is formed by stacking a word line gate dielectric layer and a word line gate.

[0078] A further improvement is that the three stages of the programming operation are controlled by a first programming signal, which includes two pulses. The first pulse defines the first programming stage, the second pulse defines the third programming stage, and the interval between the first pulse and the second pulse defines the second verification stage.

[0079] A further improvement is that the proportion of the storage units in the first part is more than 90%.

[0080] To address the contradiction in existing flash memory programming operations where setting the bit line programming voltage too high causes programming interference (interference with non-selected memory cells in the same column), while setting it too low reduces programming efficiency, this invention sets up three stages in the programming operation. In the first programming stage, the bit line programming voltage is set to a relatively small first positive voltage. This smaller first positive voltage can achieve normal programming of most of the memory cells in the flash memory, i.e., the first part. Therefore, programming interference can be reduced by lowering the first positive voltage while maintaining programming efficiency. The second verification stage is used to verify the first programming result of the first programming stage. If the verification result is normal, the subsequent third programming stage is not required, meaning that most memory cells do not need to undergo the third programming stage. When the first programming result is abnormal, the third programming stage is performed. In the third programming stage, the value of the second positive voltage is increased to achieve normal programming of the remaining small part of the memory cells, i.e., the second part. Therefore, programming efficiency can be guaranteed by setting the second positive voltage. However, since the number of memory cells that need to be programmed a second time is small, the cumulative effect of programming interference caused by the second positive voltage is reduced, ultimately reducing programming interference as well. Therefore, this invention can reduce or eliminate programming interference while maintaining programming efficiency. Attached Figure Description

[0081] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments: Figure 1 This is a schematic diagram of the circuit structure of an existing flash memory storage cell; Figure 2 This is a cross-sectional structural diagram of an existing flash memory storage cell; Figure 3 This is a diagram of the existing flash memory array structure; Figure 4 This is a curve showing the change of bit line programming voltage in the three stages of the programming operation of the flash memory in an embodiment of the present invention. Detailed Implementation

[0082] Please also refer to the structure of the flash memory storage cell 101 in this embodiment of the invention. Figure 1 and Figure 2 As shown, the array structure of the flash memory in this embodiment of the invention is also referenced. Figure 3 As shown, the flash memory in this embodiment of the invention includes a plurality of storage units 101.

[0083] In this embodiment of the invention, each of the memory cells 101 employs a discrete-gate floating-gate device.

[0084] like Figure 2As shown, the split-gate floating gate device includes: a symmetrical first source / drain region 205a and a second source / drain region 206, a plurality of split first gate structures with floating gates 104 located between the first source / drain region 205a and the second source / drain region 205b, and a second gate structure 103 located between the first gate structures; the first gate structure has a control gate 105 located on top of the floating gates 104.

[0085] The split-gate floating gate device is a dual split-gate floating gate device, and the number of the first gate structures is two, which are represented by the markings 102a and 102b respectively.

[0086] In some embodiments, the separated gate floating gate device is an N-type device, and both the first source / drain region 205a and the second source / drain region 205b are composed of N+ regions.

[0087] The P-type doped channel region is located between the first source / drain region 205a and the second source / drain region 205b and is covered by each of the first gate structure and the second gate structure 103. Each of the first gate structure and the second gate structure 103 controls the region segment of the covered channel region. The first source / drain region 205a and the second source / drain region 205b are both formed on the P-type semiconductor substrate 201 and are self-aligned with the outer surfaces of the corresponding two first gate structures. The channel regions are formed by the P-type semiconductor substrate 201 between the first source / drain region 205a and the second source / drain region 205b or by further doping on the P-type semiconductor substrate 201.

[0088] The first source-drain region 205a of the memory cell 101 is connected to the first source-drain electrode, which is connected to the bit line BL0.

[0089] The second source / drain region 205b of the memory cell 101 is connected to the second source / drain electrode, which is connected to the bit line BL1.

[0090] Each of the first gate structures is formed by stacking the tunneling dielectric layer 202, the floating gate 104, the control gate dielectric layer 203, and the control gate 105.

[0091] Each of the second gate structures 103 is formed by stacking a word line gate dielectric layer 204 and a word line gate 106.

[0092] The control gate 105 is connected to the corresponding control gate line, and the word line gate 106 is connected to the word line WL. Figure 1In the memory cell 101, there are two first gate structures, so there are also two control gate lines, which are represented by CG0 and CG1 respectively. The control gate 105 of the first gate structure 102a is connected to the control gate line CG0, and the control gate 105 of the first gate structure 102b is connected to the control gate line CG1.

[0093] like Figure 3 As shown, a flash memory array structure is formed by arranging multiple memory cells 101, wherein the memory cells 101 are arranged in rows and columns. The first source-drain region 205a and the second source-drain region 205b of each memory cell 101 are connected to corresponding bit lines, and each bit line is shared by two adjacent columns of memory cells 101.

[0094] Each of the memory cells 101 in the same column is connected in parallel between two adjacent bit lines. Figure 3 The image shows four adjacent memory cells 101 in the same column. The four memory cells are labeled 101a, 101b, 101c and 101d respectively. It can be seen that the first source-drain region 205a of each memory cell 101 in the same column is connected to the first source-drain region 205a of the adjacent memory cell 101 and connected to the bit line BL0. The second source-drain region 205b of each memory cell 101 in the same column is connected to the second source-drain region 205b of the adjacent memory cell 101 and connected to the bit line BL1.

[0095] In the array structure, the second gate structure 103 of each memory cell 101 in the same row is connected to the word line WL of the same row, and the control gate of the first gate structure of each memory cell 101 in the same row is connected to the control gate line of the same row. Figure 3 In the row structure of the memory cells 101 in the same row, the control gate line includes two lines, denoted by CG0 and CG1 respectively. The control gate 105 of the first gate structure 102a of each memory cell 101 in the same row is connected to the control gate line CG0, and the control gate 105 of the first gate structure 102b in the same row is connected to the control gate line CG1.

[0096] For a selected memory cell 101, the two bit lines connected to the selected memory cell 101 are a first bit line and a second bit line, respectively. The first bit line is the bit line located on the side closest to the selected memory bit of the selected memory cell 101. For example, when the selected memory cell 101 is... Figure 3When the storage cell 101a and the selected storage bit are storage bits 'a', the first bit line is bit line BL0 and the second bit line is bit line BL1. In the following description, the storage cell 101a is used as the selected storage cell and the storage bit 'a' is used as the selected storage bit 'a' as an example. The control gate line corresponding to the selected storage bit 'a' is the control gate line corresponding to the marker CG0.

[0097] When programming the selected memory bit 'a' of the selected memory cell 101a, the first bit line BL0 is connected to the bit line programming voltage.

[0098] In this embodiment of the invention, when programming the selected memory bit 'a' of the selected memory cell 101a, the word line WL corresponding to the selected memory cell 101a is connected to the word line programming voltage, and the control gate line CG0 corresponding to the selected memory bit 'a' in the selected memory cell 101a is connected to the control gate programming voltage.

[0099] The programming operation consists of the following three stages: The first programming stage is used to perform the first programming of the selected memory bit 'a', and the bit line programming voltage in the first programming stage is set to a first positive voltage.

[0100] The second verification stage is used to verify the state of the selected storage bit 'a', and the bit line programming voltage is set to 0V.

[0101] The third programming stage is used to perform a second programming of the selected memory bit 'a', in which the bit line programming voltage is set to a second positive voltage.

[0102] In the second verification stage, if the verification result is normal, the third programming stage is omitted; if the verification result is abnormal, the third programming stage is performed.

[0103] In the array structure, the bit line programming voltage required for normal programming of each of the memory cells 101 has a deviation.

[0104] The first positive voltage is less than the second positive voltage. The first positive voltage satisfies the programming requirements of the memory cell 101 in the first part of the array structure. Programming interference is reduced by lowering the first positive voltage.

[0105] The memory cells 101 that cannot be programmed normally by the first positive voltage constitute the memory cells 101 of the second part. The second positive voltage satisfies the programming needs of the memory cells 101 of the second part. The number of the second part is less than the number of the first part. By reducing the number of the second part, the cumulative effect of programming interference of the second positive voltage is reduced.

[0106] like Figure 4 The figure shows the bit line programming voltage variation curves in the three stages of the programming operation of the flash memory according to an embodiment of the present invention. In this embodiment, the three stages of the programming operation are controlled by the first programming signal Prog2. Figure 4 The curve of the first programming signal Prog2 is also represented by Prog2. It can be seen that the first programming signal Prog2 includes two pulses, marked by '1' and '2' respectively. The first pulse '1' defines the first programming stage, the second pulse '2' defines the third programming stage, and the interval between the first pulse '1' and the second pulse '2' defines the second verification stage.

[0107] Figure 4 In this context, the bit line programming voltage is the voltage of the first bit line BL0, therefore the curve of the bit line programming voltage is still represented by BL0. The bit line programming voltage rises to a first positive voltage during the time period defined by the first pulse '1', drops to 0V during the time period defined by the interval between the first pulse '1' and the second pulse '2', and rises to a second positive voltage during the time period defined by the second pulse '2'. Therefore, the first programming signal Prog2 can control the three stages of the programming operation.

[0108] In some embodiments, the control signal includes a programming signal Prog and a write enable signal We. During the programming operation, the programming signal Prog switches to a high level; the write enable signal We switches to an enable signal. Figure 4 In the above, the write enable signal We is also enabled when it is at a high level.

[0109] In some embodiments, the proportion of the storage cells 101 in the first portion is more than 90%. For example, if the proportion of the storage cells 101 in the first portion is 95%, then 95% of the storage cells 101 in the flash memory only need to undergo the first programming once, without needing the second programming; while only 5% of the storage cells 101 need to undergo the second programming. Therefore, the first programming is weak-disturbance programming, which is a dispersed program, capable of programming most of the storage cells 101; the second programming is strong-disturbance programming, which is a convergence program, ultimately capable of programming all the storage cells 101. Since the total number of times the second programming is reduced, the programming interference caused by the second programming is also reduced, ultimately reducing programming interference as well. Figure 4 In this context, the first programming step is also represented by Firsttry, the verification in the second verification stage is also represented by Verify, and the second programming step is also represented by Secondtry.

[0110] In this embodiment of the invention, during the programming operation, the word line programming voltage and the control gate programming voltage are set as follows: In the first programming stage, the control gate programming voltage is set to a third positive voltage, and the word line programming voltage is set to a fourth positive voltage.

[0111] In the third programming stage, the control gate programming voltage is set to the fifth positive voltage, and the word line programming voltage is set to the sixth positive voltage.

[0112] The third positive voltage is greater than the fifth positive voltage and the fourth positive voltage is less than the sixth positive voltage, so as to improve the programming efficiency in the first programming stage.

[0113] In the second verification stage, the control gate programming voltage is set to 0V, the word line programming voltage is connected to the sixth positive voltage, and the sixth positive voltage is greater than the fifth positive voltage.

[0114] Figure 4 The curves showing the changes in the word line programming voltage and the control gate programming voltage are not displayed, but by referring to curve BL0, it can be seen that the word line programming voltage and the control gate programming voltage will also undergo three stages of change, just like BL0, except that the corresponding magnitudes are different.

[0115] In some specific embodiments, the programming operations of the embodiments of the present invention can be implemented using the parameters in Table 2 below.

[0116] Table 2

[0117] In Table 2, BL0 represents the bit line programming voltage, CG0 represents the control gate programming voltage, and WL represents the word line programming voltage.

[0118] As can be seen from Table 1, in this embodiment of the invention, the voltage of BL0 will decrease in the First try, which can reduce programming interference; CG0 will increase and WL will decrease, which will improve programming efficiency to compensate for the decrease in programming efficiency caused by the reduction of BL0.

[0119] In this embodiment of the invention, it is also necessary to specify the control gate line corresponding to the non-selected storage bit, such as... Figure 3 A voltage is applied to the control gate line corresponding to CG1, and a programming current Idp needs to be applied to the second bit line, such as bit line BL1. If the control gate line voltage of the unselected memory bit is applied in the First try and Second try to turn on the region segment of the channel controlled by the first gate structure corresponding to the unselected memory bit, the voltage of CG1 can also be 6V as described in Table 1.

[0120] To address the contradiction in existing flash memory programming operations where setting the bit line programming voltage too high causes programming interference (interference with non-selected memory cells 101 in the same column), while setting it too low reduces programming efficiency, this embodiment of the invention sets three stages in the programming operation. In the first programming stage, the bit line programming voltage is set to a relatively small first positive voltage. This relatively small first positive voltage can achieve normal programming of most of the memory cells 101 in the flash memory, i.e., the first part. Therefore, programming interference can be reduced by lowering the first positive voltage while maintaining programming efficiency. The second verification stage is used to verify the first programming result of the first programming stage. If the verification result is normal, the subsequent third programming stage is not required, meaning that most of the memory cells 101 do not need to undergo the third programming stage. If the first programming result is abnormal, a third programming stage is performed. In the third programming stage, increasing the value of the second positive voltage enables normal programming of the remaining small portion of the memory cells 101, i.e., the second part. Therefore, programming efficiency can be guaranteed by setting the second positive voltage. However, since the number of memory cells 101 requiring a second programming is small, the cumulative effect of programming interference caused by the second positive voltage is reduced, ultimately reducing programming interference. Therefore, this embodiment of the invention can reduce or eliminate programming interference while maintaining programming efficiency.

[0121] The flash memory programming voltage control method of this invention embodiment: In the method of this embodiment of the invention, please also refer to the structure of the flash memory storage cell 101. Figure 1 and Figure 2 As shown, please also refer to the array structure of the flash memory. Figure 3 As shown, the flash memory includes multiple storage units 101.

[0122] In the method of this embodiment of the invention, each of the memory cells 101 employs a discrete gate floating gate device.

[0123] like Figure 2 As shown, the split-gate floating gate device includes: a symmetrical first source / drain region 205a and a second source / drain region 206, a plurality of split first gate structures with floating gates 104 located between the first source / drain region 205a and the second source / drain region 205b, and a second gate structure 103 located between the first gate structures; the first gate structure has a control gate 105 located on top of the floating gates 104.

[0124] The split-gate floating gate device is a dual split-gate floating gate device, and the number of the first gate structures is two, which are represented by the markings 102a and 102b respectively.

[0125] In some embodiments, the separated gate floating gate device is an N-type device, and both the first source / drain region 205a and the second source / drain region 205b are composed of N+ regions.

[0126] The P-type doped channel region is located between the first source / drain region 205a and the second source / drain region 205b and is covered by each of the first gate structure and the second gate structure 103. Each of the first gate structure and the second gate structure 103 controls the region segment of the covered channel region. The first source / drain region 205a and the second source / drain region 205b are both formed on the P-type semiconductor substrate 201 and are self-aligned with the outer surfaces of the corresponding two first gate structures. The channel regions are formed by the P-type semiconductor substrate 201 between the first source / drain region 205a and the second source / drain region 205b or by further doping on the P-type semiconductor substrate 201.

[0127] The first source-drain region 205a of the memory cell 101 is connected to the first source-drain electrode, which is connected to the bit line BL0.

[0128] The second source / drain region 205b of the memory cell 101 is connected to the second source / drain electrode, which is connected to the bit line BL1.

[0129] Each of the first gate structures is formed by stacking the tunneling dielectric layer 202, the floating gate 104, the control gate dielectric layer 203, and the control gate 105.

[0130] Each of the second gate structures 103 is formed by stacking a word line gate dielectric layer 204 and a word line gate 106.

[0131] The control gate 105 is connected to the corresponding control gate line, and the word line gate 106 is connected to the word line WL. Figure 1 In the above, the memory cell 101 includes two first gate structures, so the control gate line also includes two lines, denoted by CG0 and CG1 respectively. The control gate 105 of the first gate structure 102a is connected to the control gate line CG0, and the control gate 105 of the first gate structure 102b is connected to the control gate line CG1.

[0132] like Figure 3 As shown, a flash memory array structure is formed by arranging multiple memory cells 101, wherein the memory cells 101 are arranged in rows and columns. The first source-drain region 205a and the second source-drain region 205b of each memory cell 101 are connected to corresponding bit lines, and each bit line is shared by two adjacent columns of memory cells 101.

[0133] Each of the memory cells 101 in the same column is connected in parallel between two adjacent bit lines. Figure 3 The image shows four adjacent memory cells 101 in the same column. The four memory cells are labeled 101a, 101b, 101c and 101d respectively. It can be seen that the first source-drain region 205a of each memory cell 101 in the same column is connected to the first source-drain region 205a of the adjacent memory cell 101 and connected to the bit line BL0. The second source-drain region 205b of each memory cell 101 in the same column is connected to the second source-drain region 205b of the adjacent memory cell 101 and connected to the bit line BL1.

[0134] In the array structure, the second gate structure 103 of each memory cell 101 in the same row is connected to the word line WL of the same row, and the control gate of the first gate structure of each memory cell 101 in the same row is connected to the control gate line of the same row. Figure 3 In the row structure of the memory cells 101 in the same row, the control gate line includes two lines, denoted by CG0 and CG1 respectively. The control gate 105 of the first gate structure 102a of each memory cell 101 in the same row is connected to the control gate line CG0, and the control gate 105 of the first gate structure 102b in the same row is connected to the control gate line CG1.

[0135] For a selected memory cell 101, the two bit lines connected to the selected memory cell 101 are a first bit line and a second bit line, respectively. The first bit line is the bit line located on the side closest to the selected memory bit of the selected memory cell 101. For example, when the selected memory cell 101 is... Figure 3When the storage cell 101a and the selected storage bit are storage bits 'a', the first bit line is bit line BL0 and the second bit line is bit line BL1. In the following description, the storage cell 101a is used as the selected storage cell and the storage bit 'a' is used as the selected storage bit 'a' as an example. The control gate line corresponding to the selected storage bit 'a' is the control gate line corresponding to the marker CG0.

[0136] When programming the selected memory bit 'a' of the selected memory cell 101a, the first bit line BL0 is connected to the bit line programming voltage.

[0137] In the method of this embodiment of the invention, when programming the selected memory bit 'a' of the selected memory cell 101a, the word line WL corresponding to the selected memory cell 101a is connected to the word line programming voltage, and the control gate line CG0 corresponding to the selected memory bit 'a' in the selected memory cell 101a is connected to the control gate programming voltage.

[0138] In the programming operation, the programming voltage control method includes the following steps: A first programming stage is set up and the selected memory bit 'a' is programmed for the first time in the first programming stage, wherein the bit line programming voltage is set to a first positive voltage in the first programming stage.

[0139] A second verification phase is set up, and the state of the selected storage bit 'a' is verified in the second verification phase, with the bit line programming voltage set to 0V.

[0140] A third programming stage is set up, and the selected memory bit 'a' is programmed a second time in the third programming stage, wherein the bit line programming voltage is set to a second positive voltage.

[0141] In the second verification stage, if the verification result is normal, the third programming stage is omitted; if the verification result is abnormal, the third programming stage is performed.

[0142] In the array structure, the bit line programming voltage required for normal programming of each of the memory cells 101 has a deviation.

[0143] The first positive voltage is less than the second positive voltage. The first positive voltage satisfies the programming requirements of the memory cell 101 in the first part of the array structure. Programming interference is reduced by lowering the first positive voltage.

[0144] The memory cells 101 that cannot be programmed normally by the first positive voltage constitute the memory cells 101 of the second part. The second positive voltage satisfies the programming needs of the memory cells 101 of the second part. The number of the second part is less than the number of the first part. By reducing the number of the second part, the cumulative effect of programming interference of the second positive voltage is reduced.

[0145] like Figure 4 The figure shows the bit line programming voltage variation curves in the three stages of the programming operation of the flash memory according to an embodiment of the present invention. In the method of the present invention, the three stages of the programming operation are controlled by the first programming signal Prog2. Figure 4 The curve of the first programming signal Prog2 is also represented by Prog2. It can be seen that the first programming signal Prog2 includes two pulses, marked by '1' and '2' respectively. The first pulse '1' defines the first programming stage, the second pulse '2' defines the third programming stage, and the interval between the first pulse '1' and the second pulse '2' defines the second verification stage.

[0146] Figure 4 In this context, the bit line programming voltage is the voltage of the first bit line BL0, therefore the curve of the bit line programming voltage is still represented by BL0. The bit line programming voltage rises to a first positive voltage during the time period defined by the first pulse '1', drops to 0V during the time period defined by the interval between the first pulse '1' and the second pulse '2', and rises to a second positive voltage during the time period defined by the second pulse '2'. Therefore, the first programming signal Prog2 can control the three stages of the programming operation.

[0147] In some embodiments, the control signal includes a programming signal Prog and a write enable signal We. During the programming operation, the programming signal Prog switches to a high level; the write enable signal We switches to an enable signal. Figure 4 In the above, the write enable signal We is also enabled when it is at a high level.

[0148] In some embodiments, the proportion of the storage cells 101 in the first portion is more than 90%. For example, if the proportion of the storage cells 101 in the first portion is 95%, then 95% of the storage cells 101 in the flash memory only need to undergo the first programming once, without needing the second programming; while only 5% of the storage cells 101 need to undergo the second programming. Therefore, the first programming is weak-disturbance programming, which is a dispersed program, capable of programming most of the storage cells 101; the second programming is strong-disturbance programming, which is a convergence program, ultimately capable of programming all the storage cells 101. Since the total number of times the second programming is reduced, the programming interference caused by the second programming is also reduced, ultimately reducing programming interference as well. Figure 4 In this context, the first programming step is also represented by Firsttry, the verification in the second verification stage is also represented by Verify, and the second programming step is also represented by Secondtry.

[0149] In the method of this embodiment of the invention, the programming voltage control method further includes setting the word line programming voltage and the control gate programming voltage, including: In the first programming stage, the control gate programming voltage is set to a third positive voltage, and the word line programming voltage is set to a fourth positive voltage.

[0150] In the third programming stage, the control gate programming voltage is set to the fifth positive voltage, and the word line programming voltage is set to the sixth positive voltage.

[0151] The third positive voltage is greater than the fifth positive voltage and the fourth positive voltage is less than the sixth positive voltage, so as to improve the programming efficiency in the first programming stage.

[0152] In the second verification stage, the control gate programming voltage is set to 0V, the word line programming voltage is connected to the sixth positive voltage, and the sixth positive voltage is greater than the fifth positive voltage.

[0153] Figure 4 The curves showing the changes in the word line programming voltage and the control gate programming voltage are not displayed, but by referring to curve BL0, it can be seen that the word line programming voltage and the control gate programming voltage will also undergo three stages of change, just like BL0, except that the corresponding magnitudes are different.

[0154] In some specific embodiments, the programming operations of the embodiments of the present invention can be implemented using the parameters in Table 2 below.

[0155] As can be seen from Table 1, in the method of this embodiment, the voltage of BL0 will decrease in the First try, which can reduce programming interference; CG0 will increase and WL will decrease, which will improve programming efficiency to compensate for the reduction in programming efficiency caused by the decrease in BL0.

[0156] In the method of this embodiment of the invention, it is also necessary to specify the control gate line corresponding to the non-selected storage bit, such as... Figure 3 A voltage is applied to the control gate line corresponding to CG1, and a programming current Idp needs to be applied to the second bit line, such as bit line BL1. If the control gate line voltage of the unselected memory bit is applied in the First try and Second try to turn on the region segment of the channel controlled by the first gate structure corresponding to the unselected memory bit, the voltage of CG1 can also be 6V as described in Table 1.

[0157] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A flash memory, characterized in that, It includes multiple storage cells, and the multiple storage cells are arranged to form an array structure of flash memory, wherein the storage cells are arranged in rows and columns in the array structure; Each of the memory cells in the same column is connected in parallel between two adjacent bit lines; For a selected memory cell, the two bit lines connected to the selected memory cell are the first bit line and the second bit line, respectively. The first bit line is the bit line located on the side of the selected memory bit closer to the selected memory cell. When programming a selected memory bit of the selected memory cell, the first bit line is connected to the bit line programming voltage. The programming operation has the following three stages: The first programming stage is used to perform the first programming of the selected memory bit, wherein the bit line programming voltage in the first programming stage is set to a first positive voltage; The second verification stage is used to verify the state of the selected memory bit, and the bit line programming voltage is set to 0V. The third programming stage is used to perform a second programming of the selected memory bit, wherein the bit line programming voltage is set to a second positive voltage in the third programming stage; In the second verification stage, if the verification result is normal, the third programming stage is omitted; if the verification result is abnormal, the third programming stage is performed. In the array structure, the bit line programming voltage required for normal programming of each memory cell has a deviation; The first positive voltage is less than the second positive voltage. The first positive voltage satisfies the programming requirements of the memory cells in the first part of the array structure. Programming interference is reduced by lowering the first positive voltage. The memory cells that cannot be programmed normally under the first positive voltage constitute the memory cells of the second part. The second positive voltage satisfies the programming requirements of the memory cells of the second part. The number of the second part is less than the number of the first part. By reducing the number of the second part, the cumulative effect of programming interference of the second positive voltage is reduced.

2. The flash memory as described in claim 1, characterized in that: Each of the aforementioned memory cells employs a discrete-gate floating-gate device; The split-gate floating gate device includes: a first source-drain region and a second source-drain region symmetrically arranged, a plurality of split first gate structures with floating gates located between the first source-drain region and the second source-drain region, and a second gate structure located between the first gate structures; the first gate structure has a control gate located on top of the floating gate. The first source-drain region and the second source-drain region of each of the memory cells are connected to the corresponding bit lines; The first source-drain regions of each of the memory cells in the same column and the first source-drain regions of adjacent memory cells are connected together, and the second source-drain regions of each of the memory cells in the same column and the second source-drain regions of adjacent memory cells are connected together.

3. The flash memory as described in claim 2, characterized in that: The split-gate floating gate device is a dual split-gate floating gate device, and the number of the first gate structures is two.

4. The flash memory as described in claim 3, characterized in that: The separated gate floating gate device is an N-type device, and both the first source / drain region and the second source / drain region are composed of N+ regions; The P-type doped channel region is located between the first source / drain region and the second source / drain region and is covered by each of the first gate structure and the second gate structure, each of the first gate structure and the second gate structure controlling the region segment of the covered channel region respectively.

5. The flash memory as described in claim 2 or 3, characterized in that: In the array structure, the second gate structures of each memory cell in the same row are connected to the word line of the same row, and the control gates of the first gate structures of each memory cell in the same row are connected to the control gate line of the same row. When programming the selected memory bit of the selected memory cell, the word line corresponding to the selected memory cell is connected to the word line programming voltage, and the control gate line corresponding to the selected memory bit in the selected memory cell is connected to the control gate programming voltage. In the programming operation, the word line programming voltage and the control gate programming voltage are set as follows: In the first programming stage, the control gate programming voltage is set to a third positive voltage, and the word line programming voltage is set to a fourth positive voltage; In the third programming stage, the control gate programming voltage is set to the fifth positive voltage, and the word line programming voltage is set to the sixth positive voltage; The third positive voltage is greater than the fifth positive voltage and the fourth positive voltage is less than the sixth positive voltage, so as to improve the programming efficiency in the first programming stage.

6. The flash memory as described in claim 5, characterized in that: In the second verification stage, the control gate programming voltage is set to 0V, the word line programming voltage is connected to the sixth positive voltage, and the sixth positive voltage is greater than the fifth positive voltage.

7. The flash memory as described in claim 2, characterized in that: The three stages of the programming operation are controlled by a first programming signal, which includes two pulses. The first pulse defines the first programming stage, the second pulse defines the third programming stage, and the interval between the first pulse and the second pulse defines the second verification stage.

8. The flash memory as described in claim 1, characterized in that: The storage units in the first part account for more than 90%.

9. A method for controlling the programming voltage of flash memory, characterized in that, Flash memory includes multiple storage cells arranged to form an array structure of flash memory, wherein the storage cells are arranged in rows and columns in the array structure; Each of the memory cells in the same column is connected in parallel between two adjacent bit lines; For a selected memory cell, the two bit lines connected to the selected memory cell are the first bit line and the second bit line, respectively. The first bit line is the bit line located on the side of the selected memory bit closer to the selected memory cell. When programming a selected memory bit of the selected memory cell, the first bit line is connected to the bit line programming voltage. In the programming operation, the programming voltage control method includes the following steps: A first programming stage is set up and the selected memory bit is programmed for the first time in the first programming stage, wherein the bit line programming voltage in the first programming stage is set to a first positive voltage; A second verification stage is set up, and the state of the selected memory bit is verified in the second verification stage, wherein the bit line programming voltage is set to 0V; A third programming stage is set up and the selected memory bit is programmed a second time in the third programming stage, wherein the bit line programming voltage is set to a second positive voltage; In the second verification stage, if the verification result is normal, the third programming stage is omitted; if the verification result is abnormal, the third programming stage is performed. In the array structure, the bit line programming voltage required for normal programming of each memory cell has a deviation; The first positive voltage is less than the second positive voltage. The first positive voltage satisfies the programming requirements of the memory cells in the first part of the array structure. Programming interference is reduced by lowering the first positive voltage. The memory cells that cannot be programmed normally under the first positive voltage constitute the memory cells of the second part. The second positive voltage satisfies the programming requirements of the memory cells of the second part. The number of the second part is less than the number of the first part. By reducing the number of the second part, the cumulative effect of programming interference of the second positive voltage is reduced.

10. The flash memory programming voltage control method as described in claim 9, characterized in that: Each of the aforementioned memory cells employs a discrete-gate floating-gate device; The split-gate floating gate device includes: a first source-drain region and a second source-drain region symmetrically arranged, a plurality of split first gate structures with floating gates located between the first source-drain region and the second source-drain region, and a second gate structure located between the first gate structures; the first gate structure has a control gate located on top of the floating gate. The first source-drain region and the second source-drain region of each of the memory cells are connected to the corresponding bit lines; The first source-drain regions of each of the memory cells in the same column and the first source-drain regions of adjacent memory cells are connected together, and the second source-drain regions of each of the memory cells in the same column and the second source-drain regions of adjacent memory cells are connected together.

11. The flash memory programming voltage control method as described in claim 10, characterized in that: The split-gate floating gate device is a dual split-gate floating gate device, and the number of the first gate structures is two.

12. The flash memory programming voltage control method as described in claim 11, characterized in that: The separated gate floating gate device is an N-type device, and both the first source / drain region and the second source / drain region are composed of N+ regions; The P-type doped channel region is located between the first source / drain region and the second source / drain region and is covered by each of the first gate structure and the second gate structure, each of the first gate structure and the second gate structure controlling the region segment of the covered channel region respectively.

13. The flash memory programming voltage control method as described in claim 10 or 11, characterized in that: In the array structure, the second gate structures of each memory cell in the same row are connected to the word line of the same row, and the control gates of the first gate structures of each memory cell in the same row are connected to the control gate line of the same row. When programming the selected memory bit of the selected memory cell, the word line corresponding to the selected memory cell is connected to the word line programming voltage, and the control gate line corresponding to the selected memory bit in the selected memory cell is connected to the control gate programming voltage. The programming voltage control method further includes setting the word line programming voltage and the control gate programming voltage, including: In the first programming stage, the control gate programming voltage is set to a third positive voltage, and the word line programming voltage is set to a fourth positive voltage; In the third programming stage, the control gate programming voltage is set to the fifth positive voltage, and the word line programming voltage is set to the sixth positive voltage; The third positive voltage is greater than the fifth positive voltage and the fourth positive voltage is less than the sixth positive voltage, so as to improve the programming efficiency in the first programming stage.

14. The flash memory programming voltage control method as described in claim 13, characterized in that: In the second verification stage, the control gate programming voltage is set to 0V, the word line programming voltage is connected to the sixth positive voltage, and the sixth positive voltage is greater than the fifth positive voltage.

15. The flash memory programming voltage control method as described in claim 10, characterized in that: The three stages of the programming operation are controlled by a first programming signal, which includes two pulses. The first pulse defines the first programming stage, the second pulse defines the third programming stage, and the interval between the first pulse and the second pulse defines the second verification stage.

16. The flash memory programming voltage control method as described in claim 9, characterized in that: The storage units in the first part account for more than 90%.

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