Memory device and programming method using the same

Abstract

A memory device including a plurality of memory blocks and a plurality of source switches and a programming method using the same. Each of the source switches corresponds to one of the memory blocks, and each of the source switches is coupled to a common source line of the corresponding one of the memory blocks. A selected source switch corresponding to a selected memory block among the memory blocks for a programming operation is configured to bias the common source line of the selected memory block to a reference voltage during a program cycle of the programming operation. Unselected source switches corresponding to unselected memory blocks among the memory blocks for the programming operation are configured to float the common source lines of the unselected memory blocks during the program cycle of the programming operation.

Description

Technical Field

[0001] This invention relates to a storage device, and more particularly, to a storage device having high cell density and low leakage current, and a programming method using the same. Background Technology

[0002] Flash memory, such as NOR flash memory and NAND flash memory, is widely used for storing data in many applications. Programming operations are performed to write data into the memory cells via word lines, bit lines, and source lines coupled to the cells to be programmed. However, conventional memories experience bit line leakage current flowing through unselected memory cells during programming operations. The amount of bit line leakage current increases with the bit line length. Thus, conventional memories are divided into multiple memory blocks with a predetermined capacity corresponding to a predetermined number of word lines (i.e., 2 megabytes per block). Due to bit line leakage current, the number of word lines in each memory block is limited. Furthermore, a pair of bit line splitting circuits are designed at both ends of each memory block to reduce bit line leakage current during programming operations. However, because memories comprise a large number of memory blocks, the number of bit line splitting circuits is large, resulting in large-size and low-cell-density memories. Summary of the Invention

[0003] The present invention provides a memory device, a memory array, and a programming method thereon that can improve cell density and programming efficiency.

[0004] A storage device includes multiple memory arrays, each of which includes multiple memory blocks and multiple source switches. Each of the multiple memory blocks includes multiple memory cells coupled to a common source line. Each of the multiple source switches corresponds to one of the multiple memory blocks, and each of the multiple source switches is coupled to the common source line of the corresponding one of the multiple memory blocks. A selected source switch corresponding to a selected memory block for a programming operation is configured to apply a reference voltage to the common source line of the selected memory block during a programming cycle of the programming operation. An unselected source switch corresponding to an unselected memory block for a programming operation is configured to float the common source line of the unselected memory block during a programming cycle of the programming operation.

[0005] A method for programming a storage array includes selecting a storage block from a plurality of storage blocks in the storage array for a programming operation, the selected storage block including a selected storage cell for the programming operation. During a programming cycle of the programming operation, a reference voltage is applied to a shared source line coupled to the selected storage block of the storage array. During the programming cycle of the programming operation, the shared source lines coupled to unselected storage blocks of the storage array are floated. Attached Figure Description

[0006] Figure 1 This is a schematic diagram illustrating a storage device according to some embodiments.

[0007] Figure 2 This is a schematic diagram illustrating a storage array according to some embodiments.

[0008] Figure 3 This is a schematic diagram illustrating a storage block during programming operations according to some embodiments.

[0009] Figures 4A to 4C This is a waveform diagram showing the word line voltage and bit line voltage during programming operations according to some embodiments.

[0010] Figure 4D The threshold distribution of storage cells in a storage array according to some embodiments is shown.

[0011] Figure 5 This is a flowchart illustrating a programming method according to some embodiments.

[0012] [Explanation of Symbols]

[0013] 100: Storage devices

[0014] 101: Storage Array

[0015] 110: Memory chip

[0016] 112, 114: Bit line splitting circuit

[0017] 120: Decoder circuit

[0018] 130: Read / Write Circuit

[0019] 140: Control Circuit

[0020] 101_1, 101_k: Storage array

[0021] 116_1, 116_2, 116_m: Source switches

[0022] 510, 520, 530: Steps

[0023] B1, B2, Bm: Storage blocks

[0024] BL1, BLn: Bit lines

[0025] CRL1, CRL2, CRLm: Control signals

[0026] EN1, ENn: Enable signals

[0027] Ipgm: Programming Current

[0028] GBL1, GBL2: Global Bit Lines

[0029] GND: Reference Node

[0030] MC, MC1: Storage unit

[0031] SL1, SL2, SLm: Shared source line

[0032] SL11, SL1y, SLn1, SLny: Local source lines

[0033] T: Programming cycle

[0034] t1, t2, ta, tb, tc: Time points

[0035] T1, T2, Tm: Transistors

[0036] T12, T14, Tn2, Tn4: Switches

[0037] V_BL: Programming voltage / Bit line voltage

[0038] VP1, VP2: Single pulse voltage

[0039] VP11, VP12, VP21, VP22: Voltage pulses

[0040] VT1: Original threshold voltage

[0041] VT2: Instantaneous threshold voltage

[0042] VT3: Target threshold voltage

[0043] V_WL: Voltage / Word Line Voltage

[0044] WL11, WL1x, WLm1, WLmx: Partial letter lines Detailed Implementation

[0045] Figure 1A schematic diagram of a memory device 100 including a memory chip 110, a decoder circuit 120, a read / write circuit 130, and a control circuit 140 is shown. The memory chip 110 includes multiple memory arrays 101_1 to 101_k, each of which includes multiple memory cells (not shown) for storing data. In an embodiment, each of the memory arrays 101_1 to 101_k includes multiple memory blocks and a pair of bit line splitting circuits configured to separate the bit lines of one of the memory arrays 101_1 to 101_k from the bit lines of the other. In an embodiment, each memory block may have a predetermined capacity, and only one pair of bit line splitting circuits is included in each of the memory arrays 101_1 to 101_k. In this way, the number of bit line splitting circuits is reduced compared to designs in conventional memories. In one embodiment, the memory blocks in each of the memory arrays 101_1 to 101_k are formed in a single semiconductor well. In another embodiment, the memory arrays 101_1 to 101_k are NOR memory arrays.

[0046] Decoder circuitry 120 is coupled to memory chip 110 and configured to decode address signals to select memory cells in memory arrays 101_1 to 101_k for storage operations (i.e., read operations or programming operations). Decoder circuitry 120 may include row decoder circuitry (not shown) and column decoder circuitry (not shown) for decoding addresses of memory cells in the memory array. Read / write circuitry 130 is coupled to memory chip 110 and configured to perform a read operation for reading data stored in the selected memory, or a programming operation for writing data to the selected memory cell. Read / write circuitry 130 may include a sense amplifier (not shown) configured to sense data stored in the selected memory cell during a read operation. Read / write circuitry 130 may also include circuitry for writing data to the selected memory cell during a programming operation. Control circuitry 140 is coupled to decoder circuitry 120 and read / write circuitry 130 to control the operation of decoder circuitry 120 and read / write circuitry 130. For example, control circuit 140 can send control signals to decoder circuit 120 to control the decoding operation performed by decoder circuit 120. Control circuit 140 can also send control signals to read / write circuit 130 to perform read or programming operations.

[0047] Figure 2 A schematic diagram of a storage array 101 according to some embodiments is shown. Figure 2 The storage array 101 shown can be Figure 1The memory array 100 shown comprises any one of the memory arrays 101_1 to 101_k. The memory array 101 includes a plurality of memory blocks B1 to Bm, a plurality of common source lines SL1 to SLm, a plurality of source switches 116_1 to 116_m, and a pair of bit line splitting circuits 112 and 114. Each of the source switches 116_1 to 116_m corresponds to one of the memory blocks B1 to Bm; and each of the common source lines SL1 to SLm is coupled between one of the memory blocks B1 to Bm and its corresponding source switch 116_1 to 116_m. For example, the common source line SL1 is coupled between the memory block B1 and the source switch 116_1, and the common source line SLm is coupled between the memory block Bm and the source switch 116_m. The memory blocks B1 to Bm of the memory array 101 may be formed in a single semiconductor well.

[0048] Each of the memory blocks B1 to Bm may include multiple memory cells MC arranged in an array structure comprising multiple rows and multiple columns. The memory cells MC in memory blocks B1 to Bm are coupled to multiple local source lines, multiple local word lines, and multiple bit lines. For example, the memory cells MC in memory block B1 are coupled to local source lines SL11 to SL1y, local word lines WL11 to WL1x, and bit lines BL1 to BLn. Similarly, the memory cells MC in memory block Bm are coupled to local source lines SLn1 to SLny, local word lines WLm1 to WLmx, and bit lines BL1 to BLn, where m, n, x, and y are positive integers. The local source lines of a particular memory block within memory blocks B1 to Bm are coupled to a common source line corresponding to that particular memory block. For example, local source lines SL11 to SL1y of memory block B1 are coupled to a common source line SL1, and local source lines SLn1 to SLny of memory block Bm are coupled to a common source line SLm. Bit lines BL1 to BLn are coupled to a column of memory cells in memory array 101. In other words, unlike local word lines and local source lines that are only coupled to memory cells in memory blocks corresponding to local word lines and local source lines, bit lines BL1 to BLn are coupled to a group of memory cells in all memory blocks B1 to Bm. Operations such as read operations or program operations are performed on memory cell MC by means of the local source lines, local word lines, and bit lines coupled to the memory cell MC.

[0049] In this embodiment, bit line splitting circuits 112 and 114 are coupled to bit lines BL1 to BLn of the memory array 101 and configured to connect the bit lines BL1 to BLn of the memory array 101 to the memory chip (i.e., Figure 1The bit lines of other memory arrays in the memory chip 110 are segmented. In an embodiment, each of the bit line segmentation circuits 112 and 114 includes a plurality of switches, each of which is coupled to a bit line among bit lines BL1 to BLn. Bit line segmentation circuit 112 includes switches T12 to Tn2 respectively coupled to a first end of bit lines BL1 to BLn. Similarly, bit line segmentation circuit 114 includes switches T14 to Tn4 respectively coupled to a second end of bit lines BL1 to BLn. In other words, each of bit lines BL1 to BLn is coupled to one of the switches T12 to Tn2 of bit line segmentation circuit 112 and one of the switches T14 to Tn4 of bit line segmentation circuit 114. For example, bit line BL1 is coupled to switches T12 and T14 of bit line segmentation circuits 112 and 114, and bit line BLn is coupled to switches Tn2 and Tn4 of bit line segmentation circuits 112 and 114.

[0050] Switches T12 to Tn2 of bit line splitting circuit 112 are coupled between bit lines BL1 to BLn and global bit line GBL1, and switches T14 to Tn4 of bit line splitting circuit 114 are coupled between bit lines BL1 to BLn and global bit line GBL2. Depending on design requirements, global bit line GBL1 can be electrically coupled to global bit line GBL2, or it can be electrically isolated from global bit line GBL2. In an embodiment, switches T12 to Tn2 and switches T14 to Tn4 are transistors with control terminals that receive enable signals EN1 to ENn. Enable signals EN1 to ENn can be controlled by a control circuit (i.e., Figure 1 The control circuit 140 in the middle generates this. Furthermore, switches coupled to the same bit line are controlled by the same enable signal. For example, switches T12 and T14 coupled to the same bit line BL1 are controlled by the same enable signal EN1; and switches Tn2 and Tn4 coupled to the same bit line BLn are controlled by the same enable signal ENn.

[0051] In an embodiment, each of source switches 116_1 to 116_m includes a transistor having a first terminal, a second terminal, and a control terminal. The first terminal of the transistor is coupled to one of the common source lines SL1 to SLm, the second terminal of the transistor is coupled to a reference node GND, and the control terminal of the transistor receives a control signal. For example, source switch 116_1 includes a transistor T1 coupled between the common source line SL1 and the reference node GND and controlled by a control signal CRL1. Similarly, source switch 116_m includes a transistor Tm coupled between the common source line SLm and the reference node GND and controlled by a control signal CRLm. The control signals CRL1 to CRLm can be controlled by an external circuit (i.e., such as...). Figure 1 The control circuit 140 shown generates and provides this.

[0052] Source switches 116_1 to 116_m can be individually controlled by control signals CRL1 to CRLm according to the operation performed on the memory block corresponding to the source switch. During a programming operation on a memory cell in a selected memory block, the source switch corresponding to the selected memory block is turned on, while the source switches corresponding to unselected memory blocks are turned off. For example, suppose memory block B1 is the selected memory block for programming operations, and other memory blocks B2 to Bm are unselected memory blocks for programming operations. Source switch 116_1 corresponding to the selected memory block B1 is turned on to electrically connect the common source line SL1 to the reference node GND, thereby applying a reference voltage (i.e., ground voltage) to the common source line SL1 of the selected memory block B1. At the same time, the source switches 116_2 to 116_m corresponding to the unselected storage blocks B2 to Bm are turned off, thereby causing the common source lines SL2 to SLm of the unselected storage blocks B2 to Bm to float during programming operations.

[0053] Figure 3 An example is shown of the voltage applied to the memory cells of memory blocks B1 to Bm during a programming operation on memory cell MC1 of memory block B1, according to some embodiments. It is assumed that memory block B1, including memory cell MC1, is the selected memory block for the programming operation, and the other memory blocks, including memory block Bm, are unselected memory blocks. (Refer to...) Figure 2 and Figure 3 During the programming cycle of the programming operation, source switch 116_1 is turned on by control signal CRL1 to apply a reference voltage to the common source line SL1 corresponding to the selected memory block B1. Simultaneously, during the programming cycle, source switch 116_m is turned off by control signal CRLm to allow the common source line SLm corresponding to the unselected memory block Bm to float. Furthermore, during the programming cycle, voltage V_WL is applied to the local word line WL11 coupled to the selected memory cell MC1, and programming voltage V_BL is applied to the bit line BL1 coupled to the selected memory cell MC1. Therefore, programming current Ipgm flows through the selected memory cell MC1 to program data into the selected memory cell MC1.

[0054] The source lines coupled to the memory cells in the unselected memory block Bm float, and the word lines coupled to the memory cells in the unselected memory block Bm are applied with a reference voltage (i.e., 0 volts). Thus, bit line leakage current due to the high drain voltage between the bit lines and source lines of the unselected memory cells is suppressed, and no bit line leakage current flows through the memory cells in the unselected memory block Bm. Therefore, memory array 101 can include more memory blocks, and memory array 101 requires fewer bit line splitting circuits without reducing the efficiency of programming operations on memory array 101. In this embodiment, only one pair of bit line splitting circuits (i.e., ...) is required for all memory blocks B1 to Bm in memory array 101. Figure 2 (Bit line partitioning circuits 112 and 114 in the memory). Compared to conventional memories where each memory block must include a pair of bit line partitioning circuits, the memory array 101 of the present invention has a high cell density without reducing programming efficiency. For example, each 2Mb memory block in a conventional memory requires a pair of bit line partitioning circuits, while the pair of bit line partitioning circuits can be designed for each 4Mb, 8Mb, 16Mb, etc., without reducing programming efficiency.

[0055] Figures 4A to 4C The diagram illustrates waveforms of the word line voltage V_WL and bit line voltage V_BL for programming a selected memory cell (or a page of memory) during a programming cycle T of a programming operation, according to some embodiments. The selected page of memory may refer to a memory cell in a row of a memory array; and the programming cycle T of the programming operation refers to... Figures 4A to 4C The time period from time t1 to time t2 is shown. Figures 4A to 4C In the programming operation, during the programming cycle T, a reference voltage (i.e., 0V) is applied to the source line coupled to the selected memory cell. During the programming cycle, the selected memory cell changes from the original threshold voltage to the target threshold voltage.

[0056] Reference Figure 4ADuring programming cycle T, a bit line voltage V_BL is applied to the bit line coupled to the selected memory cell, and a word line voltage V_WL is applied to the word line coupled to the selected memory cell. The word line voltage V_WL is an incremental step pulse programming (ISPP) voltage comprising multiple incrementing voltage pulses. The word line voltage V_WL is a two-step ISPP voltage comprising voltage pulses VP11 and VP22, wherein the level of voltage pulse VP11 is lower than the voltage level of voltage pulse VP12. During the first cycle from time t1 to time ta, voltage pulse VP11 of the word line voltage V_WL is applied to the word line coupled to the selected memory cell, and during the second cycle from time ta to time t2, voltage pulse VP12 of the word line voltage V_WL is applied to the word line coupled to the selected memory cell. The number of voltage pulses in the word line voltage V_WL and the duration of the first cycle from time t1 to ta and the second cycle from ta to t2 are not limited in this invention. In addition, during programming cycle T, a bit line voltage V_BL, which is a single pulse voltage VP2, is applied to the bit line coupled to the selected memory cell.

[0057] Figure 4D The distribution of threshold voltages of memory cells during programming operations according to some embodiments is shown. Figure 4D The vertical axis represents the number of memory cells, and the horizontal axis represents the threshold voltage of the memory cells. (Refer to...) Figure 4A and Figure 4D The threshold voltage of the selected memory cell is not immediately pushed from the original threshold voltage VT1 to the target threshold voltage VT3. Instead, the threshold voltage of the selected memory cell is first pushed from the original threshold voltage VT1 to the instantaneous threshold voltage VT2 by the voltage pulse VP11 of the word line voltage V_WL. Then, the threshold voltage of the selected memory cell is pushed from the instantaneous threshold voltage VT2 to the target threshold voltage VT3 by the voltage pulse VP12 of the word line voltage V_WL.

[0058] Figure 4B The waveforms of the word line voltage V_WL and the bit line voltage V_BL according to an embodiment of the present invention are shown. Figure 4A The waveforms of word line voltage V_WL and bit line voltage V_BL in the diagram are as follows: Figure 4B The difference between the waveforms of the word line voltage V_WL and the bit line voltage V_BL is that the word line voltage V_WL is a single-pulse voltage VP1, while the bit line voltage V_BL is a multi-step ISPP voltage. Figure 4BIn this context, the word line voltage V_WL is a single-pulse voltage VP1 with a voltage level, while the bit line voltage V_BL is a two-step ISPP voltage including voltage pulses VP21 and VP22. During the first cycle from time t1 to time tb, voltage pulse VP21 of the bit line voltage V_BL is applied to the bit line coupled to the selected memory cell, and during the second cycle from time tb to time t2, voltage pulse VP22 of the bit line voltage V_BL is applied to the bit line coupled to the selected memory cell. (Refer to...) Figure 4B and Figure 4D Since the bit line coupled to the selected memory cell is subjected to a multi-step ISPP voltage, the threshold voltage of the selected memory cell is pushed from the original threshold voltage VT1 to the instantaneous threshold voltage VT2 by the voltage pulse VP21 before being pushed to the target threshold voltage VT3 by the voltage pulse VP22.

[0059] Figure 4C The waveforms of the word line voltage V_WL and the bit line voltage V_BL are shown according to an embodiment of the present invention. Figure 4A The waveforms of the word line voltage V_WL and bit line voltage V_BL in the diagram are as follows: Figure 4C The difference between the waveforms of the word line voltage V_WL and the bit line voltage V_BL is that both the word line voltage V_WL and the bit line voltage V_BL are multi-step ISPP voltages. Figure 4C In the process, the word line voltage V_WL includes voltage pulses VP11 and VP12, where the voltage level of voltage pulse VP11 is lower than the voltage level of voltage pulse VP12. The bit line voltage V_BL includes voltage pulses VP21 and VP22, where the voltage level of voltage pulse VP21 is lower than the voltage level of voltage pulse VP22. During the first cycle from time t1 to time tc, voltage pulse VP11 is applied to the word line coupled to the selected memory cell, and voltage pulse VP21 is applied to the bit line coupled to the selected memory cell. During the second cycle from time tc to time t2, voltage pulse VP12 is applied to the word line coupled to the selected memory cell, and voltage pulse VP22 is applied to the bit line coupled to the selected memory cell.

[0060] Reference Figures 4A to 4C When a multi-step ISPP voltage is applied to a bit line, word line, or both of the word line and the bit line coupled to the selected memory cell, the programming current flowing to the selected memory cell via the bit line is reduced, the bit line voltage drop caused by the parasitic resistance of the bit line is reduced, and the programming operation requires less power. Therefore, the efficiency of programming operations on the memory cell is improved.

[0061] Figure 5A flowchart illustrating a programming method according to some embodiments is shown. In block 510, a memory block among a plurality of memory blocks in a memory array is selected for a programming operation, wherein the selected memory block includes a selected memory cell for the programming operation. In block 520, during a programming cycle of the programming operation, a reference voltage is applied to a common source line coupled to the selected memory block of the memory array. In block 530, during a programming cycle of the programming operation, a common source line coupled to an unselected memory block of the memory array is floated.

[0062] In summary, applying a reference voltage (i.e., 0 volts) to the common source line coupled to the selected memory block for programming operations, and allowing the common source line coupled to the unselected memory block to float, suppresses bit line leakage current flowing through the unselected memory cells in the unselected memory block. Furthermore, independently controlling multiple source switches in the memory array to apply the reference voltage to the selected memory block and allow the unselected memory blocks to float increases the number of memory blocks included in each memory array without increasing bit line leakage current. Moreover, the entire memory array requires only one pair of bit line splitting circuits, thus reducing the number of bit line splitting circuits in the memory array, increasing the cell density in the memory array, and reducing the size of the memory array. Additionally, multi-step ISPP voltages are applied to the bit lines and / or word lines coupled to the selected memory cells, thereby improving the efficiency of programming operations on the memory array.

Claims

1. A storage device, comprising: Multiple storage arrays, each of the multiple storage arrays comprising: Multiple storage blocks, each of the multiple storage blocks including multiple storage cells coupled to a common source line; A plurality of source switches, each of the plurality of source switches corresponding to one of the plurality of memory blocks, and each of the plurality of source switches being coupled to the common source line of the corresponding one of the plurality of memory blocks; Multiple bit lines, each of which is coupled to a set of memory cells in each of the multiple memory blocks; and Multiple bit line splitting circuits, coupled to the multiple bit lines of the multiple memory arrays, split the multiple bit lines of one of the multiple memory arrays from the bit lines of another of the multiple memory arrays. The selected source switch corresponding to the selected memory block for the programming operation among the plurality of memory blocks is configured to apply a reference voltage to the common source line of the selected memory block during the programming cycle of the programming operation. The unselected source switch corresponding to the unselected memory block among the plurality of memory blocks for the programming operation is configured to cause the common source line of the unselected memory block to float during the programming cycle of the programming operation, and Each of the plurality of memory arrays comprises only two bit line splitting circuits, wherein the first bit line splitting circuit is coupled to a first end of each of the plurality of bit lines, and the second bit line splitting circuit is coupled to a second end of each of the plurality of bit lines.

2. The storage device according to claim 1, wherein Each of the plurality of source switches is independently controlled according to the control signal.

3. The storage device according to claim 2, wherein Each of the plurality of source switches is coupled between the common source line of the corresponding one in the plurality of memory blocks and the reference node that receives the reference voltage. During the programming cycle, the selected source switch corresponding to the selected memory block is turned on to bias the common source line of the selected memory block to the reference voltage, and During the programming cycle, the unselected source switch corresponding to the unselected memory block is turned off, so that the common source line of the unselected memory block floats.

4. The storage device according to claim 1, wherein The plurality of storage arrays are either storage arrays or non-storage arrays. The plurality of memory blocks in each of the plurality of memory arrays are formed in a single semiconductor well, and Each of the plurality of storage blocks includes a predetermined number of the storage units.

5. The storage device according to claim 1, wherein The selected storage block includes selected storage units for the programming operation. The selected memory cell is coupled to the selected bit line, the selected word line, and the selected source line. During the programming cycle, a reference voltage is applied to the selected source line, and During the programming cycle, a word line voltage is applied to the selected word line, wherein the word line bias voltage includes a first word line voltage pulse and a second word line voltage pulse, the second word line voltage pulse being greater than the first word line voltage pulse. During the first cycle of the programming cycle, the first word line voltage pulse is applied to the selected word line, and during the second cycle of the programming cycle, the second word line voltage pulse is applied to the selected word line.

6. The storage device according to claim 1, wherein The selected storage block includes selected storage units for the programming operation. The selected memory cell is coupled to the selected bit line, the selected word line, and the selected source line. During the programming cycle, a reference voltage is applied to the selected source line, and During the programming cycle, a bit line voltage is applied to the selected bit line, wherein the bit line bias voltage comprises a first bit line voltage pulse and a second bit line voltage pulse, the second bit line voltage pulse being greater than the first bit line voltage pulse. During the first cycle of the programming cycle, the first bit line voltage pulse is applied to the selected bit line, and during the second cycle of the programming cycle, the second bit line voltage pulse is applied to the selected bit line.

7. The storage device according to claim 1, wherein The selected storage block includes selected storage units for the programming operation. The selected memory cell is coupled to the selected bit line, the selected word line, and the selected source line. During the programming cycle, a reference voltage is applied to the selected source line, and During the programming cycle, a word line voltage is applied to the selected word line, wherein the word line bias voltage includes a first word line voltage pulse and a second word line voltage pulse, the second word line voltage pulse being greater than the first word line voltage pulse. During the first cycle of the programming cycle, the first word line voltage pulse is applied to the selected word line, and during the second cycle of the programming cycle, the second word line voltage pulse is applied to the selected word line. During the programming cycle, a bit line voltage is applied to the selected bit line, wherein the bit line bias voltage comprises a first bit line voltage pulse and a second bit line voltage pulse, the second bit line voltage pulse being greater than the first bit line voltage pulse. During the first cycle of the programming cycle, the first bit line voltage pulse is applied to the selected bit line, and during the second cycle of the programming cycle, the second bit line voltage pulse is applied to the selected bit line.

8. A method for programming a memory array, comprising: For a programming operation, a storage block is selected from a plurality of storage blocks in the storage array, wherein the selected storage block includes the selected storage cell for the programming operation; During the programming cycle of the programming operation, a reference voltage is applied to the common source line coupled to the selected memory block of the memory array; as well as During the programming cycle of the programming operation, a common source line coupled to an unselected memory block of the memory array is floated, wherein the memory array comprises only two bit line splitting circuits, a first bit line splitting circuit coupled to a first end of the bit line, and a second bit line splitting circuit coupled to a second end of the bit line.

9. The programming method according to claim 8, further comprising: During the programming cycle, the reference voltage is applied to the selected source line coupled to the selected memory cell; An incremental step pulse voltage, including a first word line voltage pulse and a second word line voltage pulse, is applied to the selected word line coupled to the selected memory cell, wherein the second word line voltage pulse is greater than the first word line voltage pulse.

10. The programming method according to claim 8, further comprising: During the programming cycle, the reference voltage is applied to the selected source line coupled to the selected memory cell; An incremental step pulse voltage, including a first bit line voltage pulse and a second bit line voltage pulse, is applied to the selected bit line coupled to the selected memory cell, wherein the second bit line voltage pulse is greater than the first bit line voltage pulse.

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