Apparatus and method for improving flash memory endurance

Abstract

The application discloses a device for improving the endurance of flash memory, and all the storage units adopt separated gate floating gate devices, a second gate structure formed by stacking a word line gate dielectric layer and a word line gate is located between first gate structures with floating gates, and the second gate structure is formed by stacking a word line gate dielectric layer and a word line gate. The device for improving the endurance of flash memory comprises a word line programming voltage generating circuit, a storage area, a trimming signal generating circuit and a control device. The control device is used for realizing: reading the cycle number during programming; the trimming signal generating circuit forms a trimming signal according to the cycle number; the word line programming voltage generating circuit outputs a word line programming voltage according to the trimming signal, and programming is performed by using the word line programming voltage, and the more the cycle number is, the greater the word line programming voltage is. The application further discloses a method for improving the endurance of flash memory. The application can compensate the influence of the erasing and writing number on the programming depth, and can improve the endurance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuits, and in particular to an apparatus for improving the endurance of flash memory. This invention also relates to a method for improving the endurance of flash memory. Background Technology

[0002] like Figure 1 The diagram shown is a cross-sectional view of a conventional flash memory cell. Figure 1 The flash memory shown is a NORD type flash memory; the existing flash memory includes multiple memory cells 101, which form an array unit, and the array units are arranged to form an array structure of the flash memory. Each memory cell 101 uses a discrete gate floating gate device.

[0003] like Figure 1 As shown, the split-gate floating gate device includes: a symmetrical first source / drain region 205a and a second source / drain region 206, a plurality of split first gate structures with floating gates 104 located between the first source / drain region 205a and the second source / drain region 205b, and a second gate structure 103 located between the first gate structures; the first gate structure has a control gate 105 located on top of the floating gates 104.

[0004] The split-gate floating gate device is a dual split-gate floating gate device, and the number of the first gate structures is two, which are represented by the markings 102a and 102b respectively.

[0005] The separated gate floating gate device is an N-type device, and both the first source / drain region 205a and the second source / drain region 205b are composed of N+ regions.

[0006] The P-type doped channel region is located between the first source / drain region 205a and the second source / drain region 205b and is covered by each of the first gate structure and the second gate structure 103. The first source / drain region 205a and the second source / drain region 205b are both formed on the P-type semiconductor substrate 201 and are self-aligned with the outer surfaces of the corresponding two first gate structures. The channel regions are formed by the P-type semiconductor substrate 201 between the first source / drain region 205a and the second source / drain region 205b or by further doping on the P-type semiconductor substrate 201.

[0007] The second source / drain region 205b of the memory cell 101 is connected to the second source / drain electrode, which is connected to the bit line BL1.

[0008] The first source-drain region 205a of the memory cell 101 is connected to the first source-drain electrode, which is connected to the bit line BL0.

[0009] Each of the first gate structures is formed by stacking the tunneling dielectric layer 202, the floating gate 104, the control gate dielectric layer 203, and the control gate 105.

[0010] Each of the second gate structures 103 is formed by stacking a word line gate dielectric layer 204 and a word line gate 106.

[0011] The control gate 105 is connected to the corresponding control gate line, and the word line gate 106 is connected to the word line WL. Figure 1 In the above, the memory cell 101 includes two first gate structures, so the control gate line also includes two lines, denoted by CG0 and CG1 respectively. The control gate 105 of the first gate structure 102a is connected to the control gate line CG0, and the control gate 105 of the first gate structure 102b is connected to the control gate line CG1.

[0012] When programming selected storage bits of the storage unit 101, in order to... Figure 1 Taking the storage bit 'a' corresponding to the floating gate 104 in the first gate structure 102a as an example, where the selected storage bit is used, in some implementations, the applied voltage is as shown in Table 1:

[0013] Table 1

[0014] 9 1.5 5 4.5 Idp

[0015] As shown in Table 1, the voltages applied during programming of storage bit 'a' include:

[0016] The control gate line CG1 is connected to 5V and is used to open, i.e., conduct, the region segment of the channel controlled by the first gate structure 102b.

[0017] The word line WL is connected to 1.5V and is used to open the region segment of the channel region controlled by the second gate structure 103;

[0018] Bit line BL1 is connected to the programming current Idp.

[0019] The control gate line CG0 is connected to a 9V high voltage, and the bit line BL0 is connected to a 4.5V high voltage. In this way, after the programming current passes through the channel region controlled by the first gate structure 102b and the second gate structure 103 and reaches the bottom of the first gate structure 102a, the source-side hot electron injection programming can be realized because both the control gate line CG0 and the bit line BL1 are high voltage.

[0020] The voltage connected to the word line WL, i.e., the word line programming voltage Vwlp, is a fixed voltage, such as 1.5V as listed above. Figure 2AAs shown, curve 301 illustrates the variation of the word line gate threshold voltage (Vt) of a memory cell in a conventional flash memory with the number of cycles. Vt represents the word line gate threshold voltage, and Tcyc represents the test time corresponding to the number of cycles. In practical use, as the number of cycles increases, the threshold voltage of the channel region controlled by the second gate structure 103 of each memory cell, i.e., the word line gate threshold voltage Vt, will change. This is because, as the number of cycles increases, the amount of charge captured by defects in the second gate structure 103 increases, thereby increasing the word line gate threshold voltage Vt. Therefore, curve 301 is a curve that continuously rises with Tcyc, indicating that the programming depth is getting deeper and deeper.

[0021] With the word line programming voltage Vwlp fixed and the word line gate threshold voltage Vt increasing, the programming depth of the memory cell will increase. This is because, taking the programming of memory bit 'a' as an example:

[0022] The voltage at the source end of the channel region controlled by the second gate structure 103 is the word line programming voltage Vwlp minus the word line gate threshold voltage Vt. When the word line gate threshold voltage Vt increases, the voltage at the source end of the channel region controlled by the second gate structure 103 will obviously decrease. This will increase the voltage difference between the bit line BL0 and the source end of the channel region controlled by the second gate structure 103, i.e., the source-drain voltage will increase. The voltage settings of CG0 and BL0 cause the channel region controlled by the first gate structure 102a to operate in the linear region. Therefore, as the source-drain voltage increases, the source-drain current will also increase, thus increasing the source-end hot electron injection efficiency. This increases the number of storage electrons injected into memory bit 'a' through the source-end hot electron injection effect, thereby increasing the programming depth of memory bit 'a'. Figure 2B As shown in Figure 302, the read current of a current-carrying flash memory cell varies with the number of cycles. Ir10 represents the current for... Figure 1 By programming the storage bit 'a' and reading the current after programming another bit, it can be seen that Ir10 decreases continuously with the increase of Tcyc, indicating that Ir10 sigma is getting larger and larger. Summary of the Invention

[0023] The technical problem to be solved by this invention is to provide an apparatus for improving the write endurance of flash memory, which can compensate for the impact of write cycles on programming depth, thereby improving the write endurance of flash memory. To this end, this invention also provides a method for improving the write endurance of flash memory.

[0024] To solve the above-mentioned technical problems, the present invention provides an apparatus for improving the write resistance of flash memory, wherein the flash memory includes multiple storage cells; each of the storage cells adopts a discrete gate floating gate device.

[0025] The split-gate floating gate device includes: a first source-drain region and a second source-drain region symmetrically arranged, a plurality of split first gate structures with floating gates located between the first source-drain region and the second source-drain region, and a second gate structure located between the first gate structures; the first gate structure has a control gate located on top of the floating gate.

[0026] The channel region is located between the first source / drain region and the second source / drain region and is covered by each of the first gate structure and the second gate structure, and each of the first gate structure and the second gate structure controls the region segment of the channel region covered by each gate structure.

[0027] The second gate structure is composed of a word line gate dielectric layer and a word line gate stacked together; as the number of cycles increases, charge accumulates in the word line gate dielectric layer and increases the word line gate threshold voltage of the region segment of the channel covered by the second gate structure.

[0028] Devices that improve the write endurance of flash memory include:

[0029] A word line programming voltage generation circuit, wherein the input terminal of the word line programming voltage generation circuit is connected to a trimming signal, and the output terminal outputs the word line programming voltage.

[0030] A storage area is used to store the cycle count of the storage unit.

[0031] A trimming signal generation circuit is used to generate a trimming signal related to the number of cycles of the storage cell.

[0032] Control device, used to achieve:

[0033] When programming the selected memory cell, the number of loops is read.

[0034] The trimming signal generation circuit generates the trimming signal based on the number of cycles.

[0035] The word line programming voltage generation circuit outputs the word line programming voltage according to the trimming signal, and uses the word line programming voltage for programming. The more cycles there are, the larger the word line gate threshold voltage becomes, and the larger the word line programming voltage becomes, so as to eliminate the impact of the increase in word line gate threshold voltage on the programming of the memory cell.

[0036] A further improvement is that the control device is also used to achieve:

[0037] The number of cycles in the storage area is updated.

[0038] A further improvement is that the storage area is implemented using additional words in the sectors of the flash memory.

[0039] A further improvement is that the trimming signal generation circuit includes:

[0040] A multiplexer has n inputs and 1 output, and the output of the multiplexer outputs the trimming signal; n is an integer greater than 1.

[0041] There are n trimming code units, and the output of each trimming code unit is connected to one input of the multiplexer.

[0042] A control signal generation circuit is used to decompose the number of cycles into n control signals, each of which corresponds to an interval of the number of cycles.

[0043] Each of the control signals is connected to an input terminal of one of the trimming code units and the output signal of the trimming code unit is set by the control signal.

[0044] The multiplexer also selects one of the output signals of the n trimming code units as the trimming signal according to the control signal.

[0045] A further improvement is that the control device updates the cycle count in the storage area by controlling the erasure process, wherein the erasure process includes:

[0046] Read the number of loops from the appended word.

[0047] The sector is erased.

[0048] The loop count is incremented by 1 and then written into the additional word.

[0049] A further improvement is that the control signal generation circuit is implemented using the control device; under the control device, the programming includes:

[0050] Read the number of loop iterations;

[0051] n control signals are generated according to the number of cycles; the n control signals are transmitted to the trimming signal generation circuit, the trimming signal generation circuit outputs the trimming signal according to the n control signals, and the word line programming voltage generation circuit outputs the word line programming voltage according to the trimming signal.

[0052] Programming is performed using the aforementioned word line programming voltage.

[0053] A further improvement is that, in the programming, the word line programming voltage is used to program a word.

[0054] A further improvement is that the split-gate floating gate device is a dual split-gate floating gate device, and the number of the first gate structures is two.

[0055] To solve the above-mentioned technical problems, the present invention provides a method for improving the write resistance of flash memory, wherein the flash memory includes multiple storage cells; each of the storage cells adopts a discrete gate floating gate device.

[0056] The split-gate floating gate device includes: a first source-drain region and a second source-drain region symmetrically arranged, a plurality of split first gate structures with floating gates located between the first source-drain region and the second source-drain region, and a second gate structure located between the first gate structures; the first gate structure has a control gate located on top of the floating gate.

[0057] The channel region is located between the first source / drain region and the second source / drain region and is covered by each of the first gate structure and the second gate structure, and each of the first gate structure and the second gate structure controls the region segment of the channel region covered by each gate structure.

[0058] The second gate structure is composed of a word line gate dielectric layer and a word line gate stacked together; as the number of cycles increases, charge accumulates in the word line gate dielectric layer and increases the word line gate threshold voltage of the region segment of the channel covered by the second gate structure.

[0059] Methods to improve the write endurance of flash memory include:

[0060] A word line programming voltage generation circuit is configured, wherein the input terminal of the word line programming voltage generation circuit is connected to a trimming signal, and the output terminal outputs the word line programming voltage.

[0061] A storage area is set up to store the number of cycles of the storage unit.

[0062] A trimming signal generation circuit is provided to generate a trimming signal related to the number of cycles of the storage cell.

[0063] When programming the selected memory cell, the programming steps are set as follows:

[0064] The number of loops to read the storage unit.

[0065] The trimming signal is generated based on the number of cycles, and the word line programming voltage is output based on the trimming signal.

[0066] Programming is performed using the word line programming voltage. The more cycles are performed, the higher the word line gate threshold voltage becomes, and the higher the word line programming voltage becomes, in order to eliminate the impact of the increase in the word line gate threshold voltage on the programming of the memory cell.

[0067] A further improvement is that the method for improving the write endurance of flash memory also includes the step of:

[0068] The number of cycles in the storage area is updated.

[0069] A further improvement is that the storage area is implemented using additional words in the sectors of the flash memory.

[0070] A further improvement is that the trimming signal generation circuit includes:

[0071] A multiplexer has n inputs and 1 output, and the output of the multiplexer outputs the trimming signal; n is an integer greater than 1.

[0072] There are n trimming code units, and the output of each trimming code unit is connected to one input of the multiplexer.

[0073] A control signal generation circuit is used to decompose the number of cycles into n control signals, each of which corresponds to an interval of the number of cycles.

[0074] Each of the control signals is connected to an input terminal of one of the trimming code units and the output signal of the trimming code unit is set by the control signal.

[0075] The multiplexer also selects one of the output signals of the n trimming code units as the trimming signal according to the control signal.

[0076] A further improvement is that the method for improving the write endurance of flash memory updates the cycle count in the storage area by controlling the erasure process, wherein the erasure step includes:

[0077] Read the number of loops from the appended word.

[0078] The sector is erased.

[0079] The loop count is incremented by 1 and then written into the additional word.

[0080] A further improvement is that the control signal generation circuit is implemented using a control device; under the control of the control device, the programming steps include:

[0081] The number of loop iterations to read the storage unit;

[0082] The control signal generation circuit generates n control signals according to the number of cycles, the trimming signal generation circuit outputs the trimming signal according to the n control signals, and the word line programming voltage generation circuit outputs the word line programming voltage according to the trimming signal.

[0083] Programming is performed using the aforementioned word line programming voltage.

[0084] A further improvement is that, in the programming step, the word line programming voltage is used to program a word.

[0085] A further improvement is that the split-gate floating gate device is a dual split-gate floating gate device, and the number of the first gate structures is two.

[0086] In flash memory such as NORD flash memory, which uses split-gate floating-gate devices in the storage cell, the present invention provides a device to improve the flash memory's write endurance. The device can adjust the word line programming voltage according to the number of cycles, i.e., the number of erase / write cycles. The adjusted word line programming voltage can compensate for the effect of the increase in word line gate threshold voltage on programming when the number of cycles increases, thereby avoiding the increase in programming depth with the increase of the number of cycles, and finally improving the flash memory's write endurance. Attached Figure Description

[0087] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0088] Figure 1 This is a cross-sectional structural diagram of an existing flash memory storage cell;

[0089] Figure 2A This is a curve showing the change of word line gate threshold voltage of existing flash memory cells with the number of cycles;

[0090] Figure 2B It is a curve showing the change in read current of an existing flash memory cell with the number of cycles;

[0091] Figure 3 This is a schematic diagram of the structure of a device for improving the erasure and write resistance of flash memory according to an embodiment of the present invention;

[0092] Figure 4A This is a schematic diagram of the storage region for the number of cycles in a preferred embodiment of the present invention for improving the erasure and write resistance of flash memory;

[0093] Figure 4B This is a flowchart of the erasure operation in the apparatus for improving the erasure and write resistance of flash memory according to a preferred embodiment of the present invention;

[0094] Figure 4C This is a flowchart of programming in the apparatus for improving the erasure and write resistance of flash memory according to a preferred embodiment of the present invention;

[0095] Figure 5 This is a schematic diagram of the trimming signal generation circuit and the word line programming voltage generation circuit in the apparatus for improving the erasure and write resistance of flash memory according to a preferred embodiment of the present invention. Detailed Implementation

[0096] like Figure 3 The diagram shown is a structural schematic of a device for improving the write endurance of flash memory according to an embodiment of the present invention. In this device, the flash memory includes multiple storage units 101. Please refer to [reference needed for details on storage units 101]. Figure 1 As shown, a NORD type flash memory storage cell 101 is used; each of the storage cells 101 uses a split-gate floating gate 104 device.

[0097] like Figure 1 As shown, the split-gate floating gate device includes: a symmetrical first source / drain region 205a and a second source / drain region 206, a plurality of split first gate structures with floating gates 104 located between the first source / drain region 205a and the second source / drain region 205b, and a second gate structure 103 located between the first gate structures; the first gate structure has a control gate 105 located on top of the floating gates 104.

[0098] The channel region is located between the first source / drain region 205a and the second source / drain region 205b and is covered by each of the first gate structure and the second gate structure 103. Each of the first gate structure and the second gate structure 103 controls the region segment of the channel region covered by each gate structure.

[0099] The second gate structure 103 is formed by stacking a word line gate 106 dielectric layer 204 and a word line gate 106. As the number of cycles increases, charge accumulates in the word line gate 106 dielectric layer 204, increasing the word line gate threshold voltage Vt in the region of the channel covered by the second gate structure 103. Please refer to [reference needed] for details. Figure 2A The curve 301 is shown.

[0100] In this embodiment of the invention, the split-gate floating gate device is a dual split-gate floating gate device, and the number of the first gate structures is two, which are respectively represented by the markings 102a and 102b.

[0101] The split-gate floating-gate device is an N-type device, and both the first source / drain region 205a and the second source / drain region 205b are composed of N+ regions. The channel region is P-type doped. Both the first source / drain region 205a and the second source / drain region 205b are formed on a P-type semiconductor substrate 201 and are self-aligned with the outer surfaces of the corresponding two first gate structures. The channel regions are formed by the P-type semiconductor substrate 201 between the first source / drain region 205a and the second source / drain region 205b, or further formed by doping on the P-type semiconductor substrate 201. In other embodiments, the split-gate floating-gate device can also be a P-type device, with both the first source / drain region 205a and the second source / drain region 205b composed of P+ regions, and the channel region being N-type doped.

[0102] The second source / drain region 205b of the memory cell 101 is connected to the second source / drain electrode, which is connected to the bit line BL1.

[0103] The first source-drain region 205a of the memory cell 101 is connected to the first source-drain electrode, which is connected to the bit line BL0.

[0104] Each of the first gate structures is formed by stacking the tunneling dielectric layer 202, the floating gate 104, the control gate dielectric layer 203, and the control gate 105.

[0105] Each of the second gate structures 103 is formed by stacking a word line gate dielectric layer 204 and a word line gate 106.

[0106] The control gate 105 is connected to the corresponding control gate line, and the word line gate 106 is connected to the word line WL. Figure 1 In the above, the memory cell 101 includes two first gate structures, so the control gate line also includes two lines, denoted by CG0 and CG1 respectively. The control gate 105 of the first gate structure 102a is connected to the control gate line CG0, and the control gate 105 of the first gate structure 102b is connected to the control gate line CG1.

[0107] Devices that improve the write endurance of flash memory include:

[0108] The word line programming voltage Vwlp generation circuit 404 has an input terminal connected to the trim signal trim and an output terminal that outputs the word line programming voltage Vwlp.

[0109] Storage area 401 is used to store the number of cycles of the storage unit 101.

[0110] In some preferred embodiments, such as Figure 4A The diagram shown is a schematic representation of the storage region for the number of cycles in a preferred embodiment of the device for improving the write endurance of flash memory. The storage region 401 is implemented using an additional word 401a in sector 405 of the flash memory. Figure 4A In this context, sector 405 is also represented by "sector", and the additional word 401a is also represented by "extraworld to store cycling info".

[0111] The trim signal generation circuit 403 is used to generate the trim signal trim related to the number of cycles of the storage unit 101.

[0112] Control device 402 is used to achieve:

[0113] When programming the selected storage unit 101, the loop count is read. Figure 3 In this context, the number of iterations is represented by Cycling.

[0114] The trim signal generation circuit 403 generates the trim signal trim based on the number of cycles.

[0115] The word line programming voltage Vwlp generation circuit 404 outputs the word line programming voltage Vwlp according to the trim signal trim, and uses the word line programming voltage Vwlp for programming. The more cycles there are, the larger the word line gate threshold voltage Vt becomes, and the larger the word line programming voltage Vwlp becomes, so as to eliminate the impact of the increase in word line gate threshold voltage Vt on the programming of the memory cell 101.

[0116] In this embodiment of the invention, the control device 402 is further configured to update the cycle count in the storage area 401. In some preferred embodiments, the control device 402 updates the cycle count in the storage area 401 by controlling an erase operation. Figure 4B The diagram shows a flowchart of the erasure operation in a preferred embodiment of the apparatus for improving the erasure and write resistance of flash memory; the erasure includes:

[0117] Step S101: Receive the erase command and begin erasing. Figure 4B In Chinese, the erase command is also represented by Erase CMD.

[0118] Step S102: Read the loop count in the appended word 401a, i.e. Figure 4B The Readcycling info is shown below.

[0119] Step S103: Erase the sector 405, that is... Figure 4B The Erase sector is shown in the diagram.

[0120] Step S104: Increment the loop count by 1 and write it into the additional word 401a, i.e. Figure 4B The example shows Cycling+1; write extra word.

[0121] like Figure 5 As shown, the trimming signal generation circuit 403 includes:

[0122] The multiplexer 407 has n input terminals and 1 output terminal. The output terminal of the multiplexer 407 outputs the trimming signal trim; n is an integer greater than 1. Figure 5 In this context, the multiplexer 407 is also represented by MUX.

[0123] There are n trimming code units 406, and the output of each trimming code unit is connected to one input of the multiplexer 407. Figure 5 In this context, the trim code unit 406 is also represented by a numbered trim code.

[0124] A control signal generation circuit is used to decompose the number of cycles into n control signals, each of which corresponds to an interval of the number of cycles.

[0125] Each of the control signals is connected to an input terminal of one of the trimming code units 406 and the output signal of the trimming code unit 406 is set by the control signal.

[0126] The multiplexer 407 also selects one of the output signals of the n trimming code units 406 as the trimming signal trim, according to the control signal.

[0127] In some preferred embodiments, the control signal generation circuit is implemented using the control device 402, under which, as... Figure 4C The diagram shown is a flowchart of programming in a preferred embodiment of the device for improving the erasure and write resistance of flash memory according to the present invention; the programming includes:

[0128] Step S201: Receive programming command, programming begins. Figure 4C In this context, programming commands are also represented by Program CMD.

[0129] Step S202: Read the number of loops, i.e. Figure 4C The image shows the reading cycling info.

[0130] Step S203: Generate n control signals according to the number of cycles, i.e. Figure 4C The Togenerate S1 / ... / Sn shown in the diagram. S1, S2 to Sn represent the numbers of each of the control signals, and each control signal corresponds to an interval of the number of cycles. Each control signal is obtained by dividing the number of cycles into several steps.

[0131] The trimming signal generation circuit 403 outputs the trimming signal trim based on the n control signals. For example... Figure 5 As shown, the corresponding trimming code unit 406 is selected according to S1, S2 to Sn. Then, the multiplexer 407 uses the output of the selected trimming code unit 406 as the trimming signal trim.

[0132] The word line programming voltage Vwlp generation circuit 404 outputs the word line programming voltage Vwlp according to the trim signal trim.

[0133] Step S204: Programming is performed using the word line programming voltage Vwlp. In this programming, the word line programming voltage Vwlp is used to program a single word, i.e. Figure 4C The word program shown.

[0134] In flash memory such as NORD flash memory using a split-gate floating-gate 104 device in storage cell 101, this embodiment of the invention includes a device to improve the write endurance of the flash memory. This device adjusts the word line programming voltage Vwlp based on the number of cycles (i.e., the number of erase / write cycles). The adjusted word line programming voltage Vwlp compensates for the increase in word line gate threshold voltage Vt as the number of cycles increases, thus preventing the programming depth from increasing with the number of cycles and ultimately improving the write endurance of the flash memory. Therefore, in this embodiment of the invention, although the curve of the word line gate threshold voltage Vt changes with... Figure 2A Similarly, however, after programming according to the embodiments of the present invention, Ir10 will no longer decrease with the increase of Tcye, so the device's write and erase resistance can be improved in the end.

[0135] This invention provides a method for improving the write endurance of flash memory:

[0136] In the method for improving the write endurance of flash memory according to the embodiments of the present invention, the flash memory includes a plurality of storage cells 101, and the storage cells 101 of the flash memory are also referred to Figure 1 As shown, a NORD type flash memory storage cell 101 is used; each of the storage cells 101 uses a split-gate floating gate 104 device.

[0137] like Figure 1 As shown, the split-gate floating gate device includes: a symmetrical first source / drain region 205a and a second source / drain region 206, a plurality of split first gate structures with floating gates 104 located between the first source / drain region 205a and the second source / drain region 205b, and a second gate structure 103 located between the first gate structures; the first gate structure has a control gate 105 located on top of the floating gates 104.

[0138] The channel region is located between the first source / drain region 205a and the second source / drain region 205b and is covered by each of the first gate structure and the second gate structure 103. Each of the first gate structure and the second gate structure 103 controls the region segment of the channel region covered by each gate structure.

[0139] The second gate structure 103 is formed by stacking a word line gate 106 dielectric layer 204 and a word line gate 106. As the number of cycles increases, charge accumulates in the word line gate 106 dielectric layer 204, increasing the word line gate threshold voltage Vt in the region of the channel covered by the second gate structure 103. Please refer to [reference needed] for details. Figure 2A The curve 301 is shown.

[0140] In the method of this embodiment of the invention, the split-gate floating gate device is a dual split-gate floating gate device, and the number of the first gate structures is two, which are respectively represented by the markings 102a and 102b.

[0141] The separated gate floating gate device is an N-type device, and both the first source / drain region 205a and the second source / drain region 205b are composed of N+ regions. The channel region is P-type doped. Both the first source / drain region 205a and the second source / drain region 205b are formed on a P-type semiconductor substrate 201 and are self-aligned with the outer surfaces of the corresponding two first gate structures. The channel regions are formed by the P-type semiconductor substrate 201 between the first source / drain region 205a and the second source / drain region 205b, or further formed by doping on the P-type semiconductor substrate 201. In other embodiments, the separated gate floating gate device can also be a P-type device, with both the first source / drain region 205a and the second source / drain region 205b composed of P+ regions, and the channel region being N-type doped.

[0142] The second source / drain region 205b of the memory cell 101 is connected to the second source / drain electrode, which is connected to the bit line BL1.

[0143] The first source-drain region 205a of the memory cell 101 is connected to the first source-drain electrode, which is connected to the bit line BL0.

[0144] Each of the first gate structures is formed by stacking the tunneling dielectric layer 202, the floating gate 104, the control gate dielectric layer 203, and the control gate 105.

[0145] Each of the second gate structures 103 is formed by stacking a word line gate dielectric layer 204 and a word line gate 106.

[0146] The control gate 105 is connected to the corresponding control gate line, and the word line gate 106 is connected to the word line WL. Figure 1 In the above, the memory cell 101 includes two first gate structures, so the control gate line also includes two lines, denoted by CG0 and CG1 respectively. The control gate 105 of the first gate structure 102a is connected to the control gate line CG0, and the control gate 105 of the first gate structure 102b is connected to the control gate line CG1.

[0147] Methods to improve the write endurance of flash memory include:

[0148] A word line programming voltage Vwlp generation circuit 404 is configured, wherein the input terminal of the word line programming voltage Vwlp generation circuit 404 is connected to the trim signal trim, and the output terminal outputs the word line programming voltage Vwlp.

[0149] A storage area 401 is provided to store the number of cycles of the storage unit 101.

[0150] In some preferred embodiments of the method, such as Figure 4A The diagram shown is a schematic representation of the storage region for the number of cycles in a preferred embodiment of the device for improving the write endurance of flash memory. The storage region 401 is implemented using an additional word 401a in sector 405 of the flash memory. Figure 4A In this context, sector 405 is also represented by "sector", and the additional word 401a is also represented by "extra world to store cycling info".

[0151] A trim signal generation circuit 403 is provided to generate a trim signal trim related to the number of cycles of the storage unit 101.

[0152] When programming the selected memory cell, the programming steps are set as follows:

[0153] Read the number of loop iterations.

[0154] The trim signal trim is generated based on the number of cycles.

[0155] The word line programming voltage Vwlp is output according to the trim signal trim.

[0156] Programming is performed using the word line programming voltage Vwlp. The more cycles are performed, the larger the word line gate threshold voltage Vt becomes, and the larger the word line programming voltage Vwlp becomes, so as to eliminate the impact of the increase in word line gate threshold voltage Vt on the programming of the memory cell 101.

[0157] The method in this embodiment of the invention further includes the step of updating the cycle count in the storage area 401. In some preferred embodiments, the control device 402 updates the cycle count in the storage area 401 by controlling erasure. Figure 4B The diagram shows a flowchart of the erasure operation in a preferred embodiment of the method for improving the erasure and write resistance of flash memory; the erasure includes:

[0158] Step S101: Receive the erase command and begin erasing. Figure 4BIn Chinese, the erase command is also represented by Erase CMD.

[0159] Step S102: Read the loop count in the appended word 401a, i.e. Figure 4B The Readcycling info is shown below.

[0160] Step S103: Erase the sector 405, that is... Figure 4B The Erase sector is shown in the diagram.

[0161] Step S104: Increment the loop count by 1 and write it into the additional word 401a, i.e. Figure 4B The example shows Cycling+1; write extra word.

[0162] like Figure 5 As shown, the trimming signal generation circuit 403 includes:

[0163] The multiplexer 407 has n input terminals and 1 output terminal. The output terminal of the multiplexer 407 outputs the trimming signal trim; n is an integer greater than 1. Figure 5 In this context, the multiplexer 407 is also represented by MUX.

[0164] There are n trimming code units 406, and the output of each trimming code unit is connected to one input of the multiplexer 407. Figure 5 In this context, the trim code unit 406 is also represented by a numbered trim code.

[0165] A control signal generation circuit is used to decompose the number of cycles into n control signals, each of which corresponds to an interval of the number of cycles.

[0166] Each of the control signals is connected to an input terminal of one of the trimming code units 406 and the output signal of the trimming code unit 406 is set by the control signal.

[0167] The multiplexer 407 also selects one of the output signals of the n trimming code units 406 as the trimming signal trim, according to the control signal.

[0168] In some preferred embodiments, the control signal generation circuit is implemented using a control device 402, under which, as... Figure 4C The diagram shown is a flowchart of the programming process in a preferred embodiment of the device for improving the erasure and write resistance of flash memory; the programming includes:

[0169] Step S201: Receive programming command, programming begins. Figure 4CIn this context, programming commands are also represented by Program CMD.

[0170] Step S202: Read the number of loops, i.e. Figure 4C The image shows the reading cycling info.

[0171] Step S203: Generate n control signals according to the number of cycles, i.e. Figure 4C The Togenerate S1 / ... / Sn shown in the diagram. S1, S2 to Sn represent the numbers of each of the control signals, and each control signal corresponds to an interval of the number of cycles. Each control signal is obtained by dividing the number of cycles into several steps.

[0172] The trimming signal generation circuit 403 outputs the trimming signal trim based on the n control signals. For example... Figure 5 As shown, the corresponding trimming code unit 406 is selected according to S1, S2 to Sn. Then, the multiplexer 407 uses the output of the selected trimming code unit 406 as the trimming signal trim.

[0173] The word line programming voltage Vwlp generation circuit 404 outputs the word line programming voltage Vwlp according to the trim signal trim.

[0174] Step S204: Programming is performed using the word line programming voltage Vwlp. In this programming, the word line programming voltage Vwlp is used to program a single word, i.e. Figure 4C The word program shown.

[0175] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A device for improving the write endurance of flash memory, characterized in that, Flash memory includes multiple storage cells; each of the storage cells employs a discrete-gate floating-gate device. The split-gate floating gate device includes: a first source-drain region and a second source-drain region symmetrically arranged, a plurality of split first gate structures with floating gates located between the first source-drain region and the second source-drain region, and a second gate structure located between the first gate structures; the first gate structure has a control gate located on top of the floating gate. The channel region is located between the first source / drain region and the second source / drain region and is covered by each of the first gate structure and the second gate structure, and each of the first gate structure and the second gate structure controls the region segment of the channel region covered by each gate structure. The second gate structure is composed of a word line gate dielectric layer and a word line gate stacked together; as the number of cycles increases, charge accumulates in the word line gate dielectric layer and increases the word line gate threshold voltage of the region segment of the channel covered by the second gate structure; Devices that improve the write endurance of flash memory include: A word line programming voltage generation circuit, wherein the input terminal of the word line programming voltage generation circuit is connected to a trimming signal, and the output terminal outputs the word line programming voltage; A storage area for storing the cycle count of the storage unit; A trimming signal generation circuit is used to generate a trimming signal related to the number of cycles of the storage cell; Control device, used to achieve: When programming the selected memory cell, the number of loops is read; The trimming signal generation circuit generates the trimming signal according to the number of cycles; The word line programming voltage generation circuit outputs the word line programming voltage according to the trimming signal, and uses the word line programming voltage for programming. The more cycles there are, the larger the word line gate threshold voltage becomes, and the larger the word line programming voltage becomes, so as to eliminate the impact of the increase in word line gate threshold voltage on the programming of the memory cell.

2. The apparatus for improving the write endurance of flash memory as described in claim 1, characterized in that: The control device is also used to achieve: The number of cycles in the storage area is updated.

3. The apparatus for improving the write endurance of flash memory as described in claim 2, characterized in that: The storage area is implemented using additional words in the sectors of the flash memory.

4. The apparatus for improving the write endurance of flash memory as described in claim 3, characterized in that: The trimming signal generation circuit includes: A multiplexer has n inputs and 1 output, the output of which outputs the trimming signal; n is an integer greater than 1. n trimming code units, the output of each trimming code unit is connected to one input of the multiplexer; A control signal generation circuit is used to decompose the number of cycles into n control signals, each of the control signals corresponding to an interval of the number of cycles. Each of the control signals is connected to an input terminal of one of the trimming code units and the output signal of the trimming code unit is set by the control signal; The multiplexer also selects one of the output signals of the n trimming code units as the trimming signal according to the control signal.

5. The apparatus for improving the write endurance of flash memory as described in claim 3, characterized in that: The control device updates the cycle count in the storage area by controlling the erasure process, wherein the erasure process includes: Read the loop count from the appended word; The sector is erased; The loop count is incremented by 1 and then written into the additional word.

6. The apparatus for improving the write endurance of flash memory as described in claim 4, characterized in that: The control signal generation circuit is implemented using the control device. Under the control device, the programming includes: Read the number of loop iterations; n control signals are generated according to the number of cycles; the n control signals are transmitted to the trimming signal generation circuit, the trimming signal generation circuit outputs the trimming signal according to the n control signals, and the word line programming voltage generation circuit outputs the word line programming voltage according to the trimming signal. Programming is performed using the aforementioned word line programming voltage.

7. The apparatus for improving the write endurance of flash memory as described in claim 6, characterized in that: In the programming process, the word line programming voltage is used to program a word.

8. The apparatus for improving the write endurance of flash memory as described in claim 1, characterized in that: The split-gate floating gate device is a dual split-gate floating gate device, and the number of the first gate structures is two.

9. A method for improving the write endurance of flash memory, characterized in that, Flash memory includes multiple storage cells; each of the storage cells employs a discrete-gate floating-gate device. The split-gate floating gate device includes: a first source-drain region and a second source-drain region symmetrically arranged, a plurality of split first gate structures with floating gates located between the first source-drain region and the second source-drain region, and a second gate structure located between the first gate structures; the first gate structure has a control gate located on top of the floating gate. The channel region is located between the first source / drain region and the second source / drain region and is covered by each of the first gate structure and the second gate structure, and each of the first gate structure and the second gate structure controls the region segment of the channel region covered by each gate structure. The second gate structure is composed of a word line gate dielectric layer and a word line gate stacked together; as the number of cycles increases, charge accumulates in the word line gate dielectric layer and increases the word line gate threshold voltage of the region segment of the channel covered by the second gate structure; Methods to improve the write endurance of flash memory include: A word line programming voltage generation circuit is configured, wherein the input terminal of the word line programming voltage generation circuit is connected to a trimming signal, and the output terminal outputs the word line programming voltage; A storage area is set up to store the cycle count of the storage unit; A trimming signal generation circuit is provided to generate a trimming signal related to the number of cycles of the storage cell. When programming the selected memory cell, the programming steps are set as follows: The number of loop iterations to read the storage unit; The trimming signal is generated based on the number of cycles, and the word line programming voltage is output based on the trimming signal; Programming is performed using the word line programming voltage. The more cycles are performed, the higher the word line gate threshold voltage becomes, and the higher the word line programming voltage becomes, in order to eliminate the impact of the increase in the word line gate threshold voltage on the programming of the memory cell.

10. The method for improving the erasure and write resistance of flash memory as described in claim 9, characterized in that: The method for improving the write resistance of flash memory also includes the following steps: The number of cycles in the storage area is updated.

11. The method for improving the write endurance of flash memory as described in claim 10, characterized in that: The storage area is implemented using additional words in the sectors of the flash memory.

12. The method for improving the write endurance of flash memory as described in claim 11, characterized in that: The trimming signal generation circuit includes: A multiplexer has n inputs and 1 output, the output of which outputs the trimming signal; n is an integer greater than 1. n trimming code units, the output of each trimming code unit is connected to one input of the multiplexer; A control signal generation circuit is used to decompose the number of cycles into n control signals, each of the control signals corresponding to an interval of the number of cycles. Each of the control signals is connected to an input terminal of one of the trimming code units and the output signal of the trimming code unit is set by the control signal; The multiplexer also selects one of the output signals of the n trimming code units as the trimming signal according to the control signal.

13. The method for improving the write endurance of flash memory as described in claim 11, characterized in that: The method for improving the write endurance of flash memory updates the cycle count in the storage area by controlling the erasure process. The erasure step includes: Read the loop count from the appended word; The sector is erased; The loop count is incremented by 1 and then written into the additional word.

14. The method for improving the write endurance of flash memory as described in claim 12, characterized in that: The control signal generation circuit is implemented using a control device; under the control of the control device, the programming steps include: The number of loop iterations to read the storage unit; The control signal generation circuit generates n control signals according to the number of cycles, the trimming signal generation circuit outputs the trimming signal according to the n control signals, and the word line programming voltage generation circuit outputs the word line programming voltage according to the trimming signal. Programming is performed using the aforementioned word line programming voltage.

15. The method for improving the write endurance of flash memory as described in claim 14, characterized in that: In the programming step, the word line programming voltage is used to program a word.

16. The method for improving the erasure and write resistance of flash memory as described in claim 9, characterized in that: The split-gate floating gate device is a dual split-gate floating gate device, and the number of the first gate structures is two.

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