一种半导体器件及其三维堆叠制造方法
By fabricating vias on the first substrate of a semiconductor device and growing an insulating layer on the sidewalls, and then thinning the vias and bonding them with the second substrate to fill the interconnect metal, the problems of back-side thinning exposure and photolithography alignment accuracy in the prior art are solved, and efficient three-dimensional vertical interconnects and multi-layer chip stacking are realized.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- INST OF MICROELECTRONICS CHINESE ACAD OF SCI LTD
- Filing Date
- 2023-04-24
- Publication Date
- 2026-07-17
AI Technical Summary
Existing methods for 3D stacking of semiconductor devices have problems such as high difficulty in controlling the back-side thinning and exposure process of TSVs, high requirements for alignment accuracy during photolithography and stacking bonding, and insufficient vertical interconnect connectivity.
Through-holes are fabricated on the first substrate and an insulating layer is grown on the sidewalls. After thinning, an insulating layer is deposited on the back side, and then bonded to the second substrate. Interconnect metal is filled into the through-holes. Three-dimensional stacking is performed by bonding first and then filling.
It effectively reduces the process control difficulty of TSV back-side thinning exposure, improves the connectivity of three-dimensional vertical interconnects, and reduces the alignment accuracy requirements during photolithography and stacking bonding. It has good scalability and can be extended to three-dimensional stacking integration of multi-layer chips.
Smart Images
Figure CN116598256B_ABST