半导体结构及其制作方法
By designing interconnected sealing ring structures within the semiconductor structure to form protective rings, the problems of impurities and stress introduction during wafer dicing are solved, thereby improving chip reliability.
CN116598266BActive Publication Date: 2026-07-17CHANGXIN MEMORY TECH INC
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2023-04-26
- Publication Date
- 2026-07-17
AI Technical Summary
Technical Problem
In existing technologies, chip defects caused by wafer dicing processes, especially the introduction of impurities and stress, affect chip reliability.
Method used
In a semiconductor structure, an interconnected first and second sealing ring structure is designed, including annular trenches and redistribution layers and metal layers covering the sidewalls, forming a protective ring to block impurities and stress.
Benefits of technology
It effectively protects the devices within the semiconductor structure, improves chip reliability, and prevents damage during wafer dicing.
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Figure CN116598266B_ABST
Abstract
本公开实施例提供一种半导体结构及其制作方法，其中，半导体结构包括：基底结构，具有密封环区域和器件区域，包括位于器件区域的至少一个器件和位于密封环区域且围绕器件区域呈封闭环的第一密封环结构；钝化层，位于基底结构上方；环状沟槽，贯穿钝化层且延伸至第一密封环结构的顶面；环状沟槽具有相对的第一侧壁和第二侧壁，第一侧壁靠近器件区域，第二侧壁远离器件区域；第二密封环结构，至少覆盖第一侧壁，与第一密封环结构的至少部分顶面接触。
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