Semiconductor device structure

Abstract

A semiconductor element structure is provided. The semiconductor element structure includes a first metallization line, a second metallization line, a first isolation feature, a second isolation feature, a profile modification, and a contact feature. The first metallization line and the second metallization line extend along a first direction. The first isolation feature and the second isolation feature are disposed between the first metallization line and the second metallization line. The first metallization line, the second metallization line, the first isolation feature, and the second isolation feature define an aperture. The profile modification is disposed within the aperture to modify a profile of the aperture in plan view. The contact feature is disposed within the aperture.

Description

[0001] This invention claims priority to U.S. Patent Applications No. 17 / 665,722 and 17 / 666,037 (i.e., priority date "February 7, 2022"), the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] This disclosure relates to a semiconductor device structure, and more particularly to a semiconductor device structure having a profile modifier. Background Technology

[0003] With the rapid development of the electronics industry, integrated circuits (ICs) have achieved high performance and miniaturization. Thanks to advancements in materials and design technologies, current integrated circuits are smaller and more complex than their predecessors.

[0004] Contacts are used to connect different features within or between in a semiconductor structure. For example, a contact is used to connect one conductive feature to another. In some cases, voids may form in the openings filled with the contact material, thus adversely affecting the electrical connection between conductive features. Therefore, a new semiconductor device structure and method are needed to improve this problem.

[0005] The above description of "prior art" provides background information only and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art of this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention

[0006] One aspect of this disclosure provides a semiconductor device structure. The semiconductor device structure includes a first metallization line, a second metallization line, a first isolation feature, a second isolation feature, a contour modifier, and a contact feature. The first metallization line and the second metallization line extend along a first direction. The first isolation feature and the second isolation feature are disposed between the first metallization line and the second metallization line. The first metallization line, the second metallization line, the first isolation feature, and the second isolation feature define an aperture. The contour modifier is disposed within the aperture to modify the profile of the aperture in a plan view. The contact feature is disposed within the aperture.

[0007] Another aspect of this disclosure provides another semiconductor device structure. The semiconductor device structure includes a first metallization line, a second metallization line, a first isolation feature, a second isolation feature, a contour modifier, and a contact feature. The first metallization line and the second metallization line extend along a first direction. The first isolation feature and the second isolation feature are disposed between the first metallization line and the second metallization line. The first metallization line, the second metallization line, the first isolation feature, and the second isolation feature define an aperture. The contour modifier is disposed within the aperture. The contour modifier includes a plurality of mutually separated segments. Each segment is located at a corner of the aperture. The contact feature is disposed within the aperture.

[0008] Another aspect of this disclosure provides a method for fabricating a semiconductor device structure. The method includes: providing a substrate; forming a first metallization line and a second metallization line on the substrate, wherein the first metallization line and the second metallization line extend along a first direction; forming a first isolation feature and a second isolation feature between the first metallization line and the second metallization line, wherein the first metallization line, the second metallization line, the first isolation feature, and the second isolation feature define an aperture; forming a contour modifier to modify the contour of the aperture in a plan view; and forming a contact feature within the aperture.

[0009] Embodiments of this disclosure illustrate a semiconductor device structure with a contour modifier. In some embodiments, a contour modifier can be used to round the aperture to accommodate contact features, such that the contact features have a partially circular, partially elliptical, or partially elliptical contour in a plan view. When conductive material is filled into the circular aperture to form the contact features, voids can be formed with little or no voids, thus increasing the yield of the semiconductor device structure.

[0010] The technical features and advantages of this disclosure have been summarized quite extensively above to provide a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure through modifications or design of other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the appended claims. Attached Figure Description

[0011] A more complete understanding of the disclosure of this application can be obtained by referring to the accompanying drawings in conjunction with the embodiments and claims, wherein the same element symbols in the drawings refer to the same elements.

[0012] Figure 1This is a top view illustrating the layout of semiconductor device structures according to some embodiments of this disclosure.

[0013] Figure 2 This is a magnified view illustrating some embodiments of this disclosure, for example. Figure 1 Region G of the semiconductor element structure shown.

[0014] Figure 3A This is a cross-sectional view illustrating some embodiments of this disclosure along... Figure 1 Semiconductor device structure with A-A' line in the middle.

[0015] Figure 3B This is a cross-sectional view illustrating some embodiments of this disclosure along... Figure 1 Semiconductor device structure with B-B' line in the middle.

[0016] Figure 3C This is a cross-sectional view illustrating some embodiments of this disclosure along... Figure 1 Semiconductor device structure with C-C' line in the middle.

[0017] Figure 4 This is a schematic diagram illustrating a method for fabricating a semiconductor device structure according to some embodiments of the present disclosure.

[0018] Figure 5 , Figure 5A , Figure 5B and Figure 5C These are one or more stages of a method for fabricating a semiconductor structure that exemplifies some embodiments of the present disclosure.

[0019] Figure 6 , Figure 6A , Figure 6B and Figure 6C These are one or more stages of a method for fabricating a semiconductor structure that exemplifies some embodiments of the present disclosure.

[0020] Figure 7 , Figure 7A , Figure 7B and Figure 7C These are one or more stages of a method for fabricating a semiconductor structure that exemplifies some embodiments of the present disclosure.

[0021] Figure 8 , Figure 8A , Figure 8B and Figure 8C These are one or more stages of a method for fabricating a semiconductor structure that exemplifies some embodiments of the present disclosure.

[0022] Figure 9 , Figure 9A , Figure 9B and Figure 9C These are one or more stages of a method for fabricating a semiconductor structure that exemplifies some embodiments of the present disclosure.

[0023] Figure 10 , Figure 10A , Figure 10B and Figure 10C These are one or more stages of a method for fabricating a semiconductor structure that exemplifies some embodiments of the present disclosure.

[0024] Figure 11 , Figure 11A , Figure 11B and Figure 11C These are one or more stages of a method for fabricating a semiconductor structure that exemplifies some embodiments of the present disclosure.

[0025] The attached figures are labeled as follows:

[0026] 100: Semiconductor Component Structure

[0027] 110: Base

[0028] 120-1: Metallized wire

[0029] 120-2: Metallized wire

[0030] 120-3: Metallized wire

[0031] 120s1: Sidewall

[0032] 120s2: Sidewall

[0033] 122-1: Spacer

[0034] 122-2: Spacer

[0035] 122s1: Sidewall

[0036] 124-1: Spacer

[0037] 124-2: Spacer

[0038] 126-1: Spacer

[0039] 126-2: Spacer

[0040] 130-1: Metallized wire

[0041] 130-2: Metallized wire

[0042] 130-3: Metallized wire

[0043] 130-4: Metallized wire

[0044] 140-1: Isolation Features

[0045] 140-2: Isolation Features

[0046] 140-3: Isolation Features

[0047] 140-4: Isolation Features

[0048] 140s1: Sidewall

[0049] 140s2: Sidewall

[0050] 150: Contour Modifier

[0051] 150': Contour finishing material

[0052] 152-1: Segmentation

[0053] 152-2: Segmentation

[0054] 152-3: Segmentation

[0055] 152-4: Segmentation

[0056] 152s1: Sidewall

[0057] 160-1: Contact Characteristics

[0058] 160-2: Contact Characteristics

[0059] 160-3: Contact Characteristics

[0060] 160-4: Contact Characteristics

[0061] 160-5: Contact Characteristics

[0062] 160-6: Contact Characteristics

[0063] 170: Gate structure

[0064] 182: Dielectric layer

[0065] 184: Dielectric layer

[0066] 186: Dielectric layer

[0067] 188: Dielectric layer

[0068] 188o: Opening

[0069] 300: Preparation method

[0070] 310: Operation

[0071] 320: Operation

[0072] 330: Operation

[0073] 340: Operation

[0074] 350: Operation

[0075] 360: Operation

[0076] 370: Operation

[0077] A-A':line

[0078] B-B': line

[0079] C-C': line

[0080] E1: Corner

[0081] G: Area

[0082] R1: Aperture

[0083] R2: Aperture

[0084] W1: Width

[0085] W2: Width

[0086] W3: Width

[0087] W4: Width

[0088] W5: Width

[0089] X: Direction

[0090] Y: direction

[0091] Z: Direction Detailed Implementation

[0092] Embodiments, or examples, of the present disclosure illustrated in the accompanying drawings will now be described in specific language. It should be understood that this is not intended to limit the scope of the disclosure. Any changes or modifications to the described embodiments, and any further application of the principles described herein, should be considered as commonly done by one of ordinary skill in the art related to the content of this disclosure. Reference numerals may be repeated throughout the embodiments, but this does not imply that a feature of one embodiment is applicable to another embodiment, even if they share the same reference numerals.

[0093] It should be understood that although the terms first, second, third, etc., can be used to describe various elements, components, regions, layers, or parts, these elements, components, regions, layers, or parts are not limited by these terms. Rather, these terms are only used to distinguish one element, component, region, layer, or part from another. Therefore, the first element, component, region, layer, or part discussed below can be referred to as the second element, component, region, layer, or part without departing from the teachings of the present invention.

[0094] The terminology used herein is for describing specific embodiments only and is not intended to limit the scope of the invention. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise. It should be further understood that the terms “comprising” and “including” as used in this specification indicate the presence of the stated feature, integer, step, operation, element, or component, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof.

[0095] Figure 1 This is a top view illustrating the layout of a semiconductor element structure 100 according to some embodiments of the present disclosure.

[0096] In some embodiments, the semiconductor device structure 100 may include active and / or passive components. Active components may include a memory chip (e.g., a dynamic random access memory (DRAM) chip, a static random access memory (SRAM) chip, etc.), a power management chip (e.g., a power management integrated circuit (PMIC) chip), a logic chip (e.g., a system-on-a-chip (SoC), a central processing unit (CPU), a graphics processing unit (GPU), an application processor (AP), a microcontroller, etc.), a radio frequency (RF) chip, a sensor chip, a microelectromechanical system (MEMS) chip, a signal processing chip (e.g., a digital signal processing (DSP) chip), a front-end chip (e.g., an analog front-end (AFE) chip), or other active components. Passive components may include a capacitor, a resistor, an inductor, a fuse, or other passive components.

[0097] In some embodiments, the semiconductor device structure 100 may include a plurality of metallization lines 120-1, 120-2 and 120-3, a plurality of metallization lines 130-1, 130-2, 130-3 and 130-4, a plurality of isolation features 140-1, 140-2, 140-3 and 140-4, a plurality of contour modifiers 150, and a plurality of contact features 160-1, 160-2, 160-3, 160-4, 160-5 and 160-6.

[0098] In some embodiments, metallization lines 120-1, 120-2, and 120-3 may extend along the X direction. Metallization lines 120-1, 120-2, and 120-3 may be parallel to each other along the Y direction. Metallization lines 120-1, 120-2, and 120-3 may be spaced apart from each other. In some embodiments, each of metallization lines 120-1, 120-2, and 120-3 may serve as a bit line and may be used to connect, but is not limited to, gate structures (e.g., bit line gates) and contacts (e.g., bit line contacts).

[0099] In some embodiments, the semiconductor device structure 100 may include a plurality of spacers 122-1, 122-2, 124-1, 124-2, 126-1, and 126-2. Each spacer 122-1, 122-2, 124-1, 124-2, 126-1, and 126-2 may be disposed on a sidewall of a metallization line (e.g., 120-1, 120-2, and 120-3). For example, spacers 122-1 and 122-2 may be disposed on two opposite sidewalls of metallization line 120-1. Spacers 122-2 and 124-1 may face each other. Each of spacers 122-1, 122-2, 124-1, 124-2, 126-1, and 126-2 may extend along the X direction. Each of spacers 122-1, 122-2, 124-1, 124-2, 126-1, and 126-2 can be parallel to each other in the Y direction. Each of spacers 122-1, 122-2, 124-1, 124-2, 126-1, and 126-2 can be spaced apart from each other. Each spacer 122-1, 122-2, 124-1, 124-2, 126-1, and 126-2 can be used to isolate the metallized line from the contact features (e.g., 160-1, 160-2, 160-3, 160-4, 160-5, and 160-6).

[0100] In some embodiments, metallization lines 130-1, 130-2, 130-3, and 130-4 may extend along the Y direction. Metallization lines 130-1, 130-2, 130-3, and 130-4 may be parallel to each other along the X direction. Metallization lines 130-1, 130-2, 130-3, and 130-4 may be spaced apart from each other. In some embodiments, each of metallization lines 130-1, 130-2, 130-3, and 130-4 may serve as a word line, used to connect, but not limited to, gate structures (e.g., word line gates) and contacts (e.g., word line contacts).

[0101] In some embodiments, isolation features 140-1, 140-2, 140-3, and 140-4 may be disposed on two opposite sides of a contact feature (e.g., 160-1, 160-2, 160-3, 160-4, 160-5, or 160-6). In some embodiments, each isolation feature 140-1, 140-2, 140-3, and 140-4 may be located between two metallization lines in a plan view. For example, isolation features 140-1 and 140-2 may be located between metallization lines 120-1 and 120-2.

[0102] In some embodiments, each of the isolation features 140-1, 140-2, 140-3, and 140-4 may have a partially circular, partially elliptical, or partially elliptical profile in a plan view. For example, the two sidewalls of isolation feature 140-1, extending from metallization line 120-1 to metallization line 120-2 (or from spacer 122-2 to spacer 124-1), may have an arcuate shape in a plan view. Each of the aforementioned sidewalls may have a protruding surface in a plan view.

[0103] In some embodiments, each of the isolation features 140-1, 140-2, 140-3, and 140-4 may overlap with one of the metallization lines (e.g., 130-1, 130-2, 130-3, and 130-4) along the Z-direction. Although not shown, it should be noted that contact features (e.g., character line contacts) may penetrate one of the isolation features 140-1, 140-2, 140-3, and 140-4 and may be electrically connected to the corresponding metallization line 130-1, 130-2, 130-3, or 130-4. In some embodiments, each isolation feature 140-1, 140-2, 140-3, and 140-4 may contact the sidewall of the spacer of the metallization line. For example, isolation feature 140-1 may contact spacers 122-2 and 124-1.

[0104] In some embodiments, the metallization lines (e.g., 120-1, 120-2, and 120-3) and the isolation features (e.g., 140-1, 140-2, 140-3, and 140-4) can define an aperture (e.g., R1). In some embodiments, the spacers (e.g., 122-1, 122-2, 124-1, 124-2, 126-1, and 126-2) of the metallization lines (e.g., 120-1, 120-2, and 120-3) and the isolation features (e.g., 140-1, 140-2, 140-3, and 140-4) can define an aperture. For example, the spacer 122-2 of the metallization line 120-1, the spacer 124-1 of the metallization line 120-2, and the isolation features 140-1 and 140-2 can define an aperture R1. In some embodiments, the two edges defined by the two sidewalls of the isolation features (such as 140-1 and 140-2) may protrude toward each other in a plan view.

[0105] In some embodiments, the contour modifier 150 may be located within the aperture R1. In some embodiments, the contour modifier 150 may be located at the corner of the aperture R1. In some embodiments, the contour modifier 150 may be used to modify the contour of the aperture R1. In some embodiments, the contour modifier 150 may be used to round the contour of the aperture R1. In some embodiments, the contour modifier 150 may be used to define an aperture R2 (or a circular aperture) having a partially circular, partially elliptical, or partially elliptical contour. In some embodiments, the aperture R2 may be defined by the gaps in the metallization lines (e.g., 122-1, 122-2, 124-1, 124-2, 126-1, and 126-2) and the contour modifier 150. In some embodiments, the contour modifier 150 may overlap with the metallization lines (e.g., 130-1, 130-2, 130-3, and 130-4) along the Z direction.

[0106] In some embodiments, contact features 160-1, 160-2, 160-3, 160-4, 160-5, and 160-6 (or cell contacts) may be arranged along the X direction. In some embodiments, each of contact features 160-1, 160-2, 160-3, 160-4, 160-5, and 160-6 may be located between two metallization lines in a plan view. For example, contact feature 160-1 may be located between metallization lines 120-1 and 120-2. In some embodiments, contact features (e.g., 160-1 and 160-2) may be spaced apart from each other by an isolation feature (e.g., 140-1). In some embodiments, each of contact features 160-1, 160-2, 160-3, 160-4, 160-5, and 160-6 may have a partially circular, partially elliptical, or partially elliptical profile in a plan view. In some embodiments, each contact feature (160-1, 160-2, 160-3, 160-4, 160-5, and 160-6) may contact the sidewall of a spacer (e.g., 122-1, 122-2, 124-1, 124-2, 126-1, and 126-2). In some embodiments, each contact feature (160-1, 160-2, 160-3, 160-4, 160-5, and 160-6) may contact the sidewall of a contour trimmer 150. In some embodiments, each contact feature (160-1, 160-2, 160-3, 160-4, 160-5, and 160-6) may be located within an aperture R1 or R2. In some embodiments, the contour of each contact feature (160-1, 160-2, 160-3, 160-4, 160-5, and 160-6) may be modified or defined by contour modifier 150.

[0107] Figure 2 This is a magnified view illustrating some embodiments of this disclosure, for example. Figure 1Region G of the semiconductor element structure 100 shown.

[0108] like Figure 2 As shown, the metallization line 120-1 may have a sidewall 120s1 on which a spacer 122-2 is disposed. The metallization line 120-2 may have a sidewall 120s2 on which a spacer 124-1 is disposed.

[0109] Isolation feature 140-1 has a sidewall 140s1 facing the sidewall 140-2 of isolation feature 140-2. In some embodiments, sidewalls 140s1 and 140s2 may protrude or project toward each other. In some embodiments, contour trimmer 150 may include segments 152-1, 152-2, 152-3, and 152-4. In some embodiments, segments 152-1, 152-2, 152-3, and 152-4 may be separated from each other. In some embodiments, segments 152-1, 152-2, 152-3, and 152-4 may be located within aperture R1. In some embodiments, segments 152-1, 152-2, 152-3, and 152-4 may be located at a corner (e.g., E1) of aperture R1. For example, segment 152-1 may be located at a corner (e.g., E1) defined by the sidewall 122s1 of the spacer 122-2 of the metallization line 120-1 and the sidewall 140s1 of the isolation feature 140-1. In some embodiments, each of segments 152-1, 152-2, 152-3, and 152-4 may have a sidewall extending from the sidewalls of the spacers (e.g., 122-1, 122-2, 124-1, 124-2, 126-1, and 126-2) and the sidewalls of the isolation features (e.g., 140-1, 140-2, 140-3, and 140-4). For example, segment 152-1 may have a sidewall 152s1 extending from the sidewall 122s1 of the spacer 122-2 to the sidewall 140s1 of the isolation feature 140-1.

[0110] In some embodiments, segments 152-1, 152-2, 152-3, and 152-4 may taper gradually along the Y direction. For example, segment 152-1 tapers gradually along the negative Y direction, while segment 152-3 tapers gradually along the positive Y direction. In some embodiments, each of segments 152-1, 152-2, 152-3, and 152-4 may taper progressively toward a corner (e.g., E1) of the aperture R1. In some embodiments, the sidewalls of the contour modifier 150 may be recessed relative to contact features (e.g., 160-1, 160-2, 160-3, 160-4, 160-5, and 160-6). For example, sidewall 152s1 is recessed relative to the sidewall of contact feature 160-2.

[0111] In some embodiments, each segment (e.g., 152-1) may have a width W1 along the X direction at the sidewall 122s1 of the spacer 122-2, and a width W2 along the X direction between spacers 122-2 and 124-1. Width W1 is greater than width W2. In some embodiments, a portion of the sidewall (e.g., 122s1) of the spacer 122-2 is exposed from the contour trimmer 150.

[0112] In some embodiments, the contact feature (e.g., 160-2) may be surrounded by segments 152-1, 152-2, 152-3 and 152-4 of the contour modifier 150.

[0113] In some embodiments, the sidewalls of the isolation features (e.g., 140-1, 140-2, 140-3, and 140-4) may protrude relative to the contour modifier 150. For example, the sidewall 140s1 of the isolation feature 140-1 may protrude relative to segment 152-1 or 152-3.

[0114] In some embodiments, the aperture R1 may have a width W3 along the X direction at the sidewall 122s2 of spacer 124-1 (or the sidewall 122s1 of spacer 122-2), and a width W4 along the X direction between spacers 122-2 and 122-3. The width W3 is greater than the width W4.

[0115] Figure 3A , Figure 3B and Figure 3C These are cross-sectional views illustrating semiconductor device structures 100 along lines A-A', B-B', and C-C' of some embodiments of this disclosure, such as... Figure 1 As shown.

[0116] like Figure 3AAs shown, the semiconductor device structure 100 may include a substrate 110. The substrate 110 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or a similar substrate. The substrate 110 may include an elemental semiconductor, including silicon or germanium in single-crystal, polycrystalline, or amorphous form; a compound semiconductor material, including at least one of silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; an alloy semiconductor material, including at least one of SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP; any other suitable material; or combinations thereof. In some embodiments, the alloy semiconductor substrate may include a SiGe alloy having a gradient Ge characteristic, wherein the Si to Ge composition changes from the ratio at one location of the gradient SiGe characteristic to the ratio at another location. In another embodiment, the SiGe alloy is formed on a silicon substrate. In some embodiments, the SiGe alloy may be mechanically tensioned by another material in contact with the SiGe alloy. In some embodiments, the substrate 110 may have a multilayer structure, or the substrate 110 may include a multilayer compound semiconductor structure. In some embodiments, p-type and / or n-type dopants may be doped into the substrate 110. In some embodiments, p-type dopants include boron (B), other group 3 elements, or any combination thereof. In some embodiments, n-type dopants include arsenic (As), phosphorus (P), other group V elements, or any combination thereof.

[0117] Although Figure 3A Not shown, but it should be noted that substrate 110 may include an isolation structure disposed therein. The isolation structure may include shallow trench isolation (STI), field oxidation (FOX), zone silicon oxide (LOCOS) features, and / or other suitable isolation elements. The isolation structure may include dielectric materials such as silicon oxide, silicon nitride, silicon oxy-nitride, fluorinated silicates (FSG), low-k dielectric materials, combinations thereof, and / or other suitable materials. In some embodiments, contact features 160-2 and 160-5 may simultaneously contact the silicon substrate (or active region) and the isolation structure of substrate 110.

[0118] The metallization line 120-2 may be disposed on or above the substrate 110 and may be spaced apart from the substrate 110 by a gate structure (e.g., 170). The metallization line 120-2 may include conductive materials such as copper tungsten, aluminum, tantalum, tantalum nitride (TaN), titanium, titanium nitride (TiN), and / or combinations thereof.

[0119] Semiconductor device structure 100 may include a gate structure 170. The gate structure 170 may be disposed on a substrate 110. The gate structure 170 may be disposed between a metallization line (e.g., 120-2) and the substrate 110. In some embodiments, a portion of the gate structure 170 may be located at an elevation lower than the upper surface of the substrate 110. The gate structure 170 may include a gate dielectric layer and a gate electrode layer.

[0120] In some embodiments, the gate dielectric layer may include silicon oxide (SiOx), silicon nitride (SixNy), silicon oxynitride (SiON), or combinations thereof. In some embodiments, the gate dielectric layer may include a dielectric material, such as a high-k dielectric material. High-k dielectric materials may have a dielectric constant (k value) greater than 4. High-k dielectric materials may include hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), yttrium oxide (Y2O3), aluminum oxide (Al2O3), titanium oxide (TiO2), or other suitable materials. Other suitable materials are also within the scope of this disclosure.

[0121] In some embodiments, the gate electrode layer may include a polysilicon layer. In some embodiments, the gate electrode layer may be fabricated using a conductive material, such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), or other suitable materials. In some embodiments, the gate electrode layer may include a work function layer. The work function layer may be fabricated using a metallic material, which may include metals with N-work function or metals with P-work function. N-work function metals include tungsten (W), copper (Cu), titanium (Ti), silver (Ag), aluminum (Al), titanium-aluminum alloy (TiAl), titanium aluminum nitride (TiAlN), tantalum carbide (TaC), tantalum carbon nitride (TaCN), tantalum silicon nitride (TaSiN), manganese (Mn), zirconium (Zr), or combinations thereof. P-work function metals include titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), ruthenium (Ru), or combinations thereof. Other suitable materials are also within the scope of this disclosure. The gate electrode layer can be formed by low-pressure chemical vapor deposition (LPCVD) and plasma-enhanced CVD (PECVD).

[0122] The dielectric layer 182 may be disposed between the metallization line (e.g., 120-1 or 120-3) and the substrate 110. The dielectric layer 182 may include a dielectric material. For example, the dielectric layer 182 may include SiN, SiO2, silicon oxynitride (SiON), silicon carbide nitride (SiCN), silicon carbide (SiC), aluminum oxide (Al2O3), hafnium oxide (HfO2), or lanthanum oxide (La2O3).

[0123] In some embodiments, the semiconductor device structure 100 may include a dielectric layer 184. The dielectric layer 184 may be disposed on or above a metallization line (e.g., 120-1, 120-2, or 120-3). The dielectric layer 184 may include a dielectric material. For example, the dielectric layer 184 may include SiN, SiO2, silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbide (SiC), aluminum oxide (Al2O3), hafnium oxide (HfO2), or lanthanum oxide (La2O3).

[0124] Spacers (e.g., 122-1) may be formed on the sidewalls of dielectric layer 182, metallization line 120-1, and dielectric layer 184. Spacers (e.g., 124-1) may be formed on the sidewalls of dielectric layer 184, metallization line 120-2, and gate structure 170. In some embodiments, a portion of a spacer (e.g., 124-1) may be below the upper surface of substrate 110. In some embodiments, spacers (e.g., 122-1, 122-2, 124-1, 124-2, 126-1, and 126-2) may comprise multiple layers. In some embodiments, spacers (e.g., 122-1, 122-2, 124-1, 124-2, 126-1, and 126-2) may comprise silicon oxide (SiOx), silicon nitride (SixNy), silicon oxynitride (SiON), or combinations thereof. In some embodiments, the spacer (e.g., 122-1, 122-2, 124-1, 124-2, 126-1, and 126-2) may include an air gap. For example, the air gap may be sandwiched between two silicon nitride layers.

[0125] Contact features (e.g., 160-2 or 160-5) may be disposed on the substrate 110. In some embodiments, a portion of the contact feature (e.g., 160-2 or 160-5) may be below the upper surface of the substrate 110. In some embodiments, the contact feature (e.g., 160-2 or 160-5) may contact the spacers of the metallized wires. For example, contact feature 160-2 may contact spacers 122-2 and 124-1 of the metallized wire 120-1.

[0126] In some embodiments, the contact feature (e.g., 160-2 or 160-5) may include a barrier layer (not shown) and a conductive layer (not shown) on the barrier layer. The barrier layer may include titanium, tantalum, titanium nitride, tantalum nitride, manganese nitride, or a combination thereof. The conductive layer may include metals such as tungsten (W), copper (Cu), Ru, Ir, Ni, Os, Rh, Al, Mo, Co, alloys thereof, combinations thereof, or any metallic material having suitable resistance and gap-filling capability. In some embodiments, the contact feature (e.g., 160-2 or 160-5) may include a polycrystalline silicon layer.

[0127] Although Figure 3A Not shown, but it should be noted that another contact feature (e.g., bit line contact) can penetrate dielectric layer 184 and be electrically connected to metallized line 120-2, so metallized line 120-2 can apply a power supply through bit line contact.

[0128] like Figure 3B As shown, the profile modifier 150 can be disposed on the substrate 110 and located between the spacer and the contact feature. For example, segment 152-1 of the profile modifier 150 can be located between the spacer 122-2 and the contact feature 160-2. That is, a portion of the contact feature 160-2 can be separated from the spacer 122-2 by segment 152-1 of the profile modifier 150.

[0129] In some embodiments, the contour modifier 150 may include silicon oxide (SiOx), silicon nitride (SixNy), silicon oxynitride (SiON), or a combination thereof. In some embodiments, the material of the contour modifier 150 may be the same as or similar to the outermost layer of the spacer. In some embodiments, a portion of the contact feature (e.g., 160-2) may contact the sidewall (e.g., 152s1) of the spacer (e.g., 152-1).

[0130] like Figure 3C As shown, a metallization line (e.g., 130-2) can be spaced apart from the gate structure 170 by a dielectric layer 186. The metallization line 130-2 may include a conductive material such as copper tungsten, aluminum, tantalum, tantalum nitride (TaN), titanium, titanium nitride (TiN), and / or combinations thereof. In some embodiments, the metallization line (e.g., 130-2) may be located at a position lower than the upper surface of the substrate 110.

[0131] The dielectric layer 186 may include silicon oxide (SiOx), silicon nitride (SixNy), silicon oxynitride (SiON), or a combination thereof.

[0132] An isolation feature (e.g., 140-1) may be located between metallization lines (e.g., 120-1 and 120-2). The isolation feature (e.g., 140-1) may contact the sidewall (e.g., 122s1) of a spacer (e.g., 122-2). In some embodiments, such as Figure 3A and Figure 3C As shown, the elevation at which the upper surface of the substrate 110 contacts the isolation feature 140-1 can be higher than the elevation at which it contacts the contact feature 160-2.

[0133] In some embodiments, the aperture R2 can be defined using each of the segments 152-1, 152-2, 152-3, and 152-4 of the contour modifier 150, which can have a partially circular, partially elliptical, or partially elliptical profile in a plan view. When a conductive material is filled into the circular aperture R2 to form a contact feature, voids can be formed with little or no voids, thus improving the yield of the semiconductor device structure 100. In a comparative example, conductive material is filled into an opening with a profile similar to that of the aperture R1. As a result, voids that negatively impact electrical connections may be created at the corners of the opening.

[0134] Figure 4 This is a schematic diagram illustrating a method 300 for fabricating a semiconductor element structure according to some embodiments of the present disclosure.

[0135] Fabrication method 300 begins with operation 310, wherein a substrate is provided. A plurality of first metallization lines (e.g., word lines) may be formed within the substrate and extend along a first direction. A plurality of second metallization lines (e.g., bit lines) may be formed on the substrate and extend along a second direction orthogonal to the first direction. A plurality of spacers may be formed on the sidewalls of the second metallization lines and extend along the second direction. A plurality of dielectric layers may be formed on the substrate and located between the spacers of the second metallization lines.

[0136] Fabrication method 300 continues in operation 320, wherein an etching process is performed to remove a first portion of the dielectric layer. Thus, a plurality of openings in the dielectric layer can be formed. Each opening in the dielectric layer has a partially circular, partially elliptical, or partially elliptical profile. Each opening in the dielectric layer may overlap with a first metallization line along a third direction orthogonal to the first and second directions.

[0137] Preparation method 300 continues to operation 330, wherein multiple isolation features can be formed to fill openings in the dielectric layer. Each isolation feature has a partially circular, partially elliptical, or partially elliptical outline. Each isolation feature may overlap with the first metallization line along a third direction orthogonal to the first and second directions.

[0138] Preparation method 300 continues to operation 340, wherein an etching process may be performed on a second portion of the dielectric layer. This forms multiple apertures and exposes the upper surface of the substrate. Each aperture is defined by a second metallization line (or a spacer of the second metallization line) and an isolation feature, having a partially circular, partially elliptical, or partially elliptical profile. Each aperture may have corners defined by the sidewalls of the isolation feature and the sidewalls of the spacer. Each corner of the aperture may taper gradually towards the interface between the isolation feature and the spacer.

[0139] Preparation method 300 continues to operation 350, wherein a contouring material can be formed to cover the upper surface of the substrate, the sidewalls of the second metallization line (or the sidewalls of the spacer), and the sidewalls of the isolation feature. The contouring material can be conformally disposed on the upper surface of the substrate, the sidewalls of the spacer, and the sidewalls of the isolation feature. The contouring material can occupy the corners of the hole.

[0140] Preparation method 300 continues to operation 360, wherein an etching process may be performed to remove a portion of the contouring material, thereby exposing the upper surface of the substrate. The remaining contouring material forms contour modifiers to modify the contour of the aperture. Each contour modifier may have multiple segments located at the corners defined by the sidewalls of the second metallization line (or the sidewalls of the spacer) and the sidewalls of the isolation feature. Each segment of the contour modifier may extend from the sidewall of the second metallization line (or the sidewall of the spacer) to the sidewall of the isolation feature. Therefore, the aperture (or modified aperture) defined by the spacer, the contour modifier, and / or the isolation feature may be circular, and may have a partially circular, partially elliptical, or partially elliptical contour.

[0141] Preparation method 300 continues to operation 370, wherein a conductive material can be deposited to fill the circular aperture. Therefore, multiple contact features can be formed within the circular aperture. Each contact feature can have a partially circular, partially elliptical, or partially elliptical profile.

[0142] Preparation method 300 is merely an example and is not intended to limit the scope of this disclosure beyond that expressly stated in the claims. Additional operations may be provided before, during, or after each operation of preparation method 300, and some of these operations may be replaced, eliminated, or moved for other embodiments of the method. In some embodiments, preparation method 300 may further include... Figure 4 Operations not described herein. In some embodiments, preparation method 300 may include... Figure 4 One or more operations described in the document.

[0143] Figure 5 , Figure 5A , Figure 5B , Figure 5C , Figure 6 , Figure 6A , Figure 6B , Figure 6C , Figure 7 , Figure 7A , Figure 7B , Figure 7C , Figure 8 , Figure 8A , Figure 8B , Figure 8C , Figure 9 , Figure 9A , Figure 9B , Figure 9C , Figure 10 , Figure 10A , Figure 10B , Figure 10C , Figure 11 , Figure 11A , Figure 11B and Figure 11C The various stages of fabrication of semiconductor device structure 100 are illustrated. Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A and Figure 11A They are along Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 and Figure 11 A cross-sectional view of line A-A'. Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B and Figure 11B They are along Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 and Figure 11 A cross-sectional view of line B-B'.

[0144] Figure 5C , Figure 6C , Figure 7C , Figure 8C , Figure 9C , Figure 10C and Figure 11C They are along Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 and Figure 11 A cross-sectional view of the C-C' line.

[0145] Reference Figure 5 , Figure 5A , Figure 5B and Figure 5CA substrate 110 may be provided. Multiple metallization lines 130-1, 130-2, 130-3, and 130-4 (e.g., word lines) may be formed within the substrate 110 and extend in the Y direction. A gate structure 170 (e.g., a bit gate) may be formed on the substrate 110. Multiple metallization lines 120-1, 120-2, and 120-3 (e.g., bit lines) may be formed on the substrate 110 and extend in the X direction. Metallization lines 120-1, 120-2, and 120-3 may be formed on their respective gate structures 170. Multiple spacers 122-1, 122-2, 124-1, 124-2, 126-1, and 126-2 may be formed on the sidewalls of their respective metallization lines (e.g., 120-1, 120-2, and 120-3). Spacers 122-1, 122-2, 124-1, 124-2, 126-1, and 126-2 may cover the sidewalls of gate structure 170 and metallization lines 120-1, 120-2, and 120-3. A dielectric layer 182 may be formed between substrate 110 and the metallization lines (e.g., 120-1). A dielectric layer 184 may be formed on or above the metallization lines (e.g., 120-1, 120-2, and 120-3). A plurality of dielectric layers 188 may be formed on substrate 110. The dielectric layers 188 may be located between a pair of respective spacers 122-1, 122-2, 124-1, 124-2, 126-1, and 126-2. The dielectric layer may include SiN, SiO2, silicon oxynitride (SiON), silicon carbide nitride (SiCN), silicon carbide (SiC), aluminum oxide (Al2O3), hafnium oxide (HfO2), or lanthanum oxide (La2O3). In some embodiments, dielectric layer 188 may include silicon oxide. In some embodiments, each of spacers 122-1, 122-2, 124-1, 124-2, 126-1, and 126-2 may have a multilayer structure, including silicon nitride, silicon oxide, or other suitable materials. In some embodiments, the outermost layer of spacers 122-1, 122-2, 124-1, 124-2, 126-1, and 126-2 is fabricated using silicon nitride.

[0146] Please see Figure 6 , Figure 6A , Figure 6B and Figure 6C An etching process is performed. A portion of the dielectric layer 188 is removed. Portions of the dielectric layer 188 on metallization lines 130-1, 130-2, 130-3, and 130-4 can be removed. Therefore, multiple openings 188o can be formed. The upper surface of the substrate 110 can be exposed from the dielectric layer 180. Each opening 188o of the dielectric layer 188 can have a partially circular, partially elliptical, or partially elliptical profile. The etching process can include wet etching or dry etching.

[0147] Reference Figure 7 , Figure 7A , Figure 7B and Figure 7C Multiple isolation features 140-1, 140-2, 140-3, and 140-4 can be formed to fill the opening 188o of the dielectric layer 188. Each isolation feature 140-1, 140-2, 140-3, and 140-4 has a partially circular, partially elliptical, or partially elliptical outline. Each isolation feature 140-1, 140-2, 140-3, and 140-4 can overlap with its respective metallization line 130-1, 130-2, 130-3, or 130-4 along the Z-direction. Isolation features 140-1, 140-2, 140-3, and 140-4 can be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), low-pressure chemical vapor deposition (LPCVD), or other suitable processes.

[0148] Reference Figure 8 , Figure 8A , Figure 8B and Figure 8C An etching process can be performed. The remaining dielectric layer 188 can be removed. Thus, multiple apertures R1 are formed. Each aperture R1 is defined by metallization lines (e.g., 120-1, 120-2, and 120-3) (or spacers of the metallization lines) and isolation features (e.g., 140-1, 140-2, 140-3, and 140-4). Each aperture R1 may have one corner, defined by the sidewalls of the isolation features 140-1, 140-2, 140-3, and 140-4 and the sidewalls of the spacers 122-1, 122-2, 124-1, 124-2, 126-1, and 126-2. Each corner of the aperture R1 can gradually taper towards the interface between the isolation features (e.g., 140-1, 140-2, 140-3, and 140-4) and the spacers (e.g., 122-1, 122-2, 124-1, 124-2, 126-1, and 126-2). The etching process can include wet etching or dry etching.

[0149] Reference Figure 9 , Figure 9A , Figure 9B and Figure 9CA contouring material 150' can be formed to cover the upper surface of the substrate 110, the sidewalls of the spacers (e.g., 122-1, 122-2, 124-1, 124-2, 126-1, and 126-2), and the sidewalls of the isolation features (e.g., 140-1, 140-2, 140-3, and 140-4). The contouring material 150' can be conformally disposed on the upper surface of the substrate 110, the sidewalls of the spacers (e.g., 122-1, 122-2, 124-1, 124-2, 126-1, and 126-2), and the sidewalls of the isolation features (e.g., 140-1, 140-2, 140-3, and 140-4). The contouring material 150' can occupy the corners of the aperture R1. In some embodiments, the contouring material 150' can be formed by an ALD process or other suitable processes.

[0150] Reference Figure 10 , Figure 10A , Figure 10B and Figure 10C An etching process can be performed to remove a portion of the contouring material 150'. In some embodiments, the etching process may include, for example, a dry etching process.

[0151] The remaining contour-decorating material 150' forms a contour-decorating piece 150 to modify the contour of the aperture R1. Thus, a circular aperture R2 can be formed. Each contour-decorating piece 150 may have multiple segments 152-1, 152-2, 152-3, and 152-4 located at the corners of the sidewalls of the spacers (e.g., 122-1, 122-2, 124-1, 124-2, 126-1, and 126-2) and the sidewalls of the isolation features (e.g., 140-1, 140-2, 140-3, and 140-4). Each segment 152-1, 152-2, 152-3, and 152-4 of the profile modifier 150 can extend from the sidewalls of the spacers (e.g., 122-1, 122-2, 124-1, 124-2, 126-1, and 126-2) to the sidewalls of the isolation features (e.g., 140-1, 140-2, 140-3, and 140-4). Therefore, the circular aperture R2 defined by the spacers (e.g., 122-1, 122-2, 124-1, 124-2, 126-1, and 126-2), the profile modifier 150, and / or the isolation features (e.g., 140-1, 140-2, 140-3, and 140-4) can have a partially circular, partially elliptical, or partially elliptical profile.

[0152] In some embodiments, a portion of the substrate 110 may be removed, allowing the upper surface of the substrate 110 to be recessed.

[0153] refer to Figure 11 , Figure 11A , Figure 11B and Figure 11C A conductive material can be deposited to fill the circular aperture R2, thus forming a semiconductor device structure 100. Therefore, multiple contact features 160-1, 160-2, 160-3, 160-4, 160-5, and 160-6 can be formed. Each contact feature 160-1, 160-2, 160-3, 160-4, 160-5, and 160-6 can have a partially circular, partially elliptical, or partially elliptical outline.

[0154] When conductive material is filled into the circular aperture R2, few or no voids are formed at the corners of the sidewalls of the isolation features (e.g., 140-1, 140-2, 140-3, and 140-4) and the spacers (e.g., 122-1, 122-2, 124-1, 124-2, 126-1, and 126-2), thus improving the yield of the semiconductor device structure 100. In a comparative example, no contour modifiers are formed. Therefore, voids in the contact features may occur at the corners of the isolation features and spacers, adversely affecting the electrical connection.

[0155] One aspect of this disclosure provides a semiconductor device structure. The semiconductor device structure includes a first metallization line, a second metallization line, a first isolation feature, a second isolation feature, a contour modifier, and a contact feature. The first metallization line and the second metallization line extend along a first direction. The first isolation feature and the second isolation feature are disposed between the first metallization line and the second metallization line. The first metallization line, the second metallization line, the first isolation feature, and the second isolation feature define an aperture. The contour modifier is disposed within the aperture to modify the profile of the aperture in a plan view. The contact feature is disposed within the aperture.

[0156] Another aspect of this disclosure provides another semiconductor device structure. The semiconductor device structure includes a first metallization line, a second metallization line, a first isolation feature, a second isolation feature, a contour modifier, and a contact feature. The first metallization line and the second metallization line extend along a first direction. The first isolation feature and the second isolation feature are disposed between the first metallization line and the second metallization line. The first metallization line, the second metallization line, the first isolation feature, and the second isolation feature define an aperture. The contour modifier is disposed within the aperture. The contour modifier includes a plurality of mutually separated segments. Each segment is located at a corner of the aperture. The contact feature is disposed within the aperture.

[0157] Another aspect of this disclosure provides a method for fabricating a semiconductor device structure. The method includes: providing a substrate; forming a first metallization line and a second metallization line on the substrate, wherein the first metallization line and the second metallization line extend along a first direction; forming a first isolation feature and a second isolation feature between the first metallization line and the second metallization line, wherein the first metallization line, the second metallization line, the first isolation feature, and the second isolation feature define an aperture; forming a contour modifier to modify the contour of the aperture in a plan view; and forming a contact feature within the aperture.

[0158] Embodiments of this disclosure illustrate a semiconductor device structure with a contour modifier. In some embodiments, a contour modifier can be used to round the aperture to accommodate contact features, thus the contact features having a partially circular, partially elliptical, or partially elliptical contour in a plan view. When conductive material is filled into the circular aperture to form the contact features, voids can be formed or minimized, thereby increasing the yield of the semiconductor device structure.

[0159] While this disclosure and its advantages have been described in detail, it should be understood that other changes, substitutions, and alternatives may be made without departing from the spirit and scope of this disclosure as defined by the scope of the disclosed patent. For example, many of the processes described above may be implemented using different methods, and other processes or combinations thereof may be substituted for many of the processes described above.

[0160] Furthermore, the scope of this disclosure is not limited to the specific embodiments of the processes, machinery, manufacturing, material compositions, means, methods, and steps described in the specification. Those skilled in the art will understand from the content of this disclosure that existing or future processes, machinery, manufacturing, material compositions, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used in accordance with this disclosure. Accordingly, such processes, machinery, manufacturing, material compositions, means, methods, or steps are included within the scope of the patent disclosed in this disclosure.

Claims

1. A semiconductor device structure, comprising: A first metallization line and a second metallization line extend along a first direction; A first isolation feature and a second isolation feature are disposed between the first metallization line and the second metallization line, wherein the first metallization line, the second metallization line, the first isolation feature and the second isolation feature define an aperture; A contour modifier is placed within the aperture to modify the contour of the aperture in a plan view; as well as A contact feature is provided within this aperture; A first gap element is located on the sidewall of the first metallized line; and A second spacer is located on the sidewall of the second metallized line, and the aperture is defined by the first spacer, the second spacer, the first isolation feature, and the second isolation feature; The contour modifier has a first width along the first direction at the sidewall of the first gap, and a second width along the first direction between the first gap and the second gap, wherein the first width is greater than the second width.

2. The semiconductor device structure of claim 1, wherein the contour modifier rounds the contour of the aperture in a plan view.

3. The semiconductor device structure of claim 1, wherein the contour modifier is located at the corner defined by the first metallization line and the first isolation feature.

4. The semiconductor device structure of claim 1, wherein the contour modifier is disposed on the sidewall of the first metallization line.

5. The semiconductor device structure of claim 1, wherein the contour modifier is disposed on the sidewall of the first isolation feature.

6. The semiconductor device structure of claim 1, wherein the sidewalls of the first isolation feature and the sidewalls of the second isolation feature protrude from each other.

7. The semiconductor element structure of claim 1, wherein the contour modifier has a sidewall recess relative to the contact feature.

8. The semiconductor device structure of claim 1, wherein the aperture has a first width along the first direction at the sidewall of the first spacer, a second width along the first direction between the first spacer and the second spacer, and the first width is greater than the second width.

9. The semiconductor device structure of claim 1, wherein a portion of the sidewall of the first spacer is exposed from the profile modifier.

10. The semiconductor device structure of claim 1, further comprising: A third metallization line and a fourth metallization line extend along a second direction different from the first direction; The first isolation feature overlaps with the third metallization line along a third direction different from the first direction and the second direction, while the second isolation feature overlaps with the fourth metallization line along the third direction. The third metallization line overlaps with the contour modifier along the third direction.

11. A semiconductor device structure, comprising: A first metallization line and a second metallization line extend along a first direction; A first isolation feature and a second isolation feature are disposed between the first metallization line and the second metallization line, wherein the first metallization line, the second metallization line, the first isolation feature and the second isolation feature define an aperture; A profile modifier is disposed within the aperture, wherein the profile modifier comprises a plurality of mutually separated segments, each segment being located at a corner of the aperture; and A single contact feature is surrounded by these multiple segments; The first isolation feature has a sidewall protrusion relative to the contour modifier.

12. The semiconductor device structure of claim 11, wherein the plurality of segments includes a first segment that tapers toward a corner defined by the first metallization line and the first isolation feature.

13. The semiconductor device structure of claim 11, wherein the contour modifier rounds the contour of the aperture in a plan view.

14. The semiconductor device structure of claim 11, wherein the sidewall of the first isolation feature and the sidewall of the second isolation feature protrude from each other.

15. The semiconductor device structure of claim 11, further comprising: A first gap element is located on the sidewall of the first metallized line; as well as A second spacer is located on the sidewall of the second metallized line, and the aperture is defined by the first spacer, the second spacer, the first isolation feature, and the second isolation feature.

16. The semiconductor device structure of claim 15, wherein the plurality of segments includes a first segment that tapers towards the corners of the aperture and the corners of the aperture taper towards the interface between the first spacer and the first isolation feature.

17. The semiconductor device structure of claim 15, wherein the contour modifier contacts the sidewall of the first spacer.

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