Chip integration structure of inverted U-shaped silicon interposer and integration method thereof

Abstract

This invention relates to the field of chip packaging technology, specifically to a chip integration structure with an inverted U-shaped silicon interposer and its integration method. The chip integration structure with an inverted U-shaped silicon interposer includes a PCB board, characterized in that: one end of the PCB board is connected to a silicon adapter board via filler adhesive; the silicon adapter board has a groove on its side near the PCB board; a first through-hole is provided on the silicon adapter board on one side of the groove; a first conductive structure is provided within the first through-hole; a first redistribution layer is connected within the groove; several functional chip groups are provided on one side of the first redistribution layer; second conductive structures are provided on both sides of the groove; a second redistribution layer is connected on the side of the silicon adapter board away from the PCB board; logic chip groups and several functional chip groups are provided on one side of the second redistribution layer. Compared with existing technologies, using an inverted U-shaped silicon adapter board allows for the uniform bonding of heterogeneous chips on both sides of the silicon adapter board, improving the integration density and reducing the thickness of the structure.

Description

Technical Field

[0001] This invention relates to the field of chip packaging technology, specifically to a chip integration structure with an inverted U-shaped silicon interposer and its integration method. Background Technology

[0002] As product integration increases, the size of System-on-a-Chip (SoC) also grows, leading to decreased yield and increased costs. To address this issue, the industry has proposed Chiplet technology, which aims to electrically connect multiple heterogeneous chips to the outside world via a silicon interposer. The silicon interposer acts as an intermediary layer, connecting the upper and lower metal layers through its own via structure. Currently, in Chiplet technology, heterogeneous chips are integrated onto one side of the silicon interposer. Increasing the integration density requires continuously increasing the lateral area of ​​the structure, thus increasing the size of the finished chip, which does not meet the requirements for thin and lightweight chips. Summary of the Invention

[0003] To overcome the shortcomings of existing technologies, this invention provides a chip integration structure with an inverted U-shaped silicon interposer and its integration method, solving the problem of single-sided integration and increased structural area in existing Chiplet technology.

[0004] To achieve the above objectives, a chip integration structure with an inverted U-shaped silicon interposer is designed, comprising a PCB board. The PCB board is characterized in that: one end is connected to a silicon adapter board via filler adhesive; the silicon adapter board has a groove on its side near the PCB board; a first through-hole is provided on the silicon adapter board on one side of the groove; a first conductive structure is provided within the first through-hole; a first redistribution layer is connected within the groove; several functional chip groups are provided on one side of the first redistribution layer; second conductive structures are provided on both sides of the groove; a second redistribution layer is connected on the side of the silicon adapter board away from the PCB board; logic chip groups and several functional chip groups are provided on one side of the second redistribution layer.

[0005] The silicon adapter plate is in the shape of an inverted U.

[0006] The thickness of the silicon adapter plate is 250-650um, and the depth of the groove is 50-400um.

[0007] The first conductive structure forms an electrical connection with the first redistribution layer and the second redistribution layer.

[0008] One end of the second conductive structure is connected to the first rewiring layer, and the other end of the second conductive structure passes through the filler adhesive and is connected to the PCB board.

[0009] The functional chipset includes several vertically stacked functional chips. The functional chips are connected to the first redistribution layer, the second redistribution layer, and adjacent functional chips through a first adhesive layer. The first adhesive layer is provided with a first microbump. Adjacent functional chips and functional chips are electrically connected to the first redistribution layer and the second redistribution layer through the first microbump.

[0010] The functional chip includes an outermost functional chip and a relatively inner functional chip. The relatively inner functional chip has one or more second through holes, and a third conductive structure is provided in the second through hole. The third conductive structure is electrically connected to the first microbump.

[0011] The logic chipset includes a logic chip, a second adhesive layer, and a second microbump. The second redistribution layer is connected to the logic chip through the second adhesive layer. The second adhesive layer has a second microbump, and the logic chip forms an electrical connection with the second redistribution layer through the second microbump.

[0012] The present invention also provides an integration method for a chip integration structure with an inverted U-shaped silicon interposer, comprising the following steps: S1 provides a carrier; S2, forming a separation layer on the carrier; S3, a silicon adapter board is bonded to the separation layer; S4, using laser grooving or ion etching, grooves are cut on the relative first surface of the silicon adapter to form a groove, exposing the bottom and sides of the groove. S5, using laser drilling or deep reactive ion etching processes, forms the first through hole on the silicon adapter plate on one side of the bottom surface of the groove; S6, forming a first conductive structure in the first through hole; S7, A first redistribution layer is formed on the bottom surface of the groove, and the first metal layer of the first redistribution layer is electrically connected to the first conductive structure. S8, a second conductive structure is formed along the side of the groove relative to the first surface of the first redistribution layer; S9, bonding functional chipset to first surface layer relative to first redistribution layer; S10, the overall structure is inverted, the silicon adapter board is bonded to the PCB board relative to the first surface through the second conductive structure, and the silicon adapter board relative to the first surface and the PCB board are bonded together through filler glue; S11, Remove the carrier and separation layer, and form a second redistribution layer on the opposite second surface of the silicon interposer; S12, on the second redistribution layer, a logic chipset and a functional chipset are bonded relative to the first surface.

[0013] Compared with the prior art, the present invention has the following advantages: 1. This invention uses an inverted U-shaped silicon adapter plate to uniformly bond heterogeneous chips on both sides of the silicon adapter plate, which can improve the integration of the structure and reduce the thickness of the structure. 2. By evenly laying two redistribution layers on both sides of the silicon interposer, the strength of the redistribution layers can be increased, board warping can be reduced, and the accuracy of bonding between the redistribution layers and heterogeneous chips can be improved, thereby improving reliability. 3. The use of vertically connected functional chips with through holes shortens the signal propagation path, greatly improves the product's operating speed, and enhances data processing capabilities. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the structure of the present invention.

[0015] Figure 2 This is a schematic diagram of step S1 of the present invention.

[0016] Figure 3 This is a schematic diagram of step S2 of the present invention.

[0017] Figure 4 This is a schematic diagram of step S3 of the present invention.

[0018] Figure 5 This is a schematic diagram of step S4 of the present invention.

[0019] Figure 6 This is a schematic diagram of step S5 of the present invention.

[0020] Figure 7 This is a schematic diagram of step S6 of the present invention.

[0021] Figure 8 This is a schematic diagram of step S7 of the present invention.

[0022] Figure 9 This is a schematic diagram of step S8 of the present invention.

[0023] Figure 10 This is a schematic diagram of step S9 of the present invention.

[0024] Figure 11 This is a schematic diagram of step S10 of the present invention.

[0025] Figure 12 This is a schematic diagram of step S11 of the present invention.

[0026] Figure 13 This is a schematic diagram of step S12 of the present invention.

[0027] See Figures 1 to 13In this structure, 1 is the carrier, 2 is the separation layer, 3 is the silicon adapter board, 301 is the first surface of the silicon adapter board relative to the first surface, 302 is the second surface of the silicon adapter board relative to the second surface, 4 is the first through-hole, 5 is the first conductive structure, 6 is the first redistribution layer, 601 is the first redistribution layer relative to the first surface, 602 is the first redistribution layer relative to the second surface, 603 is the first metal layer, 604 is the first dielectric layer, 7 is the second conductive structure, 8 is the functional chipset, 801 is the functional chip, 802 is the first adhesive layer, 803 is the third conductive structure, 804 is the first microbump, 9 is the groove, 901 is the bottom surface of the groove, 902 is the side surface of the groove, 10 is the logic chipset, 1001 is the logic chip, 1002 is the second adhesive layer, 1003 is the second microbump, 11 is the filler adhesive, and 12 is the PCB board. Detailed Implementation

[0028] The present invention will now be further described with reference to the accompanying drawings.

[0029] like Figure 1 As shown, one end of the PCB board 12 is connected to the silicon adapter board 3 via filler glue 11. The silicon adapter board 3 has a groove 9 on the side close to the PCB board 12. The silicon adapter board 3 on the side of the groove 9 has a first through hole 4. The first through hole 4 has a first conductive structure 5. The first redistribution layer 6 is connected in the groove 302. Several functional chipsets are provided on one side of the first redistribution layer 6. Second conductive structures 7 are provided on both sides of the groove 302. The second redistribution layer 13 is connected on the side of the silicon adapter board 3 away from the PCB board 12. Logic chipsets 10 and several functional chipsets 8 are provided on one side of the second redistribution layer 13.

[0030] The silicon adapter plate 3 is inverted U-shaped.

[0031] The first conductive structure 5 forms an electrical connection with the first redistribution layer 6 and the second redistribution layer 13.

[0032] One end of the second conductive structure 7 is connected to the first redistribution layer 6, and the other end of the second conductive structure 7 passes through the filler adhesive 11 and connects to the PCB board 12. The PCB board 12 becomes the carrier for the transmission of internal electrical signals to the outside.

[0033] The functional chipset 8 includes a plurality of vertically stacked functional chips 801. The functional chips 801 are connected to the first redistribution layer 6, the second redistribution layer 13, and adjacent functional chips 801 through a first adhesive layer 802. The first adhesive layer 802 is provided with a first microbump 804. Adjacent functional chips 801 and functional chips 801 are electrically connected to the first redistribution layer 6 and the second redistribution layer 13 through the first microbump 804.

[0034] The functional chip 801 includes an outermost functional chip 801 and a relatively inner functional chip 801. The relatively inner functional chip 801 is provided with one or more second through holes. A third conductive structure 803 is provided in the second through hole. The third conductive structure 803 is electrically connected to the first micro bump 804.

[0035] The logic chipset 10 includes a logic chip 1001, a second adhesive layer 1002, and a second microbump 1003. The second redistribution layer 13 is connected to the logic chip 1001 through the second adhesive layer 1002. The second adhesive layer 1002 is provided with the second microbump 1003. The logic chip 1001 is electrically connected to the second redistribution layer 13 through the second microbump 1003.

[0036] like Figures 2 to 13 As shown, the chip integration method of the inverted U-shaped silicon interposer in this embodiment includes the following steps: S1 provides a carrier 1; S2, forming a separation layer 2 on the carrier; S3, attach the silicon adapter plate 3 to the separation layer 2; S4. Using laser grooving or ion etching, a groove is formed on the silicon adapter plate relative to the first surface 301 to form a groove 9, exposing the bottom surface 901 and the side surface 902 of the groove. S5, using laser drilling or deep reactive ion etching processes, a first through hole 4 is formed on the silicon adapter plate 3 on one side of the bottom surface 901 of the groove; S6, forming a first conductive structure 5 in the first through hole 4; S7, a first redistribution layer 6 is formed on the bottom surface 901 of the groove, and the first metal layer 603 of the first redistribution layer 6 is electrically connected to the first conductive structure 5. S8, a second conductive structure 7 is formed along the groove side 902 relative to the first surface 601 of the first redistribution layer; S9, bonding functional chipset 8 to the first surface 601 of the first redistribution layer; S10, the overall structure is inverted, and the silicon adapter board relative to the first surface 301 is bonded to the PCB board 12 through the second conductive structure 7. The silicon adapter board relative to the first surface 301 and the PCB board 12 are bonded together through the filler adhesive 11. S11, remove carrier 1 and separation layer 2, and form a second redistribution layer 13 on the opposite second surface 302 of silicon interposer; S12, on the second redistribution layer opposite to the first surface 1301, the logic chipset 10 and the functional chipset 8 are bonded.

[0037] In this invention, the first redistribution layer 6 includes a first redistribution layer relative to a first surface 601 and a first redistribution layer relative to a second surface 602, a first metal layer 603, and a first dielectric layer 604. The second redistribution layer 13 includes a second redistribution layer relative to a first surface 1301 and a second redistribution layer relative to a second surface 1302, a second metal layer 1303, and a second dielectric layer 1304. The first metal layer 603 at the first redistribution layer relative to the first surface 601 is electrically connected to the functional chipset 8 via a first microbump 804 and to the PCB board 12 via a second conductive structure 7. The first metal layer 603 at the first redistribution layer relative to the second surface 602 is electrically connected to the second metal layer 1303 at the second redistribution layer relative to the second surface 1302 via a first conductive structure 5. The second metal layer 1303 at the second redistribution layer relative to the first surface 1301 is electrically connected to the logic chipset 10 via a second microbump 1003 and to the functional chipset 8 via the first microbump 804.

[0038] The materials of the first metal layer 603 and the second metal layer 1303 are selected from one or more combinations of copper, nickel, gold, silver and titanium.

[0039] The materials of the first dielectric layer 604 and the second dielectric layer 1304 are selected from one or more combinations of polyimide, epoxy resin, silicon dioxide, and silicone.

[0040] The silicon adapter board 3 includes a silicon adapter board relative to a first surface 301 and a silicon adapter board relative to a second surface 302. The silicon adapter board relative to the first surface 301 is bonded to the PCB board 12, and the silicon adapter board relative to the second surface 302 is bonded to the second surface 1302 of the second redistribution layer.

[0041] The groove 9 includes a bottom surface 901 and a side surface 902. The bottom surface 901 is bonded to the second surface 302 of the first redistribution layer. The side surface 902 is electrically connected to the inside and outside through the attached second conductive structure 7.

[0042] The thickness of the silicon adapter plate 3 is 250-650um, the thickness of the silicon adapter plate relative to the second surface 302 to the bottom surface of the groove 901 is 200um, and the depth of the groove 302 is 50-400um.

[0043] The first conductive structure 5 is formed in the first through hole 4 by laser drilling or deep reactive ion etching on the silicon adapter plate relative to the second surface 302 to the bottom surface 901 of the groove, and then by sputtering, atomic layer deposition, electroplating or chemical plating.

[0044] The second conductive structure 7 can be a metal pillar, which can be formed on the surface of the first redistribution layer 6 by sputtering or electroplating.

[0045] The materials of the first conductive structure 5, the second conductive structure 7, and the third conductive structure 803 can be one or more combinations of copper, nickel, gold, silver, and titanium.

[0046] In the functional chipset 8, a first microbump 804 and a third conductive structure 8 are used to achieve vertical stacking connections between adjacent functional chips 801. In the logic chipset 10, a second microbump 1003 is used to achieve electrical connection with the second redistribution layer relative to the first surface 1301. The first microbump 804 and the second microbump 803 are made of solder balls.

[0047] The carrier 1 is made of one of the following materials: glass, metal, or ceramic, and can be reused. The separation layer 2 is made of adhesive tape.

[0048] This invention employs an inverted U-shaped silicon interposer board, uniformly bonding heterogeneous chips to both sides of the board, thereby improving structural integration and reducing thickness. Two redistribution layers are evenly laid on both sides of the silicon interposer board, increasing their strength, reducing board warping, and improving the accuracy of bonding between the redistribution layers and the heterogeneous chips, thus enhancing reliability. The use of functional chips with through-holes for vertical connection shortens the signal propagation path, significantly increasing product operating speed and enhancing data processing capabilities.

Claims

1. A chip integration structure with an inverted U-shaped silicon interposer, comprising a PCB board, characterized in that: One end of the PCB board (12) is connected to the silicon adapter board (3) through the filler glue (11). The silicon adapter board (3) has a groove (9) on the side close to the PCB board (12). The silicon adapter board (3) on the side of the groove (9) has a first through hole (4). The first through hole (4) has a first conductive structure (5). The first redistribution layer (6) is connected in the groove (9). Several functional chip groups are provided on one side of the first redistribution layer (6). The second conductive structure (7) is provided on both sides of the groove (9). The second redistribution layer (13) is connected on the side of the silicon adapter board (3) away from the PCB board (12). The second redistribution layer (13) has a logic chip group (10) and several functional chip groups (8) on one side.

2. The chip integration structure of the inverted U-shaped silicon interposer according to claim 1, characterized in that: The silicon adapter plate (3) is in the shape of an inverted U.

3. The chip integration structure of the inverted U-shaped silicon interposer according to claim 1 or 2, characterized in that: The thickness of the silicon adapter plate (3) is 250-650um, and the depth of the groove (9) is 50-400um.

4. The chip integration structure of the inverted U-shaped silicon interposer according to claim 1, characterized in that: The first conductive structure (5) forms an electrical connection with the first redistribution layer (6) and the second redistribution layer (13).

5. The chip integration structure of the inverted U-shaped silicon interposer according to claim 1, characterized in that: One end of the second conductive structure (7) is connected to the first redistribution layer (6), and the other end of the second conductive structure (7) passes through the filler glue (11) and is connected to the PCB board (12).

6. The chip integration structure of the inverted U-shaped silicon interposer according to claim 1, characterized in that: The functional chipset (8) includes several vertically stacked functional chips (801). The functional chips (801) are connected to the first redistribution layer (6), the second redistribution layer (13), and adjacent functional chips (801) through a first adhesive layer (802). The first adhesive layer (802) is provided with a first microbump (804). Adjacent functional chips (801) and functional chips (801) are electrically connected to each other through the first microbump (804).

7. The chip integration structure of the inverted U-shaped silicon interposer according to claim 6, characterized in that: The functional chip (801) includes an outermost functional chip (801) and a relatively inner functional chip (801). The relatively inner functional chip (801) is provided with one or more second through holes. A third conductive structure (803) is provided in the second through hole. The third conductive structure (803) is electrically connected to the first micro bump (804).

8. The chip integration structure of the inverted U-shaped silicon interposer according to claim 1, characterized in that: The logic chip group (10) includes a logic chip (1001), a second adhesive layer (1002), and a second microbump (1003). The second redistribution layer (13) is connected to the logic chip (1001) through the second adhesive layer (1002). The second adhesive layer (1002) is provided with the second microbump (1003). The logic chip (1001) is electrically connected to the second redistribution layer (13) through the second microbump (1003).

9. An integration method for a chip integration structure with an inverted U-shaped silicon interposer according to any one of claims 1 to 8, characterized in that: Includes the following steps: S1 provides a carrier (1); S2, forming a separation layer (2) on the carrier; S3, attach the silicon adapter plate (3) to the separation layer (2); S4. Using laser grooving or ion etching, a groove is formed on the silicon adapter plate relative to the first surface (301) to form a groove (9), exposing the bottom surface (901) and the side surface (902) of the groove. S5. Using laser drilling or deep reactive ion etching, a first through hole (4) is formed on the silicon adapter plate (3) on one side of the bottom surface (901) of the groove. S6, a first conductive structure (5) is formed in the first through hole (4); S7, a first redistribution layer (6) is formed on the bottom surface (901) of the groove, and the first metal layer (603) of the first redistribution layer (6) is electrically connected to the first conductive structure (5); S8, a second conductive structure (7) is formed along the sidewall (902) of the groove on the first redistribution layer opposite to the first surface (601). S9, bonding functional chipset (8) to the first surface (601) relative to the first redistribution layer. S10, the overall structure is inverted, the silicon adapter board relative to the first surface (301) is bonded to the PCB board (12) through the second conductive structure (7), and the silicon adapter board relative to the first surface (301) and the PCB board (12) are bonded together through filler glue (11); S11, remove the carrier (1) and the separation layer (2), and form a second redistribution layer (13) on the opposite second surface (302) of the silicon interposer. S12, on the second redistribution layer opposite the first surface (1301), the logic chipset (10) and the functional chipset (8) are bonded.

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