Package structure and method of forming the same

Abstract

A forming method of a packaging structure comprises: providing a transition substrate comprising a first conductive pad, and the first conductive pad is exposed to a first surface of the transition substrate; providing a device substrate comprising a passive device layer and a first redistribution layer covering the passive device layer, the passive device layer comprises a passive device, the first redistribution layer comprises a second conductive pad, the second conductive pad is electrically connected with the passive device, and the second conductive pad is exposed to a first surface of the first redistribution layer; using a hybrid bonding process to bond the transition substrate and the device substrate with the first surface of the transition substrate and the first surface of the first redistribution layer as bonding surfaces; removing part of the device substrate from a surface of the device substrate away from the transition substrate to form a groove, and the groove exposes the transition substrate or the first redistribution layer; forming a silicon bridge in the groove, and the silicon bridge comprises a third conductive pad; and mounting a functional chip on a side of the device substrate away from the transition substrate, and the functional chip is electrically connected with the third conductive pad.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of packaging, in particular to a packaging structure and a forming method thereof. BACKGROUND

[0002] With the continuous evolution of advanced packaging technology, Chiplet technology based on advanced packaging technology has become an important way to drive the improvement of design efficiency. Chiplet technology refers to a die with specific functions that can be combined and integrated. By applying System in Package (SiP) technology, different functions and different process nodes are manufactured to form a system chip through effective inter-chip interconnection and packaging architecture.

[0003] Currently, the connection by using a conversion board is one of the effective ways to realize the electrical interconnection between chips and between the chip and the substrate. However, the passive device (such as a capacitor) is not integrated in the existing conversion board, and the passive device needs to be connected with the conversion board through an additional Surface Mounted Technology (SMT) process. The flip process between the passive device and the chip and between the chip and the substrate is not matched, and the size of the passive device is large, which causes the waste of the conversion board area and is not conducive to the miniaturization of the packaging structure.

[0004] Therefore, how to realize the packaging between the passive device and the conversion board becomes the focus of research. SUMMARY

[0005] The technical problem to be solved by the present application is to provide a packaging structure and a forming method thereof, which can improve the compatibility of the packaging process and is conducive to the miniaturization of the packaging structure.

[0006] To address the aforementioned problems, the present invention provides a method for forming a packaging structure, comprising: providing an adapter substrate, the adapter substrate including a first conductive pad, the first conductive pad being exposed on a first surface of the adapter substrate; providing a device substrate, the device substrate including a passive device layer and a first redistribution layer covering the passive device layer, the passive device layer including a passive device, the first redistribution layer including a second conductive pad, the second conductive pad being electrically connected to the passive device, and the second conductive pad being exposed on the first surface of the first redistribution layer; and using the first surface of the adapter substrate and the first redistribution layer as the basis for forming the packaging structure. The first surface of the line layer is a bonding surface. A hybrid bonding process is used to bond the adapter substrate to the device substrate, wherein the first conductive pad and the second conductive pad are electrically connected. A portion of the device substrate is removed from the surface of the device substrate away from the adapter substrate to form a groove, which exposes the adapter substrate or the first redistribution layer. The area of ​​the passive device layer containing the passive device is retained. A silicon bridge is formed in the groove, and the silicon bridge includes a third conductive pad. A functional chip is mounted on the side of the device substrate away from the adapter substrate, and the functional chip is electrically connected to the third conductive pad.

[0007] In one embodiment, the adapter substrate further includes a fourth conductive pad, and the fourth conductive pad is exposed on a first surface of the adapter substrate; the device substrate further includes a first conductive post, the first conductive post being disposed within the device substrate and having one surface exposed on the first surface of the first redistribution layer; in the step of bonding the adapter substrate and the device substrate using a hybrid bonding process, the fourth conductive pad is electrically connected to the first conductive post.

[0008] In one embodiment, after the step of forming a silicon bridge in the groove, the method further includes: molding to form a molded body that fills the groove and exposes the third conductive pad to the molded body.

[0009] In one embodiment, the molding process to form a molded body includes: filling the groove with molding compound, the molding compound also covering the surface of the device substrate facing away from the adapter substrate; thinning the molding compound to remove the molding compound from the surface of the device substrate facing away from the adapter substrate and expose the third conductive pad, the remaining molding compound serving as the molded body.

[0010] In one embodiment, after the molding step to form a molded body, the method further includes: thinning the device substrate from a surface away from the adapter substrate to expose the surface of the first conductive pillar.

[0011] In one embodiment, after the step of thinning the device substrate from the surface of the device substrate away from the adapter substrate, the method further includes: planarizing the surface of the device substrate away from the adapter substrate, the surface of the molding compound, and the surface of the silicon bridge.

[0012] In one embodiment, after the step of forming the silicon bridge in the groove, the method further includes: forming a second redistribution layer, the second redistribution layer covering the surface of the device substrate away from the adapter substrate and the surface of the silicon bridge, the second redistribution layer including a fifth conductive pad electrically connected to the third conductive pad, and the fifth conductive pad being exposed on the surface of the second redistribution layer; in the step of mounting a functional chip on the side of the device substrate away from the adapter substrate, the functional chip is electrically connected to the fifth conductive pad.

[0013] In one embodiment, the second redistribution layer further includes a seventh conductive pad, which is electrically connected to the first conductive post and exposed on the surface of the second redistribution layer; during the step of mounting a functional chip on the side of the device substrate away from the adapter substrate, the functional chip is also electrically connected to the seventh conductive pad.

[0014] This invention also provides a packaging structure, including: an adapter substrate including a first conductive pad; a device substrate including a passive device layer and a first redistribution layer covering the passive device layer, the passive device layer including passive devices, the first redistribution layer being bonded to the adapter substrate, wherein the first redistribution layer includes a second conductive pad, one end of the second conductive pad being electrically connected to the passive device, and the other end being electrically connected to the first conductive pad, the device substrate having a groove exposing the adapter substrate or the first redistribution layer; a silicon bridge disposed within the groove, the silicon bridge including a third conductive pad; and a functional chip disposed on the side of the device substrate opposite to the adapter substrate, the functional chip being electrically connected to the third conductive pad.

[0015] In one embodiment, the adapter substrate further includes a fourth conductive pad, and the device substrate further includes a first conductive post that penetrates the device substrate, and the fourth conductive pad is electrically connected to the first conductive post.

[0016] In one embodiment, a second wiring layer is further included, which covers the surface of the device substrate away from the adapter substrate and the surface of the silicon bridge. The functional chip is disposed on the second wiring layer. The second wiring layer includes a fifth conductive pad, one end of which is electrically connected to the third conductive pad and the other end of which is electrically connected to the functional chip.

[0017] In one embodiment, the second redistribution layer further includes a seventh conductive pad, one end of which is electrically connected to the first conductive post and the other end of which is electrically connected to the functional chip.

[0018] In one embodiment, a molding compound is also included, which fills the groove.

[0019] In the formation method provided by this invention, passive devices are directly integrated inside the adapter substrate using wafer-level packaging technology before the functional chip is set. After integrating the passive devices, the silicon bridge is formed, thereby forming an adapter board composed of the adapter substrate and the silicon bridge. The functional chip is then electrically connected to the adapter board to form the package structure. This method eliminates the need for additional surface mount technology to connect the passive devices to the adapter board, greatly improving process compatibility. Furthermore, this method significantly saves the area of ​​the adapter substrate, which is beneficial for miniaturization of the package structure. The functional chip and the passive devices are located on the same side of the adapter substrate, resulting in a closer distance between them and improving the performance of the package structure. Additionally, the parameters of the passive devices (e.g., capacitance values) can be adjusted during the manufacturing process of the passive devices in the device substrate to achieve precise matching between the passive devices and the functional chip. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of the steps in a method for forming a packaging structure according to an embodiment of the present invention;

[0022] Figures 2A-2J This is a schematic diagram of the structure formed by the main steps of the forming method provided in an embodiment of the present invention. Detailed Implementation

[0023] The specific embodiments of the packaging structure and its formation method provided by the present invention will be described in detail below with reference to the accompanying drawings.

[0024] Figure 1 This is a schematic diagram illustrating the steps of a method for forming a packaging structure according to an embodiment of the present invention. Please refer to [link / reference]. Figure 1The forming method includes: step S10, providing an adapter substrate, the adapter substrate including a first conductive pad, and the first conductive pad being exposed on a first surface of the adapter substrate; step S11, providing a device substrate, the device substrate including a passive device layer and a first redistribution layer covering the passive device layer, the passive device layer including a passive device, the first redistribution layer including a second conductive pad, the second conductive pad being electrically connected to the passive device, and the second conductive pad being exposed on the first surface of the first redistribution layer; step S12, using the first surface of the adapter substrate and the first surface of the first redistribution layer as bonding... In step S13, a portion of the device substrate is removed from the surface of the device substrate away from the adapter substrate to form a groove, which exposes the adapter substrate or the first redistribution layer, and the area of ​​the passive device layer containing the passive device is retained; in step S14, a silicon bridge is formed in the groove, and the silicon bridge includes a third conductive pad; in step S15, a functional chip is mounted on the side of the device substrate away from the adapter substrate, and the functional chip is electrically connected to the third conductive pad.

[0025] In a method for forming a package structure according to an embodiment of the present invention, passive devices are directly integrated inside the adapter substrate using a wafer-level packaging process before the functional chip is placed. After integrating the passive devices, the silicon bridge is formed, thereby forming an adapter board composed of the adapter substrate and the silicon bridge. The functional chip is then electrically connected to the adapter board to form the package structure. This method eliminates the need for additional surface mount technology (SMT) to connect the passive devices to the adapter board, greatly improving process compatibility. Furthermore, this method significantly saves the area of ​​the adapter substrate, which is beneficial for miniaturization of the package structure. The functional chip and the passive devices are located on the same side of the adapter substrate, resulting in a closer distance between them and improving the performance of the package structure. Additionally, the parameters of the passive devices (e.g., capacitance values) can be adjusted during the manufacturing process of the passive devices in the device substrate to achieve precise matching between the passive devices and the functional chip.

[0026] Figures 2A-2J This is a schematic diagram of the structure formed by the main steps of the forming method provided in an embodiment of the present invention.

[0027] Please see Figure 1 and Figure 2A In step S10, an adapter substrate 200 is provided, the adapter substrate 200 including a first conductive pad 201, and the first conductive pad 201 is exposed on a first surface 200A of the adapter substrate 200.

[0028] In one embodiment, the adapter substrate 200 further includes a first dielectric layer 202, in which the first conductive pad 201 is formed and exposed on the top surface of the first dielectric layer 202, the top surface serving as the first surface 200A of the adapter substrate 200. The first dielectric layer 202 includes, but is not limited to, an organic dielectric layer. The material of the organic dielectric layer may be an organic resin, including but not limited to: epoxy resin (FR4), BT resin (bismaleimide triazine resin), PPE resin (polyphenylene ether resin), and PI resin (polyimide resin).

[0029] In some embodiments, the first conductive pad 201 may be a metal pad. For example, in one embodiment, the first conductive pad 201 is a copper pad.

[0030] In one embodiment, the first conductive pad 201 can penetrate the first dielectric layer 202, that is, the upper and lower surfaces of the first conductive pad 201 are exposed to the top and bottom surfaces of the first dielectric layer 202, respectively. In other embodiments, the adapter substrate 200 further includes conductive interconnects and at least one bottom conductive pad. The conductive interconnects are disposed within the first dielectric layer 202, and the first conductive pad 201 is electrically connected to the conductive interconnects. The bottom conductive pad is disposed at the bottom of the first dielectric layer 202, and the bottom conductive pad is electrically connected to the conductive interconnects, that is, the first conductive pad 201 and the bottom conductive pad are electrically connected through the conductive interconnects. The surface of the bottom conductive pad is exposed to the bottom surface of the first dielectric layer 202, serving as an external connection area at the bottom of the adapter substrate 200.

[0031] In some embodiments, the adapter substrate 200 further includes a fourth conductive pad 203, and the fourth conductive pad 203 is exposed on a first surface 200A of the adapter substrate 200. Specifically, in one embodiment, the fourth conductive pad 203 is formed within and through the first dielectric layer 202, with its upper and lower surfaces exposed on the top and bottom surfaces of the first dielectric layer 202, respectively. In other embodiments, the upper surface of the fourth conductive pad 203 is exposed on the top surface of the first dielectric layer 202, and its lower surface is also electrically connected to a bottom conductive pad via the conductive interconnect.

[0032] As an example, the present invention provides a method for forming the adapter substrate 200. The method includes: providing a carrier substrate 210; forming a sacrificial layer 211 on the carrier substrate 210; forming a first dielectric layer 202 on the sacrificial layer 211, the first dielectric layer 202 including vias; filling the vias with a conductive material to form a first conductive pad 201 and a fourth conductive pad 203. The first conductive pad 201 and the fourth conductive pad 203 are made of the same material and are formed in the same step.

[0033] In some embodiments, the formation method further includes a planarization step of the adapter substrate 200. That is, the first surface 200A of the adapter substrate 200 is planarized before performing the hybrid bonding process to improve the bonding strength of the package structure formed by subsequent hybrid bonding. The planarization process includes, but is not limited to, chemical mechanical polishing (CMP). In some embodiments, when forming the adapter substrate 200, the conductive material not only fills the vias but also covers a portion of the surface of the first dielectric layer 202. Therefore, during the planarization process, the conductive material on the surface of the first dielectric layer 202 can be removed simultaneously.

[0034] Please see Figure 1 and Figure 2B In step S11, a device substrate 220 is provided. The device substrate 220 includes a passive device layer 230 and a first redistribution layer 240 covering the passive device layer 230. The passive device layer 230 includes a passive device 231. The first redistribution layer 240 includes a second conductive pad 241. The second conductive pad 241 is electrically connected to the passive device 231 and is exposed on a first surface 240A of the first redistribution layer 240.

[0035] The passive device 231 includes, but is not limited to, resistors, capacitors, and inductors. For example, in one embodiment, the passive device 231 is a capacitor, and the passive device layer 230 is a capacitor layer, which can be obtained by fabricating a capacitor on a wafer using semiconductor processes. The capacitor includes, but is not limited to, deep trench capacitors.

[0036] The second conductive pad 241 is electrically connected to the passive device 231, serving as a pin of the passive device 231. For example, in one embodiment, the passive device 231 is a capacitor, and the second conductive pad 241 is electrically connected to the positive or negative terminal of the capacitor, serving as a pin of the positive or negative terminal of the capacitor.

[0037] In some embodiments, the first redistribution layer 240 includes a second dielectric layer 242 that covers the passive device layer 230, and a second conductive pad 241 that penetrates the second dielectric layer 242. One surface of the second conductive pad 241 is electrically connected to the passive device 231, and the other surface is exposed to the top surface of the second dielectric layer 242, which serves as the first surface 240A of the first redistribution layer 240.

[0038] In some embodiments, the second dielectric layer 242 is an organic dielectric layer, and the material of the organic dielectric layer may be an organic resin, including but not limited to: epoxy resin (FR4), BT resin (bismaleimide triazine resin), PPE resin (polyphenylene ether resin), and PI resin (polyimide resin). In some embodiments, the first dielectric layer 202 and the second dielectric layer 242 are made of the same material, which results in a stronger bond between the first dielectric layer 202 and the second dielectric layer 242 in subsequent bonding processes.

[0039] In some embodiments, the first conductive pad 201 and the second conductive pad 241 may both be metal pads, and their materials may be the same or different. For example, in one embodiment, the first conductive pad 201 and the second conductive pad 241 are made of the same material, and both are copper pads, then in the subsequent bonding process, the bonding strength of the first conductive pad 201 and the second conductive pad 241 is higher.

[0040] In one embodiment, the second conductive pad 241 extends through the second dielectric layer 242. In other embodiments, the second conductive pad 241 is disposed only in a portion of the area below the top surface of the second dielectric layer 242, and is electrically led out from the bottom surface of the second dielectric layer 242 through conductive interconnects disposed in the second dielectric layer 242. That is, the second conductive pad 241 is electrically connected to the passive device 231 through conductive interconnects.

[0041] In the forming method provided in the embodiments of the present invention, the parameters of the passive device 231 can be adjusted during the manufacturing process of the passive device 231 in the device substrate 220. For example, the capacitance value can be adjusted by changing the processing technology or adjusting the area of ​​the capacitor matrix, so that the parameters of the passive device can approach the calculated value in the simulation design, thereby achieving precise matching between the passive device 231 and the subsequently set functional chip 290.

[0042] In some embodiments, the device substrate 220 further includes a first conductive post 250, which is disposed within the device substrate 220 and has one surface exposed to the first surface 240A of the first redistribution layer 240, while its other surface is not exposed. Specifically, in one embodiment, the first conductive post 250 extends from the second dielectric layer 242 into the device substrate 220 in a direction perpendicular to the second dielectric layer 242, and one surface of the first conductive post 250 is exposed to the top surface of the second dielectric layer 242, while the other surface is located within the device substrate 220 and is not exposed.

[0043] As an example, this disclosure provides a method for forming the device substrate 220. The method includes: providing a wafer including a passive device layer 230; forming a first redistribution layer 240 on the surface of the passive device layer 230; and forming a first conductive pillar 250 extending from a first surface 240A of the first redistribution layer 240 into the passive device layer 230. The method for forming the first conductive pillar 250 includes, but is not limited to, through-silicon via (TSV) technology.

[0044] In one embodiment, the formation method further includes a planarization step of the device substrate 220. Specifically, the first surface 240A of the first redistribution layer 240 is planarized before performing the hybrid bonding process to improve the bonding strength of the package structure formed by subsequent hybrid bonding. The planarization process includes, but is not limited to, chemical mechanical polishing (CMP).

[0045] Please see Figure 1 and Figure 2C In step S12, using the first surface 200A of the adapter substrate 200 and the first surface 240A of the first redistribution layer 240 as bonding surfaces, a hybrid bonding process is used to bond the adapter substrate 200 to the device substrate 220, wherein the first conductive pad 201 and the second conductive pad 241 are electrically connected. The structure formed by the hybrid bonding process has higher current carrying capacity and better thermal performance. In some embodiments, the top surface of the first dielectric layer 202 and the top surface of the second dielectric layer 242 are also bonded together. In some embodiments, in this step, the fourth conductive pad 203 is electrically connected to the first conductive post 250.

[0046] The hybrid bonding process includes: bonding the first surface 200A of the adapter substrate 200 to the first surface 240A of the first redistribution layer 240, wherein the first dielectric layer 202 is bonded to the second dielectric layer 242; performing annealing treatment, and bonding the first conductive pad 201 to the second conductive pad 241 to form a bonding structure.

[0047] In some embodiments, prior to performing the hybrid bonding process, the method further includes: activating the first surface 200A of the adapter substrate 200 and / or the first surface 240A of the first redistribution layer 240 to form activation sites on the first surface 200A of the adapter substrate 200 and / or the first surface 240A of the first redistribution layer 240, thereby improving the bonding strength between the adapter substrate 200 and the first redistribution layer 240 during hybrid bonding. The activation process includes, but is not limited to, plasma activation. Specifically, prior to performing the bonding process, activating the first surface 200A of the adapter substrate 200 and / or the first surface 240A of the first redistribution layer 240 forms activation sites on the surfaces of the first dielectric layer 202 and / or the second dielectric layer 242, thereby improving the bonding strength between the first dielectric layer 202 and the second dielectric layer 242.

[0048] In one embodiment, both the first surface 200A of the adapter substrate 200 and the first surface 240A of the first redistribution layer 240 are activated before performing the hybrid bonding process; in another embodiment, either the first surface 200A of the adapter substrate 200 or the first surface 240A of the first redistribution layer 240 is activated before performing the bonding process.

[0049] Please see Figure 1 and Figure 2D In step S13, a portion of the device substrate 220 is removed from the surface of the device substrate 220 away from the adapter substrate 200 to form a groove 260. The groove 260 exposes the adapter substrate 200 or the first redistribution layer 240, and the area of ​​the passive device layer 230 with the passive device 231 is retained.

[0050] In this step, the area of ​​the passive device layer 230 where the passive device 231 is disposed is retained, while the area where the passive device 231 is not disposed is removed. After the passive device layer 230 is removed, the first redistribution layer 240 corresponding to the removed passive device layer 230 is also removed, thereby exposing the adapter substrate 200. The groove 260 uses the device substrate 220 as its sidewall and the adapter substrate 200 as its bottom surface. In other embodiments, only a portion of the passive device layer 230 may be removed, and the first redistribution layer 240 may not be removed, or only a portion of the first redistribution layer 240 may be removed.

[0051] Methods for removing a portion of the passive device layer 230 include, but are not limited to, etching processes. For example, in some embodiments, the method for removing a portion of the passive device layer 230 includes: forming a patterned mask layer on the surface of the device substrate 220 opposite to the transition substrate 200, the mask layer obscuring the area of ​​the passive device layer 230 where the passive device 231 is disposed and exposing the area of ​​the passive device layer 230 where the passive device 231 is not disposed; using the mask layer as a mask, etching the passive device layer 230 and the first redistribution layer 240 until the transition substrate 200 is exposed; and removing the mask layer.

[0052] Please see Figure 1 and Figure 2E In step S14, a silicon bridge 270 is formed within the groove 260. The silicon bridge 270 includes a third conductive pad 271. The silicon bridge 270 has interconnects internally, allowing functional chips 290 to achieve electrical connections between chips or within themselves via the third conductive pad 271 and the interconnect structure in the subsequently formed package structure. In this step, the silicon bridge 270 can be attached to the surface of the adapter substrate 200 using a mounting method. The third conductive pad 271 includes, but is not limited to, a copper pad.

[0053] In this step, the groove 260 can serve as a limit and alignment function, so that there is no need to form an additional groove in the adapter substrate 200 to mount the silicon bridge 270, nor is it necessary to perform a precise alignment process, thus reducing the process difficulty.

[0054] In some embodiments, the body of the silicon bridge 270 is attached to the surface of the adapter substrate 200, and the top surface of the third conductive pad 271 protrudes beyond the body of the silicon bridge 270 and beyond the surface of the device substrate 220. In other embodiments, the body of the silicon bridge 270 is attached to the surface of the adapter substrate 200, and the top surface of the third conductive pad 271 protrudes beyond the body of the silicon bridge 270 and is lower than or flush with the surface of the device substrate 220.

[0055] In some embodiments, after the step of forming the silicon bridge 270 in the groove 260, the following step is further included: See [link to documentation] Figure 2G The silicon bridge 270 is encapsulated to form an encapsulated body 272 that fills the recess 260, with the third conductive pad 271 exposed in the encapsulated body 272. The encapsulated body 272 protects and seals the silicon bridge 270.

[0056] Specifically, in one embodiment, the step of molding to form a molded body 272 includes: Please refer to Figure 2F A molding compound 300 is then filled, completely filling the groove 260 and also covering the surface of the device substrate 220 facing away from the adapter substrate 200. In this step, the molding compound 300 also covers the top surface of the third conductive pad 271. See also... Figure 2G The molding compound 300 is thinned to remove the molding compound 300 from the surface of the device substrate 220 that is away from the adapter substrate 200, exposing the third conductive pad 271. The remaining molding compound 300 serves as the molding body 272. In this step, if the top surface of the third conductive pad 271 protrudes from the surface of the device substrate 220, the third conductive pad 271 is also thinned simultaneously when the molding compound 300 is thinned.

[0057] Please see Figure 2H In some embodiments, after forming the molding compound 272, the method further includes thinning the device substrate 220 from the surface of the device substrate 220 away from the adapter substrate 200 to expose the surface of the first conductive post 250. In this step, chemical mechanical polishing (CMP) or mechanical polishing processes can be used to thin the device substrate 220.

[0058] In some embodiments, after the step of thinning the device substrate 220 from the surface of the device substrate 220 away from the adapter substrate 200, the method further includes: planarizing the surface of the device substrate 220 away from the adapter substrate 200, the surface of the molding compound 272, and the surface of the silicon bridge 270, in order to provide a flat surface for subsequent formation of other structures. The planarization process includes, but is not limited to, chemical mechanical polishing.

[0059] Please see Figure 2I In some embodiments, after forming the silicon bridge 270 within the groove 260, the method further includes forming a second redistribution layer 280. The second redistribution layer 280 covers the surface of the device substrate 220 opposite to the adapter substrate 200 and the surface of the silicon bridge 270. The second redistribution layer 280 includes a fifth conductive pad 281 electrically connected to the third conductive pad 271, and the fifth conductive pad 281 is exposed on a first surface 280A of the second redistribution layer 280. In some embodiments, if the molding compound 272 covers the surface of the silicon bridge 270, then the second redistribution layer 280 also covers the surface of the molding compound 272. The fifth conductive pad 281 may be a metal pad, such as a copper pad.

[0060] In some embodiments, the second redistribution layer 280 includes a third dielectric layer 282, wherein the fifth conductive pad 281 is formed within the third dielectric layer 282 and exposed on the top surface of the third dielectric layer 282, which serves as a first surface 280A of the second redistribution layer 280. The third dielectric layer 282 includes, but is not limited to, an organic dielectric layer. The material of the organic dielectric layer may be an organic resin, including but not limited to: epoxy resin (FR4), BT resin (bismaleimide triazine resin), PPE resin (polyphenylene ether resin), and PI resin (polyimide resin).

[0061] In one embodiment, the fifth conductive pad 281 can penetrate the third dielectric layer 282, meaning that the upper and lower surfaces of the fifth conductive pad 281 are exposed to the top and bottom surfaces of the third dielectric layer 282, respectively. In other embodiments, the second redistribution layer 280 further includes a conductive interconnect 283. The conductive interconnect 283 is disposed within the third dielectric layer 282, and one end of the fifth conductive pad 281 is electrically connected to the conductive interconnect 283, while the other end of the conductive interconnect 283 is electrically connected to the third conductive pad 271, meaning that the fifth conductive pad 281 and the third conductive pad 271 are electrically connected through the conductive interconnect 283.

[0062] In some embodiments, the second redistribution layer 280 further includes a seventh conductive pad 284, which is electrically connected to the first conductive post 250 and exposed on the surface of the second redistribution layer 280. The seventh conductive pad 284 may be a metal pad, such as a copper pad. In some embodiments, the seventh conductive pad 284 may penetrate the third dielectric layer 282, meaning that the upper and lower surfaces of the seventh conductive pad 284 are exposed on the top and bottom surfaces of the third dielectric layer 282, respectively. In other embodiments, the seventh conductive pad 284 is electrically connected to one end of the conductive interconnect 283, and the other end of the conductive interconnect 283 is electrically connected to the first conductive post 250, meaning that the seventh conductive pad 284 and the first conductive post 250 are electrically connected through the conductive interconnect 283.

[0063] In some embodiments, during the step of forming the second redistribution layer 280, multiple redistribution processes may be performed to form the conductive interconnect 283, the fifth conductive pad 281, and the seventh conductive pad 284.

[0064] Please see Figure 1 and Figure 2J In step S15, a functional chip 290 is mounted on the side of the device substrate 220 opposite to the adapter substrate 200. The functional chip 290 is electrically connected to the third conductive pad 271, thereby forming the package structure.

[0065] In the packaging structure, the functional chip 290 and the passive device 231 are disposed on the same side of the adapter substrate 200, so that the passive device 231 and the functional chip 290 are closer together, thereby improving the performance of the packaging structure.

[0066] In some embodiments, the functional chip 290 is disposed on the first surface 280A of the second redistribution layer 280 and electrically connected to the fifth conductive pad 281, and electrically connected to the third conductive pad 271 through the fifth conductive pad 281. Further, the functional chip 290 is also electrically connected to the seventh conductive pad 284, and electrically connected to the first conductive post 250 through the seventh conductive pad 284.

[0067] The functional chip 290 may be one or more, all of which are disposed on the first surface of the second redistribution layer 280. The conductive pads of the functional chip 290 facing the device substrate 220 are electrically connected to the fifth conductive pad 281 and the seventh conductive pad 284. In some embodiments, a flip-chip process can be used to electrically connect the functional chip 290 to the fifth conductive pad 281 and the seventh conductive pad 284. It is understood that the conductive pads of different functional chips 290 can be electrically connected through the silicon bridge 270, and the conductive pads of the functional chip 290 can be electrically connected to the adapter substrate 200 through the first conductive post 250.

[0068] In some embodiments, after the step of mounting the functional chip 290, a step of forming a molding compound 291 is further included, the molding compound 291 covering the functional chip 290 and filling the gap between the functional chip 290 and the second redistribution layer 280 to seal and support the functional chip 290.

[0069] The packaging structure formation method provided in this embodiment of the invention eliminates the need for additional surface mount technology (SMT) to connect the passive device 231 to the adapter board, greatly improving process compatibility. Furthermore, this formation method significantly reduces the area of ​​the adapter substrate 200, which is beneficial for miniaturization of the packaging structure. Additionally, the parameters of the passive device 231 (e.g., the capacitance value) can be adjusted during the manufacturing process of the passive device 231 in the device substrate 220 to achieve precise matching between the passive device 231 and the functional chip 290.

[0070] The present invention also provides a packaging structure formed using the above-described forming method.

[0071] Please see Figures 2A-2J The packaging structure includes: an adapter substrate 200, including a first conductive pad 201; a device substrate 220, including a passive device layer 230 and a first redistribution layer 240 covering the passive device layer 230, the passive device layer 230 including a passive device 231, the first redistribution layer 240 being bonded to the adapter substrate 200, wherein the first redistribution layer 240 includes a second conductive pad 241, one end of the second conductive pad 241 being electrically connected to the passive device 231, and the other end being electrically connected to the first conductive pad 201, the device substrate 220 having a groove 260 exposing the adapter substrate 200; a silicon bridge 270 disposed within the groove 260, the silicon bridge 270 including a third conductive pad 271; and a functional chip 290 disposed on the side of the device substrate 220 opposite to the adapter substrate 200, and the functional chip 290 being electrically connected to the third conductive pad 271.

[0072] In the packaging structure provided by this embodiment of the invention, the adapter substrate 200 and the silicon bridge 270 constitute an adapter board, and the passive device 231 is integrated inside the adapter board, which greatly saves the area of ​​the adapter board and is conducive to the miniaturization of the packaging structure; the functional chip 290 and the passive device 231 are disposed on the same side of the adapter board, so that the passive device 231 and the functional chip 290 are close to each other, which improves the performance of the packaging structure; and the passive device 231 and the functional chip 290 can be precisely matched.

[0073] In some embodiments, the adapter substrate 200 further includes a first dielectric layer 202, in which the first conductive pad 201 is formed. The first dielectric layer 202 includes, but is not limited to, an organic dielectric layer. The first conductive pad 201 may be a metal pad. For example, in one embodiment, the first conductive pad 201 is a copper pad.

[0074] In one embodiment, the first conductive pad 201 may penetrate the first dielectric layer 202. In other embodiments, the adapter substrate 200 further includes conductive interconnects and at least one bottom conductive pad. The conductive interconnects are disposed within the first dielectric layer 202, and the first conductive pad 201 is electrically connected to the conductive interconnects. The bottom conductive pad is disposed at the bottom of the first dielectric layer 202, and the bottom conductive pad is electrically connected to the conductive interconnects; that is, the first conductive pad 201 and the bottom conductive pad are electrically connected through the conductive interconnects, and the bottom conductive pad serves as an external connection area at the bottom of the adapter substrate 200.

[0075] The passive device 231 includes, but is not limited to, resistors, capacitors, and inductors. For example, in one embodiment, the passive device 231 is a capacitor, and the passive device layer 230 is a capacitor layer, the capacitor including, but not limited to, deep trench capacitors. The second conductive pad 241 is electrically connected to the passive device 231, serving as a pin of the passive device 231.

[0076] The first redistribution layer 240 is disposed between the adapter substrate 200 and the passive device layer 230. In some embodiments, the first redistribution layer 240 includes a second dielectric layer 242, which is disposed between the adapter substrate 200 and the passive device layer 230, and the second conductive pad 241 penetrates the second dielectric layer 242. In other embodiments, the second conductive pad 241 is disposed only in a portion below the top surface of the second dielectric layer 242, and is electrically led out from the bottom surface of the second dielectric layer 242 through conductive interconnects disposed in the second dielectric layer 242, that is, the second conductive pad 241 is electrically connected to the passive device 231 through conductive interconnects.

[0077] In some embodiments, the second dielectric layer 242 is an organic dielectric layer, and the second conductive pad 241 is a metal pad. In some embodiments, the first dielectric layer 202 and the second dielectric layer 242 are made of the same material, and the first conductive pad 201 and the second conductive pad 241 are made of the same material, so as to improve the bonding strength between the first redistribution layer 240 and the adapter substrate 200.

[0078] In some embodiments, the adapter substrate 200 further includes a fourth conductive pad 203, and the device substrate 220 further includes a first conductive post 250, the first conductive post 250 penetrating the device substrate 220, and the fourth conductive pad 203 being electrically connected to the first conductive post 250.

[0079] In some embodiments, the groove 260 uses the device substrate 220 as a sidewall and the adapter substrate 200 as a bottom surface. In other embodiments, the groove 260 uses the device substrate 220 as a sidewall and the first redistribution layer 240 as a bottom surface. The silicon bridge 270 is disposed on the surface of the adapter substrate 200 or the first redistribution layer 240.

[0080] In some embodiments, the encapsulation structure further includes a molding compound 272 that fills the groove 260 and covers the silicon bridge 270 to protect and seal the silicon bridge 270. The molding compound 272 also covers the side of the third conductive pad 271 to support and protect the third conductive pad 271.

[0081] In some embodiments, the packaging structure further includes a second redistribution layer 280, which covers the surface of the device substrate 220 opposite to the adapter substrate 200 and the surface of the silicon bridge 270. The functional chip 290 is disposed on the second redistribution layer 280. The second redistribution layer 280 includes a fifth conductive pad 281, one end of which is electrically connected to the third conductive pad 271, and the other end of which is electrically connected to the functional chip 290. In some embodiments, the second redistribution layer 280 further includes a seventh conductive pad 284, one end of which is electrically connected to the first conductive post 250, and the other end of which is electrically connected to the functional chip 290.

[0082] There may be one or more functional chips 290. The conductive pads of different functional chips 290 can be electrically connected through the silicon bridge 270. The conductive pads of the functional chips 290 can be electrically connected to the adapter substrate 200 through the first conductive post 250.

[0083] In some embodiments, the packaging structure further includes a molding compound 291, which covers the functional chip 290 and fills the gap between the functional chip 290 and the second redistribution layer 280 to seal and support the functional chip 290.

[0084] The packaging structure provided by the embodiments of the present invention can greatly save the area of ​​the adapter board, which is conducive to the miniaturization of the packaging structure; in addition, the passive device 231 and the functional chip 290 are close to each other, which improves the performance of the packaging structure. At the same time, the passive device 231 and the functional chip 290 can be precisely matched.

[0085] It should be noted that the terms "comprising" and "having," and their variations, used in this invention document are intended to cover non-exclusive inclusion. The terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence, unless explicitly indicated by the context; it should be understood that such use of data can be interchanged where appropriate. The term "one or more" depends at least in part on the context and can be used to describe features, structures, or characteristics in a singular sense, or in a plural sense to describe combinations of features, structures, or characteristics. The term "based on" can be understood as not necessarily intended to express an exclusive set of factors, but can instead, also at least in part on the context, allow for the presence of other factors that are not necessarily explicitly described. Furthermore, embodiments and features in embodiments of this invention can be combined with each other without conflict. In addition, descriptions of well-known components and technologies have been omitted in the above description to avoid unnecessarily obscuring the concepts of this invention. In the various embodiments described above, each embodiment focuses on its differences from other embodiments; similar / identical parts between embodiments can be referred to mutually.

[0086] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for forming an encapsulation structure, characterized in that, include: An adapter substrate is provided, the adapter substrate including a first conductive pad, and the first conductive pad being exposed on a first surface of the adapter substrate; A device substrate is provided, the device substrate including a passive device layer and a first redistribution layer covering the passive device layer, the passive device layer including a passive device, the first redistribution layer including a second conductive pad, the second conductive pad being electrically connected to the passive device, and the second conductive pad being exposed on a first surface of the first redistribution layer. Using the first surface of the adapter substrate and the first surface of the first redistribution layer as bonding surfaces, a hybrid bonding process is used to bond the adapter substrate to the device substrate, wherein the first conductive pad and the second conductive pad are electrically connected. A portion of the device substrate is removed from the surface of the device substrate away from the adapter substrate to form a groove, the groove exposing the adapter substrate or the first redistribution layer, and the area of ​​the passive device layer containing the passive device is retained; A silicon bridge is formed within the groove, the silicon bridge including a third conductive pad; A functional chip is mounted on the side of the device substrate opposite to the adapter substrate, and the functional chip is electrically connected to the third conductive pad.

2. The method for forming the packaging structure according to claim 1, characterized in that, The adapter substrate further includes a fourth conductive pad, and the fourth conductive pad is exposed on the first surface of the adapter substrate; the device substrate further includes a first conductive post, which is disposed in the device substrate and one surface of which is exposed on the first surface of the first redistribution layer. In the step of bonding the adapter substrate to the device substrate using a hybrid bonding process, the fourth conductive pad is electrically connected to the first conductive post.

3. The method for forming the packaging structure according to claim 2, characterized in that, The step of forming a silicon bridge within the groove further includes: molding to form a molded body that fills the groove and exposes the third conductive pad to the molded body.

4. The method for forming the packaging structure according to claim 3, characterized in that, The steps of molding to form a molded body include: A molding compound is filled to completely fill the groove, and the molding compound also covers the surface of the device substrate facing away from the adapter substrate; The molding compound is thinned to remove the molding compound from the surface of the device substrate facing away from the adapter substrate and expose the third conductive pad, with the remaining molding compound serving as the molding body.

5. The method for forming the packaging structure according to claim 3, characterized in that, The molding process, after forming a molded body, further includes: thinning the device substrate from the surface of the device substrate away from the adapter substrate to expose the surface of the first conductive pillar.

6. The method for forming the packaging structure according to claim 5, characterized in that, After the step of thinning the device substrate from the surface away from the adapter substrate, the method further includes: planarizing the surface of the device substrate away from the adapter substrate, the surface of the molding compound, and the surface of the silicon bridge.

7. The method for forming the packaging structure according to any one of claims 2 to 6, characterized in that, After the step of forming the silicon bridge in the groove, the method further includes: forming a second redistribution layer, the second redistribution layer covering the surface of the device substrate away from the adapter substrate and the surface of the silicon bridge, the second redistribution layer including a fifth conductive pad, the fifth conductive pad being electrically connected to the third conductive pad, and the fifth conductive pad being exposed on the surface of the second redistribution layer. In the step of mounting a functional chip on the side of the device substrate opposite to the adapter substrate, the functional chip is electrically connected to the fifth conductive pad.

8. The method for forming the packaging structure according to claim 7, characterized in that, The second redistribution layer further includes a seventh conductive pad, which is electrically connected to the first conductive post and is exposed on the surface of the second redistribution layer. In the step of mounting a functional chip on the side of the device substrate away from the adapter substrate, the functional chip is also electrically connected to the seventh conductive pad.

9. A packaging structure, characterized in that, include: The adapter substrate includes a first conductive pad; A device substrate includes a passive device layer and a first redistribution layer covering the passive device layer. The passive device layer includes passive devices. The first redistribution layer is bonded to the adapter substrate. The first redistribution layer includes a second conductive pad. One end of the second conductive pad is electrically connected to the passive device, and the other end is electrically connected to the first conductive pad. The device substrate has a groove that exposes the adapter substrate or the first redistribution layer. A silicon bridge is disposed within the groove, the silicon bridge including a third conductive pad; A functional chip is disposed on the side of the device substrate opposite to the adapter substrate, and the functional chip is electrically connected to the third conductive pad.

10. The packaging structure according to claim 9, characterized in that, The adapter substrate further includes a fourth conductive pad, and the device substrate further includes a first conductive post, which penetrates the device substrate, and the fourth conductive pad is electrically connected to the first conductive post.

11. The packaging structure according to claim 10, characterized in that, It also includes a second wiring layer, which covers the surface of the device substrate away from the adapter substrate and the surface of the silicon bridge. The functional chip is disposed on the second wiring layer. The second wiring layer includes a fifth conductive pad, one end of which is electrically connected to the third conductive pad and the other end of which is electrically connected to the functional chip.

12. The packaging structure according to claim 11, characterized in that, The second redistribution layer also includes a seventh conductive pad, one end of which is electrically connected to the first conductive post and the other end of which is electrically connected to the functional chip.

13. The packaging structure according to any one of claims 9 to 12, characterized in that, It also includes a molding compound that fills the groove.

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