Soft-controllable pwm carrier control with hardware current limiting

Abstract

The application discloses a soft controllable PWM carrier control of hardware current limiting and relates to the technical field of instantaneous large current suppression of a motor driver. The application comprises the following steps: S1: through a program, according to the margin of each module, a current point Curr_Limit2 at which a module is automatically turned on in a hardware current limiting process is set by software, and the current point is smaller than a hardware current limiting point Curr_Limit controlled by hardware; S2: in a 3KHz frequency interruption program, a motor driver detects a hardware current limiting state square wave signal OCPWM2 in a running state in real time, and confirms whether hardware has entered a hardware current limiting state; and S3: when the hardware current limiting square wave signal OCPWM2 is valid, it is confirmed that the hardware current limiting state has been entered, and a module total blocking signal Drive opened in the running state is closed. The application is different from the prior art in that after hardware current limiting, a soft controllable PWM carrier control of hardware current limiting is used to prevent damage control of a module in the process of hardware current limiting, to accurately protect the module, and to not affect the rapidity of hardware current limiting.

Description

Technical Field

[0001] This invention relates to the field of instantaneous high current suppression technology for motor drivers, specifically to soft-controllable PWM carrier control with hardware current limiting. Background Technology

[0002] In the field of motor driver control, it is common for motor drivers to experience large inrush currents due to excessively short acceleration / deceleration times, sudden load changes, or inappropriate software performance control. Hardware current limiting is a commonly used method to control this inrush current. In current solutions, once hardware current limiting is activated, a continuous on / off square wave counter is used to count the current. When the count reaches its limit, the motor driver completely cuts off the output, shuts down the module, and reports a fault to prevent module damage.

[0003] However, there are several uncertainties in the existing solutions:

[0004] 1) Hardware current limiting is entirely implemented by hardware circuitry. The rise and fall slopes of the current after hardware current limiting are related to the actual inductance of the motor. For example, if the inductance is very small, the rise and fall slopes after hardware current limiting may be close to the current slope formed by the hardware circuit's filtering. Due to the rapid turn-off of hardware current limiting, the hardware filtering will be very small, resulting in the carrier frequency of the OCPWM on / off signal of this control module potentially being around 16kHz or higher. In this case, the hardware automatically turns on and off, formed by the hardware comparison circuit. The hardware current limiting reference point Curr_Limit is fixed. When CurrAd is greater than Curr_Limit, OCPWM1 is high to control the module to turn off; when CurrAd is less than Curr_Limit, OCPWM1 is low to control the module to turn on. The hardware filtering between OCPWM1 and the module is only a few tens of microseconds due to the need for speed. When the motor inductance is very small, the carrier frequency of the OCPWM1 on / off square wave signal may reach up to around 16kHz.

[0005] 2) Because the current rise and fall slope after hardware current limiting is related to the motor inductance, there will be timing errors in the continuous counting of the OCPWM2 judgment of the effective current limiting state after hardware current limiting. This is because the effective counting of hardware current limiting is performed in software, and the hardware current limiting counting is performed by software detecting the on / off square wave signal generated by the current limiting. This square wave signal is automatically generated by the hardware after 1ms filtering. Therefore, it may not be possible to synchronize the software effective counting with the square wave signal, and some square waves may be missed, causing the time for judging the effective state of hardware current limiting to be artificially lengthened. The software detection intervals Time1 and Time2 between software detection time 1, software detection time 2, and software detection time 3 are timed in the main loop and will not differ due to different motor inductance. In the main loop, Time1 and Time2 are approximately a few milliseconds. However, Figure 2 The frequency period of the square wave signal OCPWM2 varies with the motor inductance, with a minimum period of 2ms. Just like... Figure 2 In the scenario described, no valid square waves for the hardware current limiting were detected at software detection moments 2 and 3, resulting in the loss of one valid square wave. If the overall hardware current limiting validity count requires 50 valid square waves, the actual number of valid square waves generated could reach 60 or more. This would increase the actual detection time.

[0006] 3) Currently, in order to control the duration of hardware current limiting, a timer is set to keep the hardware current limiting active. When the timer expires, the motor driver completely cuts off the output, shuts down the module, and reports a fault.

[0007] A) Due to the extended timeframe mentioned in 2), the module may be damaged due to prolonged hardware current limiting before the fault is reported.

[0008] B) Even for the same module, the OCPWM carrier frequency is different due to the different current slope in 1) after hardware current limiting, which in turn leads to different switching frequencies of the OCPWM1 module with hardware current limiting. Due to switching losses, the duration of continuous hardware current limiting that the module can withstand is also different.

[0009] C) Due to reasons mentioned in A) and B), to protect the module, the duration that the hardware current limit can withstand cannot be too long. However, it also cannot be too short, otherwise the OCPM signal will be frequently triggered after the hardware current limit is applied, falsely reporting a hardware current limit fault, thus failing to meet the original purpose of hardware current limiting. The original purpose of hardware current limiting is to suppress instantaneous inrush current and allow the motor driver to continue operating normally. Summary of the Invention

[0010] The purpose of this invention is to provide hardware-limited, softly controllable PWM carrier control to solve the problems mentioned in the background art.

[0011] To achieve the above objectives, the present invention provides the following technical solution: hardware current-limited soft-controllable PWM carrier control, comprising the following steps:

[0012] S1: Through the program, based on the margin of each module, the software sets the current point Curr_Limit2 that the module will automatically turn on during the hardware current limiting process. This current point is less than the hardware current limiting point Curr_Limit controlled by the hardware.

[0013] S2: In the 3KHz frequency interrupt routine, the motor driver detects the hardware current limiting status square wave signal OCPWM2 in real time during operation to confirm whether the hardware has entered the hardware current limiting state.

[0014] S3: When the hardware current limiting square wave signal OCPWM2 is valid, it is confirmed that the hardware current limiting state has been entered, and the module total blocking signal Drive, which is enabled in the running state, is turned off.

[0015] S4: In the 3KHz frequency interrupt routine, and when the hardware current limiting status signal OCPWM2 is valid, the current maximum value of the three-phase current is detected in real time;

[0016] S5: Determine the relationship between the maximum value of the three-phase current and the current point Curr_Limit2 that the module automatically turns on;

[0017] S6: Repeat the process of S2-S5 to form the PWM waveform for the on / off switching of the OCPWM1 control module with a maximum carrier frequency of 3KHz.

[0018] Furthermore, determining the relationship between the maximum three-phase current and the current point Curr_Limit2 that the module automatically turns on includes the following steps:

[0019] If the maximum three-phase current is less than the module's automatic current limit Curr_Limit2, the module's total blocking signal Driver will be turned on. This is because the hardware current limiting switch signal OCPWM1 will be turned on at this time because the real-time maximum three-phase current is less than the module's hardware current limit Curr_Limit. Therefore, the motor driver current will start to rise.

[0020] Furthermore, determining the relationship between the maximum three-phase current and the current point Curr_Limit2 that the module automatically turns on includes the following steps:

[0021] If the maximum three-phase current is greater than the current point Curr_Limit2 at which the module automatically turns on, the module's total blocking signal Driver will continue to turn off, and the module will also continue to turn off. At this time, the current will continue to decrease until the maximum three-phase current is less than the current point Curr_Limit2 at which the module automatically turns on.

[0022] Compared with the prior art, the beneficial effects of the present invention are:

[0023] The difference between this hardware current limiting soft-controllable PWM carrier control and existing technologies is that after hardware current limiting, the soft-controllable PWM carrier control prevents the module from being damaged during the hardware current limiting process, accurately protects the module in terms of timing, and does not affect the speed of hardware current limiting. Attached Figure Description

[0024] Figure 1 This is a circuit diagram of the present invention;

[0025] Figure 2 This is a schematic diagram of the cycle of the present invention. Detailed Implementation

[0026] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0027] like Figures 1-2 As shown, the present invention provides a technical solution: hardware current limiting soft controllable PWM carrier control.

[0028] Among them, reference Figure 1 As can be seen, this application, after hardware current limiting, uses soft-controllable PWM carrier control of hardware current limiting to prevent damage to the module during the hardware current limiting process, accurately protects the module in terms of timing, and does not affect the speed of hardware current limiting.

[0029] It should be emphasized that the main point of this application is that a software control module has been added to the on / off signal of the hardware current limiting control module, including the total blocking signal Drive signal and how to control the Drive signal. This total blocking signal Drive signal is generally existing in motor drivers.

[0030] Working Principle: In the hardware current limiting process, this invention adds software control to the automatic hardware current limiting control. First, a current point Curr_Limit2 for automatic module turn-on is set via software; this Curr_Limit2 must be less than Curr_Limit. The overall module blocking signal Drive is then introduced. When the software first detects the hardware current limiting square wave OCPWM2 signal, it simultaneously turns off the overall module blocking signal Drive. At this point, the motor driver is in a fully current-limited state, the module is blocked, and the current decreases. Since the hardware current limiting comparator is entirely hardware-controlled, as long as the current limit is less than the hardware current limit point Curr_Limit, the hardware current limiting blocking circuit will automatically open. Because the overall module blocking signal controlled by the software has not yet been opened, the module remains blocked, and the current continues to decrease until it reaches the module's automatic turn-on current point Curr_Limit2. Once the current drops to Curr_Limit2, the overall module blocking signal Drive controlled by the software opens, the module turns on, and the current rises again. The above-mentioned detection of whether the current has reached the automatic turn-on current point Curr_Limit2 of the module is performed, for example, in a 3KHz frequency interrupt. The specific frequency of the interrupt varies depending on the different modules' tolerance to the hardware current limiting point. The software can automatically select the frequency in the program according to the different modules. This invention uses a 3KHz frequency interrupt as an example. That is to say, after entering the hardware current limiting, the maximum carrier frequency of the OCPWM1 square wave PWM wave interrupted by the hardware current limiting is 3KHz. This solves the problem of the dangerous carrier wave that can damage the module due to the different current slope of the hardware current limiting caused by different motor inductances, which can reach a maximum module switching carrier frequency of 16KHz. The signal processing for detecting OCPWM2 is also performed in a 3KHz frequency interrupt. In this way, the period of detecting OCPWM2 is much smaller than the 2MS period of the OCPWM2 square wave, avoiding false alarms of hardware current limiting faults. Specifically, as shown in the figure... Figure 2 As shown.

[0031] Time1, Time2, and Time3 are all period values ​​with a frequency of 3kHz. The square wave signal OCPWM2 used by the control module to switch on and off during the process has a period of 2ms. The frequency of the detection time is much higher than the frequency of OCPWM2, so that valid square waves will not be lost.

[0032] By controlling the module's switching carrier through software-intervention and pure hardware current limiting, and using a soft-controllable PWM carrier, damage to the module can be effectively prevented from caused by large instantaneous inrush currents due to short acceleration / deceleration intervals or sudden load changes.

[0033] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended embodiments and their equivalents.

Claims

1. Hardware-limited, soft-controllable PWM carrier control, characterized in that, Includes the following steps: S1: Through the program, based on the margin of each module, the software sets the current point Curr_Limit2 that the module will automatically turn on during the hardware current limiting process. This current point is less than the hardware current limiting point Curr_Limit controlled by the hardware. S2: In the 3KHz frequency interrupt routine, the motor driver detects the hardware current limiting status square wave signal OCPWM2 in real time during operation to confirm whether the hardware has entered the hardware current limiting state. S3: When the hardware current limiting square wave signal OCPWM2 is valid, it is confirmed that the hardware current limiting state has been entered, and the module total blocking signal Drive, which is enabled in the running state, is turned off. S4: In the 3KHz frequency interrupt routine, and when the hardware current limiting status signal OCPWM2 is valid, the current maximum value of the three-phase current is detected in real time; S5: Determine the relationship between the maximum value of the three-phase current and the current point Curr_Limit2 that the module automatically turns on; S6: Repeat the process of S2-S5 to form the PWM waveform for the on / off switching of the OCPWM1 control module with a maximum carrier frequency of 3KHz. The determination of the relationship between the maximum value of the three-phase current and the current point Curr_Limit2 at which the module automatically turns on includes the following steps: If the maximum three-phase current is less than the module's automatic current-limiting point Curr_Limit2, the module's overall blocking signal Driver is activated. This is because the hardware current-limiting switch signal OCPWM1 is activated at this time because the real-time maximum three-phase current is less than the module's hardware current-limiting point Curr_Limit. Therefore, the motor driver current will start to rise. The determination of the relationship between the maximum three-phase current and the module's automatic current-limiting point Curr_Limit2 includes the following steps: If the maximum three-phase current is greater than the current point Curr_Limit2 at which the module automatically turns on, the module's total blocking signal Driver will continue to turn off, and the module will also continue to turn off. At this time, the current will continue to decrease until the maximum three-phase current is less than the current point Curr_Limit2 at which the module automatically turns on.

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