Power conversion device

Abstract

An embodiment of the present application relates to a power conversion device including: a plurality of semiconductor elements connected in parallel with each other; a plurality of gate drivers corresponding to the plurality of semiconductor elements, respectively, which supply a drive voltage to the corresponding semiconductor elements, respectively; and a control section which supplies a gate command corresponding to the drive voltage to the plurality of gate drivers based on a carrier, and the plurality of semiconductor elements are set to an on state at different timings from each other in an operation period.

Description

Technical Field

[0001] Embodiments of the present invention relate to a power conversion device. Background Technology

[0002] Power conversion devices are supplied to various devices and systems for a variety of applications. The conversion capacity of power conversion devices is increasing in response to market demands. To increase conversion capacity, it is desirable to increase the current capacity of the semiconductor elements required for power conversion. Sometimes, simply replacing the semiconductor elements within the power conversion device with those having higher rated current is sufficient. However, in cases where simply replacing the semiconductor elements is insufficient, it is necessary to increase the overall rated current of the power conversion device by connecting multiple semiconductor elements in parallel or by connecting multiple power conversion units in parallel. Summary of the Invention

[0003] One aspect of the power conversion device of the present invention includes: a plurality of semiconductor elements connected in parallel; a plurality of gate drivers corresponding to the plurality of semiconductor elements and supplying driving voltages to the corresponding semiconductor elements; and a control unit that, based on a carrier wave, supplies gate commands corresponding to the driving voltages to the plurality of gate drivers, wherein the plurality of semiconductor elements are set to an on state at different timings during operation of the plurality of semiconductor elements.

[0004] Another aspect of the power conversion device of the present invention includes a plurality of power conversion units connected in parallel with each other, wherein the plurality of power conversion units each include: a semiconductor element; a gate driver that supplies a driving voltage to the semiconductor element; and a control unit that supplies a gate command corresponding to the driving voltage to the gate driver based on a carrier wave, wherein the semiconductor element is set to an on state at different timings during the operation of the semiconductor element. Attached Figure Description

[0005] Figure 1 This is a circuit diagram showing an example of the configuration of the power conversion device according to the first embodiment.

[0006] Figure 2 This is a waveform diagram illustrating an example of the operation of the power conversion device according to the first embodiment.

[0007] Figure 3 This is a circuit diagram showing an example of the configuration of the power conversion device according to the second embodiment.

[0008] Figure 4 This is a waveform diagram illustrating an example of the operation of the power conversion device according to the second embodiment.

[0009] Figure 5 This is a circuit diagram illustrating a modified example of the power conversion device according to the embodiment.

[0010] Figure 6 This is a waveform diagram showing a variation of the power conversion device according to the embodiment. Detailed Implementation

[0011] Reference Figures 1 to 6 The power conversion device of the embodiment will be described.

[0012] Hereinafter, this embodiment will be described in detail with reference to the accompanying drawings. In the following description, elements having the same function and structure are labeled with the same symbols.

[0013] Furthermore, in the following embodiments, for constituent elements (e.g., circuits, wiring, various voltages, and signals) that are given reference symbols ending with distinguishing numbers / letters, the descriptions (reference symbols) with the numbers / letters at the end are used where they can be distinguished from each other.

[0014] <Implementation Method>

[0015] Reference Figures 1 to 6 The power conversion device of the embodiment will be described.

[0016] (1) First implementation method

[0017] Regarding the power conversion device of the first embodiment, refer to... Figure 1 as well as Figure 2 Explain the composition and actions.

[0018] (a) Example of composition

[0019] Figure 1 This is a circuit diagram showing an example of the configuration of the power conversion device 100 of this embodiment.

[0020] like Figure 1 As shown, the power conversion device 100 of this embodiment includes a plurality of semiconductor elements 1 (1a, 1b, 1c), a plurality of gate drivers 2 (2a, 2b, 2c), a braking resistor unit 3, a control unit 4, a voltage detection unit 5, a current detection unit 6, and a DC power supply 9.

[0021] Multiple semiconductor elements 1 and a braking resistor 3 are connected between the high-potential side wiring (also known as the DC link) and the low-potential side wiring of the DC power supply 9. The high-potential side wiring is electrically connected to the positive terminal 90 of the DC power supply 9 via a connection node (also known as a connection point, connection terminal, or simply a node) ND1. The low-potential side wiring is electrically connected to the negative terminal (ground) 91 of the DC power supply 9 via a connection node ND3.

[0022] Three semiconductor elements 1 (1a, 1b, 1c) are disposed within the power conversion device 100. Each semiconductor element 1 includes a switching element 10 such as an IGBT (Insulated Gate Bipolar Transistor) and a rectifier element 11 such as a diode. The semiconductor element 1 may also include a field-effect transistor (not shown) such as a MOS (Metal-oxide-semiconductor) transistor.

[0023] One of the two terminals of each semiconductor element 1 is connected to connection node ND2. The other terminal of each semiconductor element 1 is connected to connection node ND3. Connection node ND3 is connected to ground 91.

[0024] Three semiconductor elements 1a, 1b, and 1c are connected in parallel between connection nodes ND2 and ND3. This creates three parallel power paths within the power conversion device 100. The multiple semiconductor elements 1 connected in parallel share the terminal potential between the two connection nodes ND2 and ND3.

[0025] When each semiconductor element 1 is in the on state, a current of a certain magnitude corresponding to the characteristics of the semiconductor element 1 flows.

[0026] Multiple gate drivers 2 (2a, 2b, 2c) are connected one-to-one with multiple semiconductor elements 1. That is, one gate driver 2 is connected to a corresponding one of the multiple semiconductor elements 1. In this embodiment, three gate drivers 2 are provided in the power conversion device 100. Each gate driver 2 supplies a gate drive voltage (gate signal) to the corresponding semiconductor element 1 according to the gate command GC described later.

[0027] The braking resistor section 3 is connected in series with multiple semiconductor elements 1 via connection node ND2 between connection node ND1 and connection node ND3. One of the two terminals of the braking resistor section 3 is connected to the positive terminal 90 of the DC power supply 9 via connection node ND1. The other terminal of the braking resistor section 3 is connected to one terminal of each of the multiple semiconductor elements 1 via connection node ND2. The braking resistor section 3 includes multiple resistive elements (not shown). In addition to resistive elements, the braking resistor section 3 may also include capacitive elements (not shown) and inductive elements (not shown). The configuration consisting of the braking resistor section 3 and the multiple semiconductor elements 1 is also called a power conversion circuit.

[0028] The braking resistor section 3 functions as a load for the power conversion device 100. The braking resistor section 3 outputs a current I1. The magnitude (current flow) of the current I1 can be controlled based on the conduction state of the semiconductor element 1. The braking resistor section 3 generates Joule heat due to the current I1 flowing through it. For example, the power conversion device 100 can consume the supplied power through the heating of the braking resistor section 3. Thus, the power conversion device 100 can perform thermoelectric conversion. Furthermore, the magnitude of the current I1 can be limited based on the rated values ​​(e.g., rated current) of the power conversion device 100.

[0029] The control unit 4 controls the operation of multiple semiconductor elements 1 via the gate driver 2.

[0030] For example, the control unit 4 generates a PWM (Pulse Width Modulation) carrier wave to control the energizing period (also known as the conduction period) of the multiple semiconductor elements 1. The PWM carrier wave is, for example, a signal containing multiple triangular waves (triangular pulses) that are periodically output. The energizing period of the semiconductor element 1 corresponds to the period during which the semiconductor element 1 is turned on.

[0031] In order to control the on-state (power-on state) and non-on state (power-off state) of each semiconductor element 1, the control unit 4 generates gate commands GC (GCa, GCb, GCc). The control unit 4 outputs the generated gate commands GC to each gate driver 2. For example, when the corresponding semiconductor element 1 is set to the on-state (power-on state, energized state), the control unit 4 sets the signal level of the gate command GC to a first level (e.g., "H" level). When the corresponding semiconductor element 1 is set to the non-on state (power-off state, non-energized state), the control unit 4 sets the signal level of the gate command GC to a second level (e.g., "L" level) that is different from the first level.

[0032] The control unit 4 controls the pulse shape (e.g., pulse width) of the gate command GC that may be generated, based on a comparison between the PWM carrier and the current carrying rate of the semiconductor element 1, according to the supplied command power CP. The current carrying rate is determined by various controls, such as PI control of the voltage and current within the power conversion device 100. The current carrying rate is a value representing the proportion of the energizing period of the semiconductor element 1 relative to a certain cycle of the PWM carrier.

[0033] For example, the control unit 4 includes a control processor (not shown), a memory (not shown), and a counter (not shown). The control unit 4 includes arithmetic circuits configured to implement various functions through software or a combination of software and hardware.

[0034] The control unit 4 can control the timing of the operation of the semiconductor element 1 based on a sequence set by software.

[0035] The voltage detection unit 5 detects a voltage equivalent to the potential difference between connection node ND1 and connection node (ground) ND3. The voltage detection unit 5 is capable of measuring and acquiring the voltage value of the detected voltage. The voltage detection unit 5 sends a signal S1, representing the voltage value of the detected voltage, to the control unit 4. The voltage detection unit 5 is connected in parallel between connection node ND1 and connection node ND3, relative to multiple semiconductor elements 1 and the braking resistor unit 3.

[0036] The current detection unit 6 detects the current I1 output from the braking resistor unit 3. For example, the current I1 is supplied to the current detection unit 6 via the semiconductor element 1. The current detection unit 6 can measure and obtain the current value of the detected current I1. The current detection unit 6 sends a signal S2 indicating the current value of the detected current I1 to the control unit 4.

[0037] For example, the power conversion device 100 is electrically connected to an external device 200 such as a processor. The power conversion device 100 of this embodiment is capable of communicating with the external device 200. The power conversion device 100 receives a signal related to the command power CP from the external device 200. The command power CP is a signal indicating the power (e.g., power consumption) that should be converted by the braking resistor unit 3.

[0038] For example, the power conversion device 100 is connected to the electric motor 300. The electric motor 300 is connected to a wheel (not shown). The electric motor 300 receives power from a source after DC-AC conversion via a power conversion device (not shown) such as a three-phase frequency converter. The electric motor 300 generates torque based on the supplied power voltage. The electric motor 300 applies energy corresponding to the torque to the wheel. The electric motor 300 generates regenerative power based on its rotation when the power supply to the electric motor 300 is cut off (e.g., when the wheel decelerates or stops).

[0039] The power conversion device 100 adjusts the DC voltage of the DC power supply 9 and supplies it to the braking resistor section 3.

[0040] The power conversion device 100 is capable of receiving regenerated power from the electric motor 300. The regenerated power is supplied to the braking resistor section 3. The power conversion device 100 can consume the regenerated power generated by the electric motor 300 through thermoelectric conversion based on the braking resistor section 3.

[0041] Right now, Figure 1The power conversion device 100 is equivalent to a power generation braking circuit (braking chopper circuit) that controls the power consumption of the braking resistor section 3. In the power conversion device 100, which is a power generation braking circuit, for example, the semiconductor element 1 is also referred to as a braking chopper element.

[0042] Furthermore, the internal configuration of the power conversion device 100 is not limited to the aforementioned components. Other components may be further provided within the device 100, or some of the aforementioned components may be removed from the device 100. For example, one or more of the voltage detection unit 5, the current detection unit 6, and the DC power supply 9 may be external components of the power conversion device 100. In addition, various signals such as gate command GC, gate signal, and command power CP may be electrical signals supplied via wiring or optical signals supplied via optocouplers.

[0043] In the power conversion device 100 of this embodiment, the plurality of semiconductor elements 1 connected in parallel between the two connection nodes ND2 and ND3 are turned on at different times during a certain operation period. In other words, in the power conversion device 100 of this embodiment, the energizing periods of the plurality of semiconductor elements 1 do not overlap.

[0044] (b) Example of an action

[0045] Figure 2 This is a waveform diagram showing an example of the operation of the power conversion device 100 according to the first embodiment.

[0046] Figure 2 The waveform diagram represents the switching timing of the multiple semiconductor elements 1 of the power conversion device 100.

[0047] exist Figure 2 In the switching timing of semiconductor element 1, it is shown that... Figure 1 The control unit 4 generates a PWM carrier wave and the time shift of the gate commands GC (GCa, GCb, GCc) output from the control unit 4 to the semiconductor elements 1a, 1b, 1c connected in parallel with the three.

[0048] use Figure 2 The operation of the power conversion device in this embodiment will be explained.

[0049] exist Figure 1 In the power conversion device 100, the voltage between the connection nodes ND1 and ND3 is detected by the voltage detection unit 5, and the current (current flow) I1 output from the braking resistor unit 3 is detected by the current detection unit 6. A signal S1 related to the voltage value of the detected voltage and a signal S2 related to the current value of the current I1 are supplied to the control unit 4.

[0050] The control unit 4 multiplies the voltage value (represented by signal S1) with the current value (represented by signal S2) of the energizing current I1 and calculates the power consumption generated in the power conversion device (generator brake circuit) 100.

[0051] The control unit 4 receives command power CP from the external device 200. For example, the received command power CP shows a value corresponding to the required driving state of the motor 300 (e.g., deceleration or stopping).

[0052] like Figure 2 As shown, the control unit 4 generates a PWM carrier CW to generate and control the gate command GC of each semiconductor element 1. For example, the period Tz from time ta to time tb is the operation period Tz of one cycle (one sequence) in which the on / off state of the multiple semiconductor elements 1 connected in parallel is controlled sequentially. The power conversion device 100 repeatedly executes multiple operation periods Tz.

[0053] In this embodiment, the operation period Tz is divided into multiple parts (intervals) based on the number of semiconductor elements 1. When the number of semiconductor elements 1 connected in parallel between connection node ND2 and connection node ND3 is N, the period Tz is divided into N parts. N is a natural number greater than or equal to 2. For example, the lengths (Tz / N) of the N parts into which the operation period Tz is divided are equal. Each operation period Tz contains multiple periods CY corresponding to multiple triangular waves of the PWM carrier CW, depending on the number of parallel current paths (e.g., the number of parallel semiconductor elements 1).

[0054] As in this embodiment, when there are three semiconductor elements 1 connected in parallel, one operation period Tz contains a triangular wave of three cycles. That is, the operation period Tz contains three parts corresponding to the period of the controlled object of the three semiconductor elements 1. In addition, the number of semiconductor elements 1 connected in parallel can be two or more.

[0055] The control unit 4 determines the current-carrying rate DF (DF1, DF2) of one or more semiconductor elements 1 through various controls (e.g., PI control) to ensure that the calculated power consumption matches the command power CP assigned to the control unit 4. The current-carrying period (the period of conduction) of the semiconductor element 1 is set relative to a certain period CY of the PWM carrier wave CW based on the current-carrying rate DF. The time corresponding to the period CY allocated to each semiconductor element 1 is also referred to as the control target period.

[0056] During a certain operation period Tz, the control unit 4 compares the PWM carrier CW with the current rate DF1. As a result, the control unit 4 can generate a gate command GC with the desired pulse width (the period of the "H" level). The control unit 4 supplies the generated gate command GC to the corresponding gate driver 2. The gate driver 2 supplies a gate drive voltage to the corresponding semiconductor element 1 according to the "H" level signal of the supplied gate command GC. In each gate command GCa, GCb, GCc for the current rate DF1, the "H" level signal has a pulse width Wa1, Wb1, and Wc1, respectively.

[0057] Therefore, the conduction of the corresponding semiconductor element 1 is enabled.

[0058] like Figure 2 As shown, the control unit 4 switches a semiconductor element 1, which is the comparison object for the current rate, according to each cycle CY of the generated triangular wave PWM carrier CW.

[0059] For example, during the operation period Tz of the three cycles CYa, CYb, and CYc that include the PWM carrier CW, the first cycle CYa controls the semiconductor element 1a as the object of conduction, the second cycle CYb controls the semiconductor element 1b as the object of conduction, and the third cycle CYc controls the semiconductor element 1c as the object of conduction.

[0060] During period CYa, current I1 depends only on semiconductor element 1a in the on-state, and has no substantial effect on semiconductor elements 1b and 1c in the off-state. During period CYb following period CYa, current I1 depends only on semiconductor element 1b in the on-state, and has no substantial effect on semiconductor elements 1a and 1c in the off-state. During period CYc following period CYb, current I1 depends only on semiconductor element 1c in the on-state, and has no substantial effect on semiconductor elements 1a and 1b in the off-state.

[0061] Thus, in this embodiment, the control unit 4 uses the three cycles of the PWM carrier CW as an operation period Tz to repeatedly switch the on and off states of the three semiconductor elements 1.

[0062] Therefore, in the power conversion device 100 of this embodiment, during the cycle CY in which one of the plurality of semiconductor elements 1 is turned on, there are no other semiconductor elements 1 that are turned on. That is, in the power conversion device 100 of this embodiment, one semiconductor element 1 is turned on individually during a certain cycle CY.

[0063] For example, when the current carrying rate of each semiconductor element 1 is the same, the energizing periods (pulse width of gate command GC) Wa1, Wb1, and Wc1 of the multiple semiconductor elements 1 connected in parallel can be common to substantially the same length. Thus, in this embodiment, all the semiconductor elements 1 connected in parallel can make the generation loss common and equally share the required load.

[0064] Furthermore, the current flow rate of semiconductor element 1 varies depending on the magnitude of the command power CP. The pulse width of the gate command GC is controlled based on the change in current flow rate. For example, when the current flow rate becomes lower according to the command power CP, the pulse width of the gate command GC becomes narrower.

[0065] On the other hand, such as Figure 2 As with the current rate DF2, when the current rate becomes a higher value according to the command power CP, the pulse widths Wa2, Wb2, and Wc2 of the gate commands GCa, GCb, and GCc become wider. In this case, sometimes the falling edge of a certain gate command (e.g., gate command GCa) is aligned with the rising edge of another gate command (e.g., gate command GCb) that is temporally adjacent to it at substantially the same timing.

[0066] Semiconductor device 1 operates with a response speed that includes a certain amount of delay relative to the rising and falling edges of the gate command GC. That is, semiconductor device 1 actually operates after a certain delay time elapses from receiving the rising edge of the gate command GC. In addition, semiconductor device 1 stops operating after a certain delay time elapses from receiving the falling edge of the gate command GC.

[0067] Therefore, based on the set current rate DF2, even when the falling edge of a gate instruction GC aligns with the rising edge of the next gate instruction GC, the actual energizing periods of the two semiconductor elements 1 do not substantially overlap. Thus, during each operating period Tz, the semiconductor elements 1 operate independently in mutually different periods CY.

[0068] As described above, in this embodiment, the period during which each semiconductor element 1 bears the load is one-third of the operating period Tz. Therefore, even if the current I1 flows in one semiconductor element 1 in each cycle CY, the load applied to the semiconductor element 1 can be allowed to be within the withstand voltage range of the semiconductor element 1 based on the rating of the power conversion device 100.

[0069] (c) Summary

[0070] As the conversion capacity of a power conversion device increases, and the rated current is increased by connecting multiple semiconductor elements in parallel, it is desirable to ensure that the operating characteristics of each semiconductor element, the characteristics of the gate driver, and the circuit impedances between circuits are consistent. If these consistency is not achieved, the current cannot be evenly distributed among the multiple semiconductor elements operating simultaneously, potentially leading to adverse conditions such as concentrated heat generation in specific semiconductor elements. Consequently, the failure risk of the power conversion device increases.

[0071] In the design of power conversion devices, it is necessary to consider the uneven load distribution among each semiconductor element, ensuring sufficient current capacity and / or parallel quantity of the semiconductor elements from a derating perspective. Alternatively, for the sake of circuit impedance integration, the configuration of semiconductor elements and / or the design of connecting conductors must be optimized. These requirements sometimes conflict with the miniaturization and space-saving design of the device. Therefore, as a whole, this may lead to a decrease in the product competitiveness of the power conversion device.

[0072] According to this embodiment, in a circuit configuration where multiple semiconductor elements 1 are connected in parallel, the limitations of hardware design related to the operating characteristics of each semiconductor element 1, the characteristics of the gate driver 2, and the integration of circuit impedance are eliminated.

[0073] The power conversion device 100 of this embodiment includes a parallel connection circuit in which multiple semiconductor elements 1, each independently set to an on state, share the current I1. Therefore, the power conversion device 100 of this embodiment can evenly distribute the load on each semiconductor element 1, even under hardware design difficulties such as arranging the individual semiconductor elements 1 close together.

[0074] As described above, in this embodiment, the power conversion device 100 evenly divides the period (e.g., the power-on period) during which multiple semiconductor elements 1a, 1b, and 1c connected in parallel within a power-on path will be controlled by the control unit 4. Then, the power conversion device 100 of this embodiment individually assigns a turn-on command to each semiconductor element 1a, 1b, and 1c.

[0075] In this embodiment, only one semiconductor element 1 is turned on during each cycle CY of a certain period Tz. Therefore, the current I1 can be uniquely determined without considering the non-uniformity of characteristics among the multiple semiconductor elements 1 connected in parallel. Thus, in the power conversion device 100 of this embodiment, the energizing period and the current I1 of all the parallel-connected semiconductor elements 1 are consistent, resulting in loss commonality. Therefore, the power conversion device 100 of this embodiment can make the load generated during the operation period Tz equally distributed among the multiple semiconductor elements 1.

[0076] Thus, according to this embodiment, the aforementioned hardware design limitations can be eliminated, and the parallel-connected semiconductor elements 1 can be simply controlled based on software.

[0077] As a result, the power conversion device of this embodiment can reduce the limitations of the hardware design of the power conversion device.

[0078] (2) Second implementation method

[0079] Reference Figure 3 as well as Figure 4 The power conversion device of the second embodiment will be described.

[0080] (a) Example of composition

[0081] Figure 3 This is a circuit diagram showing an example of the configuration of the power conversion device 100 of this embodiment.

[0082] Figure 3 The power conversion device 100 shown includes a plurality of power conversion units 7 (7a, 7b, 7c).

[0083] For example, three power conversion units 7a, 7b, and 7c are installed within the power conversion device 100.

[0084] Power conversion unit 7a includes a semiconductor element 1a, a gate driver 2a, a control unit 4a, a voltage detection unit 5a, and a current detection unit 6a. Power conversion unit 7b includes a semiconductor element 1b, a gate driver 2b, a control unit 4b, a voltage detection unit 5b, and a current detection unit 6b. Power conversion unit 7c includes a semiconductor element 1c, a gate driver 2c, a control unit 4c, a voltage detection unit 5c, and a current detection unit 6c.

[0085] For example, in each power conversion unit 7, a current detection unit 6 is provided between the connection node ND2 and the semiconductor element 1. Figure 3 In this example, the voltage detection unit 5 is connected to the connection node ND3 without passing through the current detection unit 6.

[0086] The three power conversion units 7a, 7b, and 7c are connected in common with a braking resistor section 3.

[0087] The power conversion device 100 in this embodiment is the same as that in the above embodiment, and is equivalent to a generator braking circuit that controls the power consumption in the braking resistor section 3.

[0088] In the power conversion device 100 of this embodiment, a plurality of semiconductor elements 1 are independently provided for each power conversion unit 7, and an independent control unit 4 is provided for each plurality of semiconductor elements 1. In addition, each power conversion unit 7 may also include a plurality of semiconductor elements 1 connected in parallel.

[0089] Within each power conversion unit 7, each control unit 4 (4a, 4b, 4c) controls the operation of the corresponding semiconductor element 1 (1a, 1b, 1c) based on the detection results of the voltage detection unit 5 (5a, 5b, 5c), the detection results of the current detection unit 6 (6a, 6b, 6c), and various information such as the command power CP.

[0090] Multiple control units 4 generate PWM carriers CW (CWa, CWb, CWc) respectively. Each PWM carrier CWa, CWb, and CWc contains multiple triangular waves of a certain period.

[0091] Any one of the multiple control units 4 generates a synchronization signal SS1 and sends the generated synchronization signal SS1 to the other control units 4. For example, in this embodiment, control unit 4a generates the synchronization signal SS1. Control unit 4a sends the generated synchronization signal SS1 to control units 4b and 4c. Control units 4b and 4c receive the synchronization signal SS1.

[0092] Synchronization signal SS1 is used to control the timing of operations among multiple power conversion units 7. For example, synchronization signal SS1 is a quadrilateral pulse signal with a rising edge and a falling edge. The carrier wave of each power conversion unit 7 is synchronized with the rising edge or falling edge of synchronization signal SS1, and the phases of each carrier wave are aligned.

[0093] (b) Actions

[0094] Figure 4 This is a waveform diagram showing an example of the operation of the power conversion device 100 in this embodiment.

[0095] Figure 4 The waveform diagram represents the switching timing of multiple semiconductor elements 1 in multiple power conversion units 7 of the power conversion device 100.

[0096] exist Figure 4 In the switching timing of semiconductor element 1, it is shown that... Figure 3 The control units 4a, 4b, and 4c generate PWM carriers CWa, CWb, and CWc respectively, and the gate commands GCa, GCb, and GCc output from each control unit 4a, 4b, and 4c to semiconductor elements 1a, 1b, and 1c, as well as the time progression of the synchronization signal SS1.

[0097] exist Figure 3 In the power conversion device 100, the power conversion unit 7a obtains the voltage value between nodes ND1 and ND3 through the voltage detection unit 5a, and obtains the current value of the energizing current I1 of the braking resistor unit 3 through the current detection unit 6a.

[0098] The control unit 4a multiplies the acquired voltage value (represented by signal S1) and current value (represented by signal S2) to calculate the power consumption of the power conversion device 100. The control unit 4a uses PI control or similar methods to determine the current carrying rate DFa for the semiconductor element 1a, ensuring that the power consumption matches the command power CP supplied to the control unit 4a from the external device 200. The control unit 4a compares the PWM carrier wave CWa with the current carrying rate DFa to generate the gate command GCa for the semiconductor element 1a.

[0099] Similarly, in the power conversion unit 7b, the control unit 4b calculates the power consumption based on the voltage value obtained by the voltage detection unit 5b and the current value obtained by the current detection unit 6b. Based on the calculated power consumption and the command power CP, the control unit 4b determines the current carrying rate DFb for the semiconductor element 1b. To generate the gate command GCb for the semiconductor element 1b, the control unit 4b compares the PWM carrier CWb with the current carrying rate DFb.

[0100] Alternatively, in the power conversion unit 7c, the control unit 4c calculates the power consumption based on the voltage value obtained by the voltage detection unit 5c and the current value obtained by the current detection unit 6c. Based on the calculated power consumption and the command power CP, the control unit 4c determines the current carrying rate DFc for the semiconductor element 1c. To generate the gate command GCc for the semiconductor element 1c, the control unit 4c compares the PWM carrier CWc with the current carrying rate DFc.

[0101] exist Figure 4 In the process, for the PWM carrier CWa generated by the control unit 4a, the control unit 4a pre-sets the period (control period) of the semiconductor element 1a as the control target period for conduction control only during the period Tz. During the other periods CYb and CYc within the period Tz, the control unit 4a excludes the semiconductor element 1a from the control target and does not turn on the semiconductor element 1a.

[0102] Similarly, control unit 4b uses only the period CYb of the PWM carrier CWb as the period for controlling the conduction of semiconductor element 1b, and controls the conduction state of semiconductor element 1b. Control unit 4c uses only the period CYc of the PWM carrier CWc as the period for controlling the conduction of semiconductor element 1c, and controls the conduction state of semiconductor element 1c.

[0103] In this embodiment, since the power conversion units 7a, 7b, and 7c to which each control unit 4a, 4b, and 4c belongs are different, it is assumed that each control unit 4a, 4b, and 4c has a different control processor. In this case, the phases of the PWM carriers CWa, CWb, and CWc generated independently by each control unit 4a, 4b, and 4c are not limited to being the same.

[0104] Therefore, in this embodiment, control unit 4a is designated as the master device, and control units 4b and 4c are designated as slave devices. For example, control unit 4a of power conversion unit 7a generates a pulse-shaped synchronization signal SS1 at the beginning of the period CYa of the PWM carrier CW. Control unit 4a sends the generated synchronization signal SS1 to control units 4b and 4c in other power conversion units 7b and 7c. Control units 4b and 4c correct the phase of the corresponding PWM carriers CWb and CWc based on the received synchronization signal SS1, so that the first period CYa begins based on the timing of the synchronization signal SS1. For example, multiple PWM carriers CWa, CWb, and CWc are controlled by each control unit 4a, 4b, and 4c to ensure that the phases are aligned at the rising edge of the synchronization signal SS1.

[0105] Therefore, the power conversion device 100 of this embodiment can align the phases of multiple PWM carriers CWa, CWb, and CWc at a timing synchronized with the synchronization signal SS1.

[0106] In addition, the phases of multiple PWM carriers CWa, CWb, and CWc can also be aligned at the timing of the falling edge of the synchronization signal SS1.

[0107] Similar to the first embodiment, in this embodiment, the semiconductor elements 1 of each power conversion unit 7 are set to the on state during different timings (cycles CY). That is, during the operation period Tz, in cycle CYa, only semiconductor element 1a is set to the on state during the period corresponding to the "H" level gate command GCa from control unit 4a. In cycle CYb following cycle CYa, only semiconductor element 1b is set to the on state during the period corresponding to the "H" level gate command GCb from control unit 4b. Furthermore, in cycle CYc following cycle CYb, only semiconductor element 1c is set to the on state during the period corresponding to the "H" level gate command GCc from control unit 4c.

[0108] As described above, in this embodiment of the power conversion device 100, when the control units 4a, 4b, and 4c corresponding to the multiple semiconductor elements 1a, 1b, and 1c connected in parallel in a single power path (the path between connection node ND1 and ground 91) are each independent processors, a common synchronization signal SS1 is supplied to the control units 4a, 4b, and 4c to align the phase of the PWM carrier CW. Therefore, the power conversion device 100 of this embodiment can synchronize the switching timing of the multiple semiconductor elements 1 controlled by different PWM carrier CWs.

[0109] As a result, in this embodiment, similar to the first embodiment, the energizing period and energizing current I1 of all the parallel-connected semiconductor elements 1 are consistent, resulting in loss commonality. Therefore, the multiple semiconductor elements 1 can equally share the load generated within the power conversion device 100.

[0110] Therefore, the power conversion device 100 of this embodiment can eliminate hardware design limitations such as the operating characteristics of the parallel-connected semiconductor element 1, the characteristics of the gate driver 2, and the integration of circuit impedance, and can perform simple control of the parallel-connected semiconductor element 1 based on software.

[0111] As described above, the power conversion device 100 of this embodiment can reduce the limitations of the hardware design of power conversion devices.

[0112] (3) Variations

[0113] Reference Figure 5 as well as Figure 6 A variation of the power conversion device of the embodiment will be described.

[0114] Figure 5 This is a circuit diagram showing a modified example of the power conversion device according to the second embodiment.

[0115] like Figure 5 As shown, a synchronization signal SS1x is supplied from the external device 200 to the power conversion device 100. In the power conversion device 100, multiple control units 4 receive the synchronization signal SS1x from the external device 200.

[0116] and Figure 3 as well as Figure 4 Similar to the example, multiple control units 4 correct the phase of multiple PWM carriers based on the synchronization signal SS1x.

[0117] In this case, Figure 5 The modified power conversion device 100 can also perform the same operation as that described in the second embodiment.

[0118] Figure 6This is a waveform diagram illustrating a modified example of the operation of the power conversion device 100.

[0119] like Figure 6 As shown, during a certain operation period Tz, the value of the current rate DF3 may sometimes change. In this case, the value of the current rate DF3, which is the comparison object, will be different for each of the plurality of semiconductor elements 1. As a result, the pulse widths Wa3, Wb3, Wc3 of the plurality of gate commands GCa, GCb, GCc are different for each corresponding semiconductor element 1a, 1b, 1c.

[0120] For example, the flow rate DF3 in period CYa is higher than that in periods CYb and CYc. Conversely, the flow rate DF3 in period CYb is lower than that in period CYa, but higher than that in period CYc. In this case, the pulse width Wa3 in period CYa is wider than the pulse widths Wb3 and Wc3 in periods CYb and CYc. The pulse width Wb3 in period CYb is narrower than Wa3 in period CYa, but wider than Wc3 in period CYc.

[0121] exist Figure 6 Even if the pulse widths Wa3, Wb3, and Wc3 of the multiple gate commands GCa, GCb, and GCc within the operation period Tz are different, the switching on and off of the multiple semiconductor elements 1 is controlled so that the semiconductor elements 1 become in the on state at different timings. Thus, in this modified example, the energizing periods of the multiple semiconductor elements 1 do not overlap within the operation period Tz.

[0122] therefore, Figure 6 The modified power conversion device 100 can achieve substantially the same effect as the power conversion device 100 of the above embodiment.

[0123] (4) Other

[0124] The power conversion device 100 of the embodiment can be applied, for example, to railway vehicles, automobiles, ships, aircraft, and power generation devices. The power conversion device 100 of the embodiment can also be installed in the same system as other power conversion devices such as AC inverter circuits.

[0125] Several embodiments of the present invention have been described above, but these embodiments are merely illustrative and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are included in the scope of the invention as described in the claims and its equivalents.

Claims

1. A power conversion device, wherein, have: A braking resistor is disposed between the first node and the second node; Multiple semiconductor elements are disposed between the braking resistor section and the second node, and are connected in series with the braking resistor section and in parallel with each other between the braking resistor section and the second node. Multiple gate drivers, each corresponding to one of the aforementioned semiconductor elements, supply driving voltages to their respective semiconductor elements; and The control unit, based on a carrier wave, supplies gate commands corresponding to the driving voltages to the plurality of gate drivers respectively. During the operation of the braking resistor, the aforementioned semiconductor elements are set to the conducting state at different timings, synchronized with the periodic waveform of the carrier wave. In each of the multiple parts during the above-mentioned operation, only one of the multiple semiconductor elements is set to the on state, through which current flows from the braking resistor section.

2. The power conversion device as claimed in claim 1, wherein, In the case where the number of the aforementioned semiconductor elements is represented by N, where N is a natural number greater than or equal to 2, and the aforementioned operation period is represented by T, The aforementioned action is divided into N parts. The length of each of the N segments that are divided during the above action is represented by T / N.

3. The power conversion device as described in claim 1, wherein, The aforementioned braking resistor receives regenerative power from the motor and outputs a current corresponding to the aforementioned regenerative power.

4. The power conversion device as claimed in claim 1, wherein, The aforementioned semiconductor elements include a first semiconductor element, a second semiconductor element, and a third semiconductor element. The aforementioned carrier wave includes a first cycle, a second cycle, and a third cycle during the aforementioned operation. During the first cycle, the first semiconductor element is set to the on state, while the second and third semiconductor elements are set to the off state, and the current flows through the first semiconductor element. During the second cycle, the second semiconductor element is set to the on state, while the first and third semiconductor elements are set to the off state, and the current flows through the second semiconductor element. In the aforementioned third cycle, the third semiconductor element is set to the on state, while the first and second semiconductor elements are set to the off state, and the current flows through the third semiconductor element. The magnitude of the load on the first semiconductor element caused by the aforementioned current, the magnitude of the load on the second semiconductor element caused by the aforementioned current, and the magnitude of the load on the third semiconductor element caused by the aforementioned current are equal.

5. A power conversion device, wherein, have: A braking resistor is disposed between the first node and the second node; and Multiple power conversion units are disposed between the braking resistor section and the second node, respectively connected in series with the braking resistor section and connected in parallel with each other between the braking resistor section and the second node. Each of the multiple power conversion units includes: Semiconductor components; A gate driver supplies a driving voltage to the aforementioned semiconductor element; and The control unit, based on the carrier wave, supplies the gate driver with a gate command corresponding to the driving voltage. During the operation of the braking resistor, the semiconductor element is set to the on state at different timings, synchronized with the periodic waveform of the carrier wave. In each of the multiple parts during the above-mentioned operation, only one of the multiple semiconductor elements is set to the on state, through which current flows from the braking resistor section.

6. The power conversion device as claimed in claim 5, wherein, In the case where the number of the aforementioned multiple power conversion units is represented by N, where N is a natural number greater than 2, and the aforementioned operation period is represented by T, The aforementioned action is divided into N parts. The length of each of the N segments that are divided during the above action is represented by T / N.

7. The power conversion device as claimed in claim 5, wherein, The control unit of one of the aforementioned power conversion units generates a synchronization signal. The aforementioned synchronization signals are respectively supplied to the control units of the remaining power conversion units among the plurality of power conversion units. The control units of the remaining power conversion units, based on the synchronization signal, align the phase of the carrier wave of each of the control units of the remaining power conversion units with the phase of the carrier wave of the control unit of one power conversion unit.

8. The power conversion device as claimed in claim 7, wherein, The aforementioned synchronization signal is a pulse wave with both a rising edge and a falling edge. The phase of the carrier wave of each of the plurality of power conversion units is synchronized with either the rising edge or the falling edge.

9. The power conversion device as claimed in claim 5, wherein, The aforementioned braking resistor receives regenerative power from the motor and outputs a current corresponding to the aforementioned regenerative power.

10. The power conversion device as claimed in claim 5, wherein, The aforementioned multiple power conversion units include a first power conversion unit, a second power conversion unit, and a third power conversion unit. During the first part of the aforementioned operation, the semiconductor element of the first power conversion unit is set to an on state, while the semiconductor elements of the second and third power conversion units are set to a non-on state, and the current flows through the semiconductor element of the first power conversion unit. During the second part of the aforementioned operation, the semiconductor element of the second power conversion unit is set to an on state, while the semiconductor elements of the first and third power conversion units are set to a non-on state, and the current flows through the semiconductor element of the second power conversion unit. In the third part of the aforementioned operation, the semiconductor element of the third power conversion unit is set to an on state, while the semiconductor elements of the first power conversion unit and the second power conversion unit are set to a non-on state, and the current flows through the semiconductor element of the third power conversion unit. The load on the semiconductor element of the first power conversion unit caused by the aforementioned current, the load on the semiconductor element of the second power conversion unit caused by the aforementioned current, and the load on the semiconductor element of the third power conversion unit caused by the aforementioned current are all equal.

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