A one-way ramp ADC

Abstract

The application relates to a one-way ramp ADC, comprising a comparator, a comparator output preprocessing circuit, a clock phase calibration pulse generating circuit, a clock phase sampling decoding circuit, a data calibration circuit, a low digit calculation circuit, a counting pulse modulation circuit and a counter circuit. In the application, by converting the discrete time process of sampling the ADC clock phase into part of the continuous process of multiple sampling accumulation counting, the combination of the related multiple sampling technology based on multiple sampling accumulation counting and the ADC clock speed-up technology based on multiple groups of fixed phase difference ADC clocks is realized in the one-way ramp ADC architecture, and the sampling precision, speed and noise performance of the one-way ramp ADC are improved.

Description

Technical Field

[0001] This invention belongs to the field of ADC technology and relates to a one-way ramp ADC. Background Technology

[0002] Current high-performance image sensing applications place higher demands on the A / D conversion speed and accuracy of focal plane readout circuits. Furthermore, some applications also aim to minimize the noise of the readout circuit itself. Correlation multiple sampling (CMS) is a commonly used noise reduction method for readout circuits. This technique reduces the random noise content in the signal by acquiring and mixing several samples containing uncorrelated random noise information (typically thermal noise) and then evenly distributing them.

[0003] Single-slope ADCs (hereinafter referred to as single-slope ADCs) have become a typical AD architecture choice for column-level readout circuits of image sensors due to their simple structure, small on-chip area, and good conversion linearity. However, traditional single-slope ADCs cannot simultaneously meet the current application requirements for high speed and high precision, and they lack the ability to perform correlated multiple sampling. The speed and accuracy of single-slope ADCs can be improved by accumulating the converted values ​​of multiple sets of single-slope signals to multiple sets of sampled data in one A / D conversion cycle. It is also common to improve the speed and accuracy of single-slope ADCs by sampling and identifying the phases of multiple sets of ADC clock signals with fixed phase differences (these signals are usually generated by delay-locked loops (DLLs)).

[0004] This paper considers combining multiple sampling accumulation with multi-group ADC clock acceleration techniques to simultaneously improve ADC speed, accuracy, and noise performance. However, multiple sampling accumulation involves counter counting, which is a continuous process in time, while phase sampling of multiple ADC clocks is a discrete process in time. Combining the two requires converting the continuous process into a discrete process, or vice versa. Existing single-slope ADCs based on phase sampling of multiple ADC clocks cannot fully realize this process conversion, resulting in only one sample per A / D conversion cycle, which poses a significant challenge in implementing correlated multiple sampling functionality. Summary of the Invention

[0005] In view of the shortcomings of the prior art, the technical problem to be solved by the present invention is to provide a unidirectional ramp ADC that can improve sampling accuracy.

[0006] To achieve the above objectives, the present invention provides the following technical solution:

[0007] A one-way ramp ADC, including

[0008] A comparator is used to compare the signal to be converted with a ramp signal to obtain and output a toggle pulse;

[0009] The comparator output preprocessing circuit is used to convert the effective flip edge of the comparator output flip pulse into a rising edge, obtain and output the first modulation data pulse, and output the first counter data pulse.

[0010] A clock phase calibration pulse generation circuit is used to directly output the first modulation data pulse as the calibration data pulse and the second modulation data pulse when clock phase calibration is not required.

[0011] The clock phase sampling and decoding circuit is used to decode the calibration data pulses according to the externally input ADC DLL clock to obtain an m-bit decoded data signal, and to synchronize the data pulses of the first counter according to the externally input first ADC clock to obtain the data pulses of the second counter.

[0012] The data calibration circuit is used to take the high level of the second modulation data pulse and the ADC DLL data calibration clock as calibration event triggering elements, determine whether the flip edge of the second counter data pulse is synchronized with the flip edge of the flip pulse according to the m-bit decoded data signal, and add a corresponding number of small pulses to the second counter data pulse according to the determination result to obtain and output the data calibration pulse.

[0013] The low-bit calculation circuit is used to perform signed accumulation on the m-bit decoded data signal to obtain a low-bit signal that reflects the last m bits of information of the AD conversion result, and to add a corresponding number of small pulses to the data calibration pulse according to the carry and borrow values ​​of the accumulation result to obtain the data pulse for the third counter.

[0014] A counting pulse modulation circuit is used to convert the data pulses of the third counter into high-frequency pulses of a multi-segment high-frequency clock pattern based on the externally input second ADC clock; and

[0015] The counter circuit is used to count the high-frequency pulses obtained by the counting pulse modulation circuit to obtain a high-digit signal that reflects the information of the m-th bit and the bits before the m-th bit of the AD conversion result.

[0016] In this invention, by converting the discrete-time process of sampling the ADC clock phase into part of a continuous process of accumulating and counting multiple samplings, the invention combines correlation multiple sampling technology based on multiple sampling and accumulating counting with ADC clock speed-up technology based on multiple sets of fixed phase difference ADC clocks in a single-slope ADC architecture. This is beneficial for improving the sampling accuracy, speed and noise performance of the single-slope ADC. Attached Figure Description

[0017] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0018] Figure 1 This is a schematic diagram of a preferred embodiment of the unidirectional ramp ADC of the present invention.

[0019] Figure 2 The circuit diagram for the comparator output preprocessing circuit.

[0020] Figure 3 Circuit diagram of a pulse generation circuit for clock phase calibration.

[0021] Figure 4 The circuit diagram for the clock phase sampling and decoding circuit.

[0022] Figure 5 This is a flowchart for generating the inverting control signal.

[0023] Figure 6 A flowchart for adding small pulses to the data pulses of the second counter.

[0024] Figure 7a , Figure 7b , Figure 7c These are timing diagrams of the signals at each port of the data calibration circuit in three specific implementations.

[0025] Figure 8 This is a flowchart of the low-digit computing circuit.

[0026] Figure 9 This is a timing diagram of the port signals of a low-digit computing circuit in a specific example.

[0027] Figure 10 This is a flowchart of the counting pulse modulation circuit.

[0028] Figure 11 This is a timing diagram of key signals of a one-way ramp ADC in a specific example of a complete AD conversion process.

[0029] The meanings of the labels in the attached diagram are as follows:

[0030] Comparator-100; Signal to be converted-121; Ramp signal-122; Comparator output preprocessing circuit-200; Clock phase calibration pulse generation circuit-300; Clock phase sampling and decoding circuit-400; Clock phase calibration circuit-500; Data calibration circuit-600; Low-digit calculation circuit-700; Counting pulse modulation circuit-800; Counter circuit-900. Detailed Implementation

[0031] The following specific examples illustrate the implementation of the present invention. The illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0032] like Figure 1 As shown, a preferred embodiment of the unidirectional ramp ADC of the present invention includes a comparator 100, a comparator output preprocessing circuit 200, a clock phase calibration pulse generation circuit 300, a clock phase sampling and decoding circuit 400, a data calibration circuit 600, a low-digit calculation circuit 700, a counting pulse modulation circuit 800, and a counter circuit 900. Of course, in order to calibrate the clock phase when there is a phase mismatch in the ADC clock, the unidirectional ramp ADC may also include a clock phase calibration circuit 500.

[0033] The comparator 100 compares the signal to be converted with the ramp signal to obtain and output a flip pulse. The positive input of the comparator 100 is connected to the ramp signal 122, and the negative input is connected to the signal to be converted 121. Each low level and each high level of the ramp signal 122 intersects with each low level and each high level of the signal to be converted 121. These intersections can be one, two, or more. In this embodiment, four intersections are used as an example. Of course, there can be more intersections between each low level and each high level of the ramp signal 122 and the signal to be converted 121, allowing for more sampling of the same set of input signals. The minimum level of the ramp signal is less than the minimum low level of the signal to be converted, the maximum value of the ramp signal during the low level of the signal to be converted is greater than the maximum value of the low level of the signal to be converted, and the maximum value of the ramp signal during the high level of the signal to be converted is greater than the maximum value of the high level of the signal to be converted.

[0034] The comparator output preprocessing circuit 200 is provided with signal input terminals in, out_cnt output terminals, out_mod output terminals, input terminals for the counter data pulse positive phase output control signal adc_sub_p (hereinafter referred to as control signal adc_sub_p), input terminals for the counter data pulse inverted phase output control signal adc_sub_n (hereinafter referred to as control signal adc_sub_n), input terminals for the modulation data pulse positive phase output control signal adc_sub_p_mod (hereinafter referred to as control signal adc_sub_p_mod), and input terminals for the modulation data pulse inverted phase output control signal adc_sub_n_mod (hereinafter referred to as control signal adc_sub_n_mod). The control signals adc_sub_p, adc_sub_n, adc_sub_p_mod, and adc_sub_n_mod are all input from outside the ADC. The comparator output preprocessing circuit 200 is used to convert the effective flip edge of the flip pulse input from its signal input terminal in into a rising edge to obtain a first modulation data pulse mod (hereinafter referred to as pulse mod) and output it from its output terminal out_mod, and output a first counter data pulse cnt (hereinafter referred to as pulse cnt) from its output terminal out_cnt.

[0035] like Figure 2 As shown, the comparator output preprocessing circuit 200 includes AND gates U201, U202, U203, and U204, an inverter 205, an OR gate 206, and an OR gate 207. The second input terminals of AND gates U201 and U203, as well as the input terminal of the inverter 205, are electrically connected to the output terminal of the comparator. The second input terminals of AND gates U202 and U204 are electrically connected to the output terminal of the inverter 205. The first input terminal of AND gate U201 is used to input the control signal `adc_sub_p`, and the first input terminal of AND gate U202 is used as an input terminal to input the control signal `adc_sub_n`. The output terminals of AND gates U201 and U202 are respectively electrically connected to the two input terminals of the OR gate 206, and the output terminal of the OR gate 206 is used to output the pulse `cnt`. The first input terminal of AND gate U203 is used to input the control signal adc_sub_p_mod, and the first input terminal of AND gate U204 is used to input the control signal adc_sub_n_mod. The output terminals of AND gates U203 and U204 are electrically connected to the two input terminals of OR gate 207, and the output terminal of OR gate 207 is used to output the pulse mod.

[0036] By adopting the above circuit structure and designing the timing of the control signals adc_sub_p, adc_sub_n, adc_sub_p_mod, and adc_sub_n_mod, the signal input at the in terminal can be filtered, so that the output at the out_cnt terminal outputs the final counter data pulse that can be used by the counter circuit. Furthermore, the modulation data pulse output at the out_mod terminal will turn each valid toggle edge of the in terminal input signal into a rising edge for use by subsequent circuits.

[0037] The principle of controlling the output pulse cnt by adjusting the timing of control signals adc_sub_p and adc_sub_n is as follows: When both control signals adc_sub_p and adc_sub_n are low, the output pulse cnt always outputs a low level. When the timing of control signal adc_sub_p is high and the timing of control signal adc_sub_n is low, the output pulse cnt is consistent with the signal input at input terminal in. When the timing of control signal adc_sub_p is low and the timing of control signal adc_sub_n is high, the output pulse cnt is the inverse of the input signal at input terminal in. The principle of controlling the output pulse mod by adjusting the timing of control signals adc_sub_p_mod and adc_sub_n_mod is the same as above. It is understood that those skilled in the art are fully capable of designing the timing of the control signals adc_sub_p, adc_sub_n, adc_sub_p_mod, and adc_sub_n_mod based on the above working principles and actual needs, which will not be elaborated here.

[0038] The clock phase calibration pulse generation circuit 300 is provided with an in_mod input terminal, an out_mod' output terminal, an out_mod_calib_pulse output terminal, a first clock phase calibration pulse clk_phase_calib_pulse_1 (hereinafter referred to as pulse clk_phase_calib_pulse_1) input terminal, and a clock phase calibration pulse input switch control signal sw_clk_phase_calib_pulse (hereinafter referred to as control signal sw_clk_phase_calib_pulse) input terminal, wherein both pulse clk_phase_calib_pulse_1 and control signal sw_clk_phase_calib_pulse are externally input from the ADC. The clock phase calibration pulse generation circuit 300 is used to directly output the pulse mod input from the in_mod input terminal as calibration data pulse mod_calib_pulse (hereinafter referred to as pulse mod_calib_pulse) from the out_mod_calib_pulse output terminal when clock phase calibration is not required, and as second modulation data pulse mod' (hereinafter referred to as pulse mod') from the out_mod' output terminal. When a clock phase calibration circuit 500 is provided, the clock phase calibration pulse generation circuit is also used to output a data pulse containing a clock phase calibration pulse as a pulse mod_calib_pulse from the out_mod_calib_pulse output terminal when clock phase calibration is required.

[0039] like Figure 3 As shown, the clock phase calibration pulse generation circuit 300 includes controlled double-ended switches K301, K302, and K303, and an inverter 304. In this embodiment, a high level is used as the effective value of the clock inversion control signal. Therefore, the controlled double-ended switches K301, K302, and K303 are all closed when the control input receives a high level and open when it receives a low level.

[0040] The first terminal of the controlled double-ended switch K301 is used to input the pulse mod output by the comparator output preprocessing circuit 200. The second terminal of the controlled double-ended switch K301 is electrically connected to the first terminal of the controlled double-ended switch K302, and the second terminal of the controlled double-ended switch K302 is used to output the pulse mod'. The first terminal of the controlled double-ended switch K303 is used to connect to the pulse clk_phase_calib_pulse_1. The second terminal of the controlled double-ended switch K303 is electrically connected to the second terminal of the controlled double-ended switch K301, and the second terminal of the controlled double-ended switch K303 is used to output the pulse mod_calib_pulse. The input terminal of the inverter 304 and the control terminal of the controlled double-ended switch K303 are both connected to the control signal sw_clk_phase_calib_pulse. The control terminals of the controlled double-ended switches K301 and K302 are both electrically connected to the output terminal of the inverter 304.

[0041] The working principle of the clock phase calibration pulse generation circuit 300 is as follows: when clock phase calibration is not required, the timing of the control signal sw_clk_phase_calib_pulse is low, which closes switches 301 and 302 and opens switch 303, so that the pulse mod input from the input terminal in_mod is output from the output terminals out_mod' and out_mod_calib_pulse as is, and is then processed by the subsequent circuit. When clock phase calibration is required, the timing of the control signal sw_clk_phase_calib_pulse is first set to high level, opening switches 301 and 302 and closing switch 303. Then, the pulse clk_phase_calib_pulse_1 is input, which will be output from the out_mod_calib_pulse output terminal to the subsequent circuit for processing. After the pulse clk_phase_calib_pulse_1 is generated, the timing of the control signal sw_clk_phase_calib_pulse must be restored to low level, so that the out_mod' output terminal and the out_mod_calib_pulse output terminal output the signal input from the in_mod input terminal, maintaining the normal operation of the circuit.

[0042] In the overall circuit system, the first clock phase calibration pulse and other digital timing signals driving this ADC can all be generated by a system master clock driven by a digital timing generation circuit that is different from the first ADC clock and the ADC DLL clock. In this case, it is required that the rising edge of the first clock phase calibration pulse is consistent with any rising edge of the system master clock, or that the rising or falling edges of other digital timing signals driving this ADC are kept at an integer multiple of the system master clock period.

[0043] The clock phase sampling and decoding circuit 400 is provided with an in_cnt input terminal, an in_mod_calib_pulse input terminal, an out_cnt_sync output terminal, an out_decode<(m-1):0> output terminal, a clk_adc_1 (i.e., the first ADC clock) input terminal, a clk_adcdll<0:(2^m / 2-1)> (i.e., the ADC DLL clock) input terminal, and a sampling reset signal rst_phase_sp (hereinafter referred to as the reset signal rst_phase_sp) input terminal. The first ADC clock, the ADC DLL clock, and the reset signal rst_phase_sp are all input from outside the ADC. The ADC DLL clock is input through a bus, which includes 2... m-1 A wire network (one wire corresponds to one wire network); m is an integer not less than 1; for example, when m = 3, the ADC DLL clock includes 4 wire networks. The clock phase sampling and decoding circuit 400 is used to decode the pulse mod_calib_pulse input to the in_mod_calib_pulse input terminal according to the ADC DLL clock input to the clk_adcdll<0:(2^m / 2-1)> input terminal to obtain an m-bit decoded data signal decode<(m-1):0> (hereinafter referred to as data signal decode) and output it from its out_decode<(m-1):0> output terminal; and to synchronize the pulse cnt input to the in_cnt input terminal according to the first ADC clock input to the clk_adc_1 input terminal to obtain a second counter data pulse cnt_sync (hereinafter referred to as pulse cnt_sync) and output it from its out_cnt_sync output terminal.

[0044] like Figure 4 As shown, the clock phase sampling and decoding circuit 400 includes D flip-flops U403 and U404, and a phase sampling decoder U405. The D flip-flops U404 correspond one-to-one with the wires of the ADC DLL clock bus, meaning the clock phase sampling and decoding circuit 400 includes 2... m-1Each D flip-flop U404 has a clock input connected to a first ADC clock, a data input connected to a pulse cnt, and a data output output that outputs a synchronized pulse cnt_sync. Each D flip-flop U404's clock input is connected to a pulse mod_calib_pulse, its data input is electrically connected to a network of an external ADCDLL clock bus, and its reset input is connected to an input second reset signal. Each D flip-flop U404's data output is electrically connected to an input of a phase sampling decoder U405, which processes the input 2... m-1 The bit data is decoded to obtain an m-bit data signal, which is then output through its output terminal.

[0045] When a clock phase calibration circuit 500 is provided, the clock phase sampling and decoding circuit 400 is also provided with clock input phase inverters U401 and U402. m-1 Each D flip-flop U403 has a clock input phase inverter U402 and an adcclk_phase_sel input terminal. The clock input terminal of the D flip-flop U403 is connected to the first ADC clock through the clock input phase inverter U401. The data input terminals of each D flip-flop U404 are connected to a line of the input ADC DLL clock bus through a clock input phase inverter U402. The control terminals of the clock input phase inverters U401 and each clock input phase inverter U402 are electrically connected to the adcclk_phase_sel input terminal to connect the clock inversion control signal adcclk_phase_sel (hereinafter referred to as the control signal adcclk_phase_sel). When the control signal adcclk_phase_sel is low, clock input phase inverters U401 and U402 directly output the signals input to their input terminals; when the control signal adcclk_phase_sel is high, clock input phase inverters U401 and U402 invert the signals input to their input terminals before outputting them.

[0046] The clock phase sampling and decoding circuit 400 mainly has the following two functions:

[0047] First, in the D flip-flop U403, the pulse cnt input at the input terminal in_cnt is synchronized according to the first ADC clock (when the control signal adcclk_phase_sel is high, it is the first ADC clock after inversion) to obtain the pulse cnt_sync.

[0048] Secondly, in the D flip-flop U404, the pulse mod_calib_pulse is decoded based on the phase sampling data of each line of the ADC DLL clock bus to obtain the m-bit decoded data signal decode<(m-1):0> (hereinafter referred to as the data signal decode). If the pulse mod_calib_pulse is a rising edge, the D flip-flop U404 samples and stores the level value of each line signal of the ADC DLL clock bus at the rising edge, and then outputs it to the decoder U405 for decoding, outputting the phase information of the ADC DLL clock when the D flip-flop U404 samples. This allows for sampling and decoding of comparator data and the rising edge of the calibration pulse. Alternatively, the sampled data can be cleared using the reset signal rst_phase_sp.

[0049] The first ADC clock and the ADC DLL clock have the same frequency and a duty cycle of 50%, and clk_adcdll <0> The rising edge is delayed compared to the rising edge of clk_adc. One clock cycle, clk_adcdll <1> Compared to clk_adcdll <0> Rising edge delay One clock cycle, and so on, until clk_adcdll < (2 m-1 The rising edge of -1)> is compared to clk_adcdll<(2) m-1 -2)> rising edge delay One clock cycle. Among them, clk_adcdll <0> This represents the clock signal on the first line of the ADC DLL clock bus, clk_adcdll <1> This represents the clock signal on the second line of the ADC DLL clock bus, and so on, until clk_adcdll < (2 m-1 -1) indicates the second clock bus of the ADC DLL. m-1 Clock signal on the wire network.

[0050] Table 1 shows one possible truth table for the input terminal in<0:(2^m / 2-1)> and the output terminal out<(m-1):0> of the phase sampling decoder U405.

[0051] Table 1

[0052]

[0053] The clock phase calibration circuit 500 includes an in_decode<(m-1):0> input terminal, an out_adcclk_phase_sel output terminal, a second clock phase calibration pulse clk_phase_calib_pulse_2 (hereinafter referred to as pulse clk_phase_calib_pulse_2) input terminal, and a first reset signal rst_1 (hereinafter referred to as reset signal rst_1) input terminal. The pulse clk_phase_calib_pulse_2 and the reset signal rst_1 are input from outside the ADC. The pulse clk_phase_calib_pulse_2 and the clk_phase_calib_pulse_1 in the clock phase calibration pulse generation circuit 300 can be the same signal. The reset signal rst_1 is used to clear the data stored in the clock phase calibration circuit 500.

[0054] The clock phase calibration circuit 500 is used to determine whether the phase of the ADC clock matches the phase of the low-frequency timing signal and the low-frequency clock based on the data signal decode input at the in_decode<(m-1):0> input terminal during clock phase calibration. Based on the determination result, it outputs an inverted control signal dcclk_phase_sel from its out_adcclk_phase_sel output terminal to the clock phase sampling decoding circuit 400, the data calibration circuit 600, and the counting pulse modulation circuit 800. The ADC clock includes a first ADC clock, a second ADC clock, an ADC DLL clock, and an ADC DLL data calibration clock. The low-frequency timing signal refers to all externally input control signals, and the low-frequency clock refers to other externally output clock signals besides the ADC clock. The ADC clock frequency is an integer multiple of the low-frequency clock frequency. In practical applications, low-frequency timing signals are generally generated by specific digital timing circuits, which require a low-frequency clock for driving. Therefore, we generally consider that the low-frequency clock and the low-frequency timing signal have a fixed time delay. When designing timing circuits, we generally try to make the rising and falling edges of the low-frequency timing signal coincide with the rising edge of the low-frequency clock, so that the clock phase calibration pulse has a relatively stable time delay (i.e., phase difference) with other low-frequency signals, which is of reference value in the subsequent calibration process. For example, some rising and falling edges of the pulse cnt output by the comparator output preprocessing circuit 200 are not related to data sampling, but are related to the timing of the control signal input from the external input comparator output preprocessing circuit 200. When the pulse cnt is sent to the clock phase sampling and decoding circuit 400 for synchronization, there may be cases where the rising and falling edges of the pulse cnt that are not related to data sampling overlap with the rising edge of the first ADC clock. According to the principle of D flip-flops, this situation leads to unpredictable synchronization results, which may affect the accuracy of AD conversion. Therefore, it is determined that the phase relationship between these rising and falling edges and the ADC clock is mismatched. In this case, the ADC clock is inverted so that its falling edge aligns with the rising and falling edges in the pulse cnt that are unrelated to the sampled data, thus solving the above problem. Based on the relationship between the clock phase calibration pulse and other low-frequency timing signals, the clock phase calibration function indirectly determines the phase relationship between the rising and falling edges of low-frequency timing signals and the ADCDLL clock by determining the phase relationship between the rising edge of the calibration pulse and the ADCDLL clock. After calibration, the rising and falling edges of low-frequency timing signals will no longer be aligned with the rising edge of the first ADC clock, thereby eliminating the uncertainty of the result when synchronizing with the rising and falling edges of the pulse cnt.

[0055] In this embodiment, a high level is used as the effective value of the control signal dcclk_phase_sel. When the phase of the ADC clock meets the clock synchronization requirements, the control signal dcclk_phase_sel is invalid (i.e., the control signal dcclk_phase_sel outputs a low level); otherwise, the inverting control signal is effective (i.e., the control signal dcclk_phase_sel outputs a high level). The clock phase sampling and decoding circuit 400 inverts the input first ADC clock and the ADC DLL clock, the data calibration circuit 600 inverts the input ADC DLL data calibration clock, and the counting pulse modulation circuit 800 inverts the input second ADC clock.

[0056] like Figure 5 As shown, the clock phase calibration circuit 500 generates the control signal dcclk_phase_sel as follows:

[0057] The data signal decoded output by the clock phase sampling decoding circuit 400 is sampled at the falling edge of the input pulse clk_phase_calib_pulse_2; if the sampled value is outside the third interval, the output control signal dcclk_phase_sel is valid, which in this embodiment is active high, i.e., the output control signal dcclk_phase_sel is high at this time. Otherwise, the output control signal dcclk_phase_sel is invalid (i.e., the control signal dcclk_phase_sel is low). The third interval is [2 m-2 ,(3*2 m-2 -1)].

[0058] The data calibration circuit 600 is provided with the following input terminals: in_cnt_sync, in_mod', in_decode<(m-1):0>, out_cnt_cal, adcclk_phase_sel, clk_adcdll_cal (i.e., ADCDLL data calibration clock), first calibration modulation pulse cal_mod_pulse_1 (hereinafter referred to as pulse cal_mod_pulse_1), second calibration modulation pulse cal_mod_pulse_2 (hereinafter referred to as pulse cal_mod_pulse_2), first data symbol control signal data_pos_min_sig_1 (hereinafter referred to as control signal data_pos_min_sig_1), and second reset signal rst_2 (hereinafter referred to as reset signal rst_2). The ADC DLL data calibration clock, pulse cal_mod_pulse_1, pulse cal_mod_pulse_2, control signal data_pos_min_sig_1, and reset signal rst_2 are all input from outside the ADC. The `adcclk_phase_sel` input is used to input the control signal `adcclk_phase_sel`. When the control signal `adcclk_phase_sel` is high, it inverts the ADC DLL data calibration clock to achieve clock phase calibration. The reset signal `rst_2` is used to clear the data stored in the data calibration circuit 600.

[0059] The ADC DLL data calibration clock has the same frequency as the first ADC clock, but it must have a phase difference, meaning it needs a delay compared to the first ADC clock. The clock signal of any net of the ADCDLL clock bus can be used as the ADC DLL data calibration clock; alternatively, a separate ADC DLL data calibration clock meeting the above conditions can be generated. The pulse `cal_mod_pulse_1`, determined by the pulse `cnt` and the toggle signal, is used to assign a positive or negative sign to the data to be calibrated. The pulse `cal_mod_pulse_1` toggles once between every two adjacent sampling points during the low-level period on one side of the toggle edge of the signal to be converted, and also once between every two adjacent sampling points during the high-level period on the other side of the toggle edge (no toggle occurs between adjacent low-level and high-level sampling points). This allows for the sequential accumulation of sampling values ​​during the low-level period and the high-level period by assigning positive or negative signs to the sampled values, using an addition / subtraction interval.

[0060] The data calibration circuit 600 uses the high level of the pulse mod' input at the in_mod' input terminal and the ADC DLL data calibration clock input at the clk_adcdll_cal input terminal as calibration event triggering elements. Based on the data signal decode input at the in_decode<(m-1):0> input terminal, it determines whether a specific flip edge of the pulse cnt_sync input terminal is correctly synchronized. According to the determination result, a small pulse is appended to the pulse cnt_sync to obtain the data calibration pulse cnt_cal (hereinafter referred to as pulse cnt_cal), which is output from its out_cnt_cal output terminal. The specific flip edge of the pulse cnt_sync refers to the flip edge in the pulse cnt_sync that corresponds to the flip edge of the flip pulse.

[0061] like Figure 6 As shown, the method for appending a small pulse to the pulse cnt_sync to obtain the data calibration pulse cnt_cal is as follows:

[0062] Input the pulse cnt_sync, the m-bit data signal decode, the pulse mod', the ADC DLL data calibration clock, and the control signal data_pos_min_sig_1 to the data calibration circuit. When the control signal data_pos_min_sig_1 is high, perform the following steps:

[0063] During the high level period after the rising edge of the pulse mod', the pulse cnt_sync output by the clock phase sampling decoding circuit is sampled at the first falling edge of the ADC DLL data calibration clock, and the value of the decoded data signal output by the clock phase sampling decoding circuit 400 is detected.

[0064] When the decoded value of the data signal output by the clock phase sampling and decoding circuit 400 falls within the first interval, if the sampled value of the pulse cnt_sync is high, no small pulse is appended to the pulse cnt_sync; if the sampled value of the pulse cnt_sync is low, a small pulse is appended to the pulse cnt_sync; the first interval is [3*2 m-2 ,(2 m -1)].

[0065] When the value of the decoded data signal output by the clock phase sampling and decoding circuit 400 falls within the second interval, if the sampled value of the pulse cnt_sync is high, a small pulse is appended to the pulse cnt_sync; if the sampled value of the pulse cnt_sync is low, two small pulses are appended to the pulse cnt_sync; the second interval is [0, (2... m-2 -1)].

[0066] When the value of the data signal decoded output by the clock phase sampling and decoding circuit 400 does not fall into the first interval or the second interval, a small pulse is appended to the pulse cnt_sync.

[0067] When the control signal data_pos_min_sig_1 is low, the following steps are executed:

[0068] During the high level period after the rising edge of the pulse mod', the pulse cnt_sync output by the clock phase sampling decoding circuit 400 is sampled at the first falling edge of the ADC DLL data calibration clock, and the value of the decoded data signal output by the clock phase sampling decoding circuit 400 is detected.

[0069] When the value of the data signal decoded output by the clock phase sampling and decoding circuit 400 falls within the first interval, if the sampled value of the pulse cnt_sync is high, a small pulse is appended to the pulse cnt_sync; if the sampled value of the pulse cnt_sync is low, two small pulses are appended to the pulse cnt_sync.

[0070] When the value of the data signal decoded output by the clock phase sampling and decoding circuit 400 falls in the second interval, if the sampled value of the pulse cnt_sync is high, no small pulse is added to the pulse cnt_sync; if the sampled value of the pulse cnt_sync is low, a small pulse is added to the pulse cnt_sync.

[0071] When the value of the data signal decoded output by the clock phase sampling and decoding circuit 400 does not fall into the first interval or the second interval, a small pulse is appended to the pulse cnt_sync.

[0072] When a small pulse is appended to the pulse cnt_sync, if only one small pulse is appended, the small pulse is provided by the pulse cal_mod_pulse_1. If two small pulses are appended, the first small pulse is provided by the pulse cal_mod_pulse_1 and the second small pulse is provided by the pulse cal_mod_pulse_2. The pulses cal_mod_pulse_1 and cal_mod_pulse_2 do not overlap in time, and the duration of the high level is one ADC clock cycle (the ADC clock includes the first ADC clock, the second ADC clock, the ADC DLL clock, and the ADC DLL data calibration clock, all of which have the same period).

[0073] like Figure 7aThe figure shows the timing diagram of the signals at each port of the data calibration circuit 600 in a specific example of appending a small pulse to the pulse cnt_sync. Figure 7a In the timing of the in_decode<(m-1):0> port signal (i.e., the data signal decode), the number "7" represents the number of pulses, and the letter "X" represents the indeterminate state of the signal. At this point, only the number of pulses matters, not the waveform; therefore, the waveform is directly represented as an indeterminate state. The control signal data_pos_min_sig_1 is low, indicating a negative sign for the data. The data calibration circuit 600 receives the pulse mod' and its corresponding clock-synchronized pulse cnt_sync at the in_mod and in_cnt_sync inputs, respectively. The relationship between the rising edge a of pulse mod' and the rising edge b of pulse cnt_sync, along with the ADC DLL clock phase decoding result corresponding to rising edge a (the decoding result is "7," and rising edge a occurs earlier than the adjacent ADC clock rising edge), indicates that clock synchronization is normal and does not affect data accuracy. Furthermore, by identifying that pulse cnt_sync is high at the falling edge c of the ADCDLL data calibration clock (clk_adcdll_cal port signal), the synchronized data is determined to be correct. According to the circuit logic, a high-level pulse (a high-level pulse corresponding to the rising and falling edges d) will be appended to the output signal of the out_cnt_cal port. The high-level pulse is provided by the pulse input to the cal_mod_pulse_1 port.

[0074] like Figure 7b The figure shows the timing diagram of the signals at each port of the data calibration circuit 600 in a specific example of appending two small pulses to the pulse cnt_sync. Figure 7b In the circuit, the control signal data_pos_min_sig_1 is low, indicating that the data has a negative sign. Observing the relationship between the rising edge a of the pulse mod' and the rising edge b of the pulse cnt_sync, as well as the decoding result ("7"), it can be seen that the pulse cnt_sync is delayed during clock synchronization, resulting in data errors (missing a high-level segment). Furthermore, after the falling edge c of the ADC DLL data calibration clock detects that the pulse cnt_sync is low, it is determined that the synchronization data is incorrect. According to the circuit logic, two high-level pulses (with rising and falling edges d and e, respectively) will be appended to the output signal of the out_cnt_cal port. These two high-level pulses are provided by the pulses input from the cal_mod_pulse_1 port and the cal_mod_pulse_2 port, respectively.

[0075] like Figure 7cThe figure shows the timing diagram of the signals at each port of the data calibration circuit 600 in a specific instance where no small pulse is appended to the pulse cnt_sync. Figure 7c In the circuit, the control signal data_pos_min_sig_1 is high, indicating a positive sign in the data. Observing the relationship between the rising edge a of pulse mod' and the rising edge b of pulse cnt_sync (rising edge a versus falling edge b) and the decoding result ("7"), it can be seen that the pulse cnt_sync experiences a delay during clock synchronization, leading to data errors (an extra high-level pulse). Furthermore, after the ADC DLL data calibration clock detects the high level of pulse cnt_sync at its falling edge c, it determines that the synchronization data is incorrect. According to the circuit logic, no high-level pulse is added to the output signal of the out_cnt_cal port.

[0076] The low-digit calculation circuit 700 is provided with an in_cnt_cal input terminal, an in_decode<(m-1):0> input terminal, an out_cnt_lsb_calc output terminal, an out_lsb<(m-1):0> output terminal, a first low-digit calculation modulation pulse lsb_calc_mod_pulse_1 (hereinafter referred to as pulse lsb_calc_mod_pulse_1) input terminal, a second low-digit calculation modulation pulse lsb_calc_mod_pulse_2 (hereinafter referred to as pulse lsb_calc_mod_pulse_2) input terminal, a sampling pulse lsb_calc_mod_sp (hereinafter referred to as pulse lsb_calc_mod_sp) input terminal, a second data symbol control signal data_pos_min_sig_2 (hereinafter referred to as control signal data_pos_min_sig_2) input terminal, and a third reset signal rst_3 (hereinafter referred to as reset signal rst_3) input terminal. The pulses lsb_calc_mod_pulse_1, lsb_calc_mod_pulse_2, and lsb_calc_mod_sp, the control signal data_pos_min_sig_2, and the reset signal rst_3 are all external inputs to the ADC. The requirements for the control signal data_pos_min_sig_2 are the same as those for the control signal data_pos_min_sig_1; therefore, the control signals data_pos_min_sig_2 and data_pos_min_sig_1 can be the same signal. The sampling time of the pulse lsb_calc_mod_sp is obtained by delaying the flip edge of the flip pulse. The reset signal rst_3 is used to clear the data stored in the low-order calculation circuit 700.

[0077] The low-digit calculation circuit 700 is used to perform signed accumulation on the data signal decode input to the in_decode<(m-1):0> input terminal to obtain a low-digit signal lsb that reflects the last m bits of information of the AD conversion result, and output it from its out_lsb<(m-1):0> output terminal. It also adds a small pulse to the pulse cnt_cal input to its in_cnt_cal input terminal based on the carry and borrow values ​​of the accumulation result to obtain a third counter data pulse cnt_lsb_calc (hereinafter referred to as pulse cnt_lsb_calc), and outputs it from its out_cnt_lsb_calc output terminal.

[0078] like Figure 8 As shown, the working process of the low-digit computing circuit 700 is as follows:

[0079] The accumulation period is determined, which includes all sampling points of the low level on one side of a flip edge of the signal to be converted and all sampling points of the high level on the other side of the flip edge. At the beginning of the accumulation period, the accumulated value is cleared to zero by the reset signal rst_3.

[0080] Input the data signal decode, the data calibration pulse cnt_cal, the pulse l sb_calc_mod_sp, and the control signal data_pos_min_sig_2 to the low-digit computing circuit.

[0081] When the control signal data_pos_min_sig_2 is high, the data signal decode is sampled using the pulse lsb_calc_mod_sp, and the sum of the accumulated value and the sampled value is used as the new accumulated value. If the accumulated value is greater than (2... m -1), then subtract 2 from the accumulated value. m The value after that is used as the new accumulated value, and two small pulses are appended to the pulse cnt_cal. If the accumulated value is less than or equal to (2... m If -1), the accumulated value remains unchanged, and a small pulse is appended to the pulse cnt_cal.

[0082] When the control signal data_pos_min_sig_2 is low, the data signal decode is sampled using the pulse lsb_calc_mod_sp, and the accumulated value is subtracted from the sampled value to obtain the new accumulated value. If the accumulated value is less than 0, then 2 is added to the accumulated value. m The value after the initial value is used as the new accumulated value, and no small pulse is appended to the pulse cnt_cal. If the accumulated value is greater than or equal to 0, the accumulated value remains unchanged, and a small pulse is appended to the pulse cnt_cal.

[0083] When the accumulation period ends, the accumulated value is output as the low-order bit signal lsb.

[0084] When a small pulse is appended to the pulse cnt_cal, if only one small pulse is appended, the small pulse is provided by the pulse lsb_calc_mod_pulse_2. If two small pulses are appended, the first small pulse is provided by the pulse lsb_calc_mod_pulse_2, and the second small pulse is provided by the pulse lsb_calc_mod_pulse_1. The pulses lsb_calc_mod_pulse_1 and lsb_calc_mod_pulse_2 do not overlap in time, and the duration of the high level is one ADC clock cycle.

[0085] like Figure 9 The figure shows the timing diagram of the signals at each port of the low-digit computing circuit 700 in a specific example. Figure 9 In the timing of the in_decode<(m-1):0> port signal (i.e., the data signal decode) and the out_lsb<2:0> port signal (i.e., the low-order bit signal lsb), the numbers (e.g., "0", "2", "3", "5", "6") represent the number of pulses, and the letter "X" represents the indeterminate state of the signal. For simplicity, it is assumed that the pulse cnt_cal input to the low-order bit calculation circuit 700 does not cause a calibration event in the data calibration circuit 600. That is, each data pulse input to the in_cnt_cal port only carries an additional high-level small pulse, and the decoding operation of the ADC DLL clock is performed on its rising edge.

[0086] First, the low-digit calculation circuit 700 is reset using the reset signal rst_3, at which point the accumulated value (i.e., the data at the out_lsb<2:0> port) is cleared to zero. In this embodiment, subtraction, addition, and repetition are performed sequentially for a total of three calculations. The control signal data_pos_min_sig_2 is set low to perform the first subtraction calculation. After the pulse cnt_cal and its rising edge decoding result are input from the in_decode<2:0> port, the pulse lsb_calc_mod_sp is input high to sample the data signal decode. At the same time, the subtraction calculation is performed between the out_lsb<2:0> terminal (i.e., the accumulated value) and the data sampled from in_decode<2:0> (i.e., the sampled value), i.e., 0-6=-6. Since the result is negative, according to the logic of this circuit, an additional 8 needs to be added (in this embodiment, m=3, 2). m =2 3=8), then the final calculation result is -6+8=2, and no additional high-level pulse is added to the out_cnt_lsb_calc port. That is, the pulses input to the lsb_calc_mod_pulse_1 and lsb_calc_mod_pulse_2 ports will not be output to the out_cnt_lsb_calc port. At this time, the signal input to the in_cnt_cal port will be output by the out_cnt_lsb_calc port as is, that is, the pulse cnt_cal is directly output as the pulse cnt_lsb_calc.

[0087] The second addition is then performed. The control signal `data_pos_min_sig_2` is set high, and the above process and circuit logic are repeated to complete the calculation 2 + 3 = 5. In addition to outputting the signal received by the `in_cnt_calc` port, the `out_cnt_lsb_calc` port also adds an extra high-level pulse. In this example, this high-level pulse is provided by the signal input to the `lsb_calc_mod_pulse_2` port. The third addition is then performed, keeping the control signal `data_pos_min_sig_2` high, and the above process and circuit logic are repeated to complete the calculation 5 + 5 = 10. Since the result is greater than or equal to 8, 8 needs to be subtracted, so the final result is 10 - 8 = 2. Two extra high-level pulses are added to the `out_cnt_lsb_calc` port. In this example, the second high-level pulse is provided by the signal input to the `lsb_calc_mod_pulse_1` port.

[0088] Thus, in this embodiment, a 3-bit LSB addition and subtraction calculation is completed using the low-bit calculation circuit, i.e., -6+3+5=2, and the carry-over function of the high-bit part is realized by adding a small high-level pulse to the relevant signal.

[0089] The counting pulse modulation circuit 800 is provided with an in_cnt_lsb_calc input terminal, an out_cnt_pulse output terminal, and a clk_adc_2 (second ADC clock) input terminal. The second ADC clock and the first ADC clock in the clock phase sampling and decoding circuit 400 can be the same signal. The counting pulse modulation circuit 800 is used to convert the third counter data pulse cnt_lsb_calc (hereinafter referred to as pulse cnt_lsb_calc) input to the in_cnt_lsb_calc input terminal into a multi-segment high-frequency clock pattern cnt_pulse based on the second ADC clock input to the clk_adc_2 input terminal.

[0090] like Figure 10As shown, the counting pulse modulation circuit 800 includes a D flip-flop U801, an inverter U802, and an AND gate U803. The data input terminal of the D flip-flop U801 is connected to the data pulse cnt_lsb_calc used by the third counter. The clock input terminal of the D flip-flop U801 and the input terminal of the inverter U802 are both connected to the second ADC clock. The output terminals of the D flip-flop U801 and the inverter U802 are electrically connected to the two input terminals of the AND gate U803, respectively. The output terminal of the AND gate U803 is used to output high-frequency pulses in multiple high-frequency clock patterns.

[0091] When a clock phase calibration circuit 500 is provided, the counting pulse modulation circuit 800 also includes a clock input phase inverter U804 and an adcclk_phase_sel input terminal. The clock input terminal of the D flip-flop U801 and the input terminal of the inverter U802 are both connected to the second ADC clock via the clock input phase inverter U804. The control terminal of the clock input phase inverter U804 is electrically connected to the adcclk_phase_sel input terminal to connect the control signal adcclk_phase_sel. When the control signal adcclk_phase_sel is low, the clock input phase inverter U804 directly outputs the signal input to its input terminal; when the control signal adcclk_phase_sel is high, the clock input phase inverter U804 inverts the signal input to its input terminal before outputting it, thereby achieving the clock phase calibration function.

[0092] The circuit works as follows: the pulse cnt_lsb_calc input from the in_cnt_lsb_calc input terminal is synchronized with the clock of the D flip-flop U801, and then further modulated by the second ADC clock in the AND gate U803 of the secondary stage; the resulting high-frequency pulse cnt_pulse is input to the counter circuit 900 of the subsequent stage.

[0093] The counter circuit 900 is equipped with an in_cnt_pulse input terminal and an out_msb<(n-1):m> output terminal. The counter circuit 900 counts the high-frequency pulse cnt_pulse input to the in_cnt_pulse input terminal, obtaining the high-digit signal msb representing the information of each bit from the m-th to the n-th bit of the AD conversion result, and outputting it from its out_msb<(n-1):m> output terminal. n is the total number of bits after AD conversion. One high-level pulse of the high-frequency pulse cnt_pulse represents one count. Completing the counting of all pulses within one cycle completes one round of high (nm) bit AD conversion. Combining the high-digit signal msb and the low-digit signal lsb yields the complete AD conversion result.

[0094] like Figure 11 The figure shows the timing diagram of key signals of a one-way ramp ADC in a specific example of a complete AD conversion process. In the figure, the black area of ​​the waveform at the "out_cnt_pulse" port represents a very dense pulse. In this example, a round of four-sample correlated multiple sampling will be performed. The general principle of AD conversion in correlated multiple sampling is as follows:

[0095] The ADC receives a reset level (i.e., a low level, denoted as V) from the preceding circuitry within one AD conversion cycle. rst ) and valid signal level (i.e., high level, denoted as V) sig ), to obtain (V sig -V rst The value of the input ramp (i.e., the net value of the signal) is converted and its digital value is output. Let the DC base level of the input ramp be V. base Used to compare V rst The peak voltage of the small ramp is V rst_pk To obtain (V) under four sampling conditions sig -V rst ),have:

[0096] [(V rst_pk -V rst1 )+(V rst_pk -V rst2 )+(V rst_pk -V rst3 )+(V rst_pk -V rst4 )]

[0097] +[(V sig1 -V base )+(V sig2 -V base )+(V sig3 -V base )+(V sig4 -V base )]

[0098] =(V sig1 +V sig2 +V sig3 +V sig4 )-(V rst1 +V rst2 +V rst3 +V rst4 )+4*(V rst_pk -V base )

[0099] Among them, V rst1 V rst2 V rst3 V rst4 Indicates Vrst The values ​​obtained from four samplings; V sig1 V sig2 V sig3 V sig4 Indicates V sig The values ​​obtained during four samplings; the flipping of the output of comparator 100 at the moment when the input ramp signal and the signal to be converted overlap can be considered as the occurrence of one sampling event. The [(V] appearing in the above formula... sig1 +V sig2 +V sig3 +V sig4 )-(V rst1 +V rst2 +V rst3 +V rst4 ]] is the net signal value after correlation multisampling, since 4*(V rst_pk -V base ) is a fixed value that can be removed in subsequent processing. Therefore, the pulse duration can be generated during the conversion process, and (V) is a constant. rst_pk -V rst1 ), (V sig1 -V base The high-level pulse corresponding to the value of ) etc. (e.g. Figure 11 The waveform corresponding to the "out_cnt" port is converted into a high-speed pulse form that the counter can use (such as...). Figure 11 The waveform corresponding to the "out_cnt_pulse" port is sequentially input into the counter circuit 900 to perform addition calculations, thereby achieving the effect of the above formula.

[0100] Because ADC performs equivalent calculations such as (V) rst_pk -V rst1 ), (V sig1 -V base The duration of the high-level pulses corresponding to the pulses is calculated by subtracting the rising edge of the pulse from the falling edge. Therefore, the rising edge of the pulse waveform corresponding to the "out_cnt" port is marked with a negative sign and the falling edge with a positive sign, which serves as a reference for the timing calculation of control signals such as data_pos_min_sig_1 required for the lower 3 bits in the design of the circuit based on the ADC DLL clock.

[0101] exist Figure 11In the waveform display of the "out_msb<15:3>" port, the high-order conversion result is 6560 (binary 11001 1010 0000), and the low-order three-order conversion result of the "out_lsb<2:0>" port is 4 (binary 100). Combining these two results, the final four-sample binary result is 1100 1101 0000 0100, which is 52484 in decimal. Figure 11 The waveform corresponding to out<15:0> in the code. If a 14-bit result is needed, the lowest two bits of the binary result can be removed later, resulting in decimal 13121.

[0102] In this embodiment, the AD conversion of the n-bit output ADC is divided into two parts: one part is obtained by counting the counting pulses generated by the comparator and processed by the secondary circuit to obtain the AD conversion results of bits (n-1) to m; the other part is obtained by counting the 2 at certain times when the comparator outputs flip. m-1 Phase sampling of ADC clock signals with fixed phase differences is performed. After secondary circuit processing, multiple phase sampling results are accumulated with signs. This yields the AD conversion results from bit (m-1) to bit 0, while simultaneously reflecting the accumulated carry / reduction digits in a counting pulse. The two sets of output conversion results are then concatenated to obtain the n-bit digital output from bit (n-1) to bit 0. By converting the discrete-time process of ADC clock phase sampling into a continuous process of accumulation and counting, a combination of correlation multiple sampling technology based on multiple sampling and accumulation counting and ADC clock speed-up technology based on multiple fixed-phase-difference ADC clocks is achieved in the single-slope ADC architecture. This is beneficial for improving the sampling accuracy, speed, and noise performance of the single-slope ADC. Furthermore, this embodiment uses data calibration and clock phase calibration to mitigate conversion errors caused by ADC clock errors in data sampling, further improving the accuracy of AD conversion.

[0103] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A unidirectional ramp ADC, characterized in that: include A comparator is used to compare the signal to be converted with a ramp signal to obtain and output a flip pulse; The comparator output preprocessing circuit is used to convert the effective flip edge of the comparator output flip pulse into a rising edge, obtain and output the first modulation data pulse, and output the first counter data pulse. A clock phase calibration pulse generation circuit is used to directly output the first modulation data pulse as the calibration data pulse and the second modulation data pulse when clock phase calibration is not required. The clock phase sampling and decoding circuit is used to decode the calibration data pulses according to the externally input ADC DLL clock to obtain an m-bit decoded data signal, and to synchronize the data pulses of the first counter according to the externally input first ADC clock to obtain the data pulses of the second counter. The data calibration circuit is used to take the high level of the second modulation data pulse and the ADC DLL data calibration clock as calibration event triggering elements, determine whether the flip edge of the second counter data pulse is synchronized with the flip edge of the flip pulse according to the m-bit decoded data signal, and add a corresponding number of small pulses to the second counter data pulse according to the determination result to obtain and output the data calibration pulse. The low-bit calculation circuit is used to perform signed accumulation on the m-bit decoded data signal to obtain a low-bit signal that reflects the last m bits of information of the AD conversion result, and to add a corresponding number of small pulses to the data calibration pulse according to the carry and borrow values ​​of the accumulation result to obtain the data pulse for the third counter. The counting pulse modulation circuit is used to convert the data pulses of the third counter into high-frequency pulses of a multi-segment high-frequency clock pattern according to the externally input second ADC clock. as well as The counter circuit is used to count the high-frequency pulses obtained by the counting pulse modulation circuit to obtain a high-digit signal that reflects the information of the m-th bit and the bits before the m-th bit of the AD conversion result.

2. The unidirectional ramp ADC according to claim 1, characterized in that: The positive input terminal of the comparator is connected to a ramp signal, and the negative input terminal is connected to the signal to be converted. The ramp signal and each low level and each high level of the signal to be converted have at least one intersection point. The minimum level of the ramp signal is less than the minimum value of the low level of the signal to be converted. The maximum value of the ramp signal during the low level of the signal to be converted is greater than the maximum value of the low level of the signal to be converted. The maximum value of the ramp signal during the high level of the signal to be converted is greater than the maximum value of the high level of the signal to be converted.

3. The unidirectional ramp ADC according to claim 1, characterized in that: The comparator output preprocessing circuit includes AND gates U201, U202, U203, and U204, an inverter 205, an OR gate 206, and an OR gate 207; the second input terminals of AND gates U201 and U203, as well as the input terminal of inverter 205, are electrically connected to the output terminal of the comparator, and the second input terminals of AND gates U202 and U204 are electrically connected to the output terminal of inverter 205. The first input terminal of AND gate U201 is connected to the external input counter data pulse to output a control signal in positive phase, and the first input terminal of AND gate U202 is connected to the external input counter data pulse to output a control signal in negative phase; the output terminals of AND gates U201 and U202 are respectively electrically connected to the two input terminals of OR gate 206, and the output terminal of OR gate 206 is used to output the first counter data pulse; The first input terminal of AND gate U203 is connected to the externally input modulation data pulse to output a positive-phase control signal, and the first input terminal of AND gate U204 is connected to the externally input modulation data pulse to output a negative-phase control signal; the output terminals of AND gate U203 and AND gate U204 are respectively electrically connected to the two input terminals of OR gate 207, and the output terminal of OR gate 207 is used to output the first modulation data pulse.

4. The unidirectional ramp ADC according to claim 1, characterized in that: The clock phase sampling and decoding circuit includes D flip-flops U403 and 2. m-1 A D flip-flop U404 and a phase sampling decoder U405 are used. The clock input of the D flip-flop U403 is connected to the externally input first ADC clock, the data input of the D flip-flop U403 is connected to the data pulse for the first counter, and the data output of the D flip-flop U403 is used to output the synchronized data pulse for the second counter. The clock input terminal of each of the aforementioned D flip-flops U404 is connected to the calibration data pulse output from the clock phase calibration pulse generation circuit. The data input terminal of each of the aforementioned D flip-flops U404 is respectively connected to one line network of the externally input ADC DLL clock bus, wherein the ADC DLL clock bus includes 2 m-1 The network consists of a line network, where m is an integer greater than or equal to 1; the reset input terminal of each of the D flip-flops U404 is connected to the input second reset signal, and the data output terminal of each of the D flip-flops U404 is electrically connected to one input terminal of the phase sampling decoder U405. The output terminal of the phase sampling decoder U405 is used to output the decoded m-bit decoded data signal.

5. The unidirectional ramp ADC according to claim 1, characterized in that: The method for obtaining a data calibration pulse by appending a small pulse to the data pulse of the second counter is as follows: Input the second counter data pulse, the m-bit decoded data signal, and the second modulation data pulse to the input terminal of the data calibration circuit. Input the ADC DLL data calibration clock and the first data symbol control signal from the outside to the control terminal of the data calibration circuit. When the first data symbol control signal is high, perform the following steps: During the high level period after the rising edge of the second modulation data pulse, the second counter output by the clock phase sampling decoding circuit is sampled by the data pulse at the first falling edge of the ADC DLL data calibration clock, and the value of the m-bit decoded data signal output by the clock phase sampling decoding circuit is detected. When the value of the m-bit decoded data signal output by the clock phase sampling decoding circuit falls within the first interval, if the sampled value of the second counter using the data pulse is high, no small pulse is added to the second counter using the data pulse; if the sampled value of the second counter using the data pulse is low, a small pulse is added to the second counter using the data pulse; the first interval is [3*2 m-2 ,(2 m -1)]; When the value of the m-bit decoded data signal output by the clock phase sampling decoding circuit falls within the second interval, if the sampled value of the second counter using the data pulse is high, then a small pulse is appended to the second counter using the data pulse; if the sampled value of the second counter using the data pulse is low, then two small pulses are appended to the second counter using the data pulse; the second interval is [0, (2... m-2 -1)]; When the value of the m-bit decoded data signal output by the clock phase sampling decoding circuit does not fall into the first interval and the second interval, a small pulse is added to the data pulse of the second counter. When the first data symbol control signal is low, the following steps are executed: During the high level period after the rising edge of the second modulation data pulse, the second counter output by the clock phase sampling decoding circuit is sampled by the data pulse at the first falling edge of the ADC DLL data calibration clock, and the value of the m-bit decoded data signal output by the clock phase sampling decoding circuit is detected. When the value of the m-bit decoded data signal output by the clock phase sampling decoding circuit falls within the first interval, if the sampled value of the second counter using the data pulse is high, then a small pulse is added to the second counter using the data pulse; if the sampled value of the second counter using the data pulse is low, then two small pulses are added to the second counter using the data pulse. When the value of the m-bit decoded data signal output by the clock phase sampling decoding circuit falls into the second interval, if the sampled value of the second counter data pulse is high, no small pulse is added to the second counter data pulse; if the sampled value of the second counter data pulse is low, a small pulse is added to the second counter data pulse. When the value of the m-bit decoded data signal output by the clock phase sampling decoding circuit does not fall into the first interval or the second interval, a small pulse is added to the data pulse of the second counter.

6. The unidirectional ramp ADC according to claim 1, characterized in that: The operation of the low-digit computing circuit includes the following steps: The accumulation period is determined, which includes all sampling points of the low level on one side of a flip edge of the signal to be converted and all sampling points of the high level on the other side of the flip edge. At the beginning of the accumulation period, the accumulated value is cleared to zero. The input terminal of the low-digit computing circuit is fed with an m-bit decoded data signal and a data calibration pulse, and the control terminal of the low-digit computing circuit is fed with a sampling pulse and a second data symbol control signal from the outside. When the second data symbol control signal is high, the m-bit decoded data signal is sampled by a sampling pulse, and the sum of the accumulated value and the sampled value is used as the new accumulated value; if the accumulated value is greater than (2 m -1), then subtract 2 from the accumulated value. m The value after that is used as the new accumulated value, and two small pulses are appended to the data calibration pulse; if the accumulated value is less than or equal to (2 m If -1), the accumulated value remains unchanged, and a small pulse is appended to the data calibration pulse; When the second data symbol control signal is low, the m-bit decoded data signal is sampled by a sampling pulse, and the accumulated value is subtracted from the sampled value to obtain the new accumulated value; if the accumulated value is less than 0, then the accumulated value is added by 2. m The value after the initial value is used as the new accumulated value, and no small pulse is appended to the data calibration pulse; if the accumulated value is greater than or equal to 0, the accumulated value remains unchanged, and a small pulse is appended to the data calibration pulse. When the accumulation period ends, the accumulated value is output as the low-order bit signal.

7. The unidirectional ramp ADC according to claim 1, characterized in that: The counting pulse modulation circuit includes a D flip-flop U801, an inverter U802, and an AND gate U803. The data input terminal of the D flip-flop U801 is connected to the data pulse for the third counter. The clock input terminal of the D flip-flop U801 and the input terminal of the inverter U802 are both connected to the externally input second ADC clock. The output terminals of the D flip-flop U801 and the inverter U802 are electrically connected to the two input terminals of the AND gate U803, respectively. The output terminal of the AND gate U803 is used to output high-frequency pulses in multiple high-frequency clock patterns.

8. A unidirectional ramp ADC according to any one of claims 1 to 7, characterized in that: The clock phase calibration pulse generation circuit is also used to output a data pulse containing a clock phase calibration pulse as a calibration data pulse when clock phase calibration is required. The unidirectional ramp ADC also includes a clock phase calibration circuit. The clock phase calibration circuit is used to determine whether the phase of the ADC clock matches the phase of the low-frequency timing signal and the low-frequency clock based on the m-bit decoded data signal during clock phase calibration, and outputs an inverting control signal based on the determination result. If they match, the clock inverting control signal is invalid; otherwise, when the inverting control signal is valid, the ADC clock is inverted. The ADC clock includes a first ADC clock, a second ADC clock, an ADC DLL clock, and an ADC DLL data calibration clock.

9. A unidirectional ramp ADC according to claim 8, characterized in that: The clock phase calibration pulse generation circuit includes a controlled double-ended switch K301, a controlled double-ended switch K302, a controlled double-ended switch K303, and an inverter 304. The first terminal of the controlled double-ended switch K301 is connected to the first modulation data pulse output by the comparator output preprocessing circuit. The second terminal of the controlled double-ended switch K301 is electrically connected to the first terminal of the controlled double-ended switch K302. The second terminal of the controlled double-ended switch K302 is used to output the second modulation data pulse. The first terminal of the controlled double-ended switch K303 is used to connect to the input first clock phase calibration pulse, the second terminal of the controlled double-ended switch K303 is electrically connected to the second terminal of the controlled double-ended switch K301, and the second terminal of the controlled double-ended switch K303 is used to output calibration data pulse; The input terminal of the inverter 304 and the control terminal of the controlled double-ended switch K303 are both connected to the input clock phase calibration pulse input switch control signal. The control terminals of the controlled double-ended switches K301 and K302 are both electrically connected to the output terminal of the inverter 304.

10. A unidirectional ramp ADC according to claim 8, characterized in that, The method by which the clock phase calibration circuit generates the clock inversion control signal is as follows: The m-bit decoded data signal output by the clock phase sampling decoding circuit is sampled at the falling edge of the input second clock phase calibration pulse; if the sampled value is outside the third interval, the output clock inversion control signal is valid, and the third interval is [2]. m-2 (3*2) m-2 -1)].

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