Semiconductor structure manufacturing methods and semiconductor structures
By forming grooves in the word line grooves and giving them a raised structure, the contact area between the word lines and the active structure is increased, which solves the leakage problem caused by the reduction in line width in dynamic random access memory and improves the performance of the device.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2023-04-23
- Publication Date
- 2026-07-17
AI Technical Summary
During the process of shrinking the product linewidth of dynamic random access memory, leakage current is prone to occur in the device, especially due to the short-channel effect caused by the shortening of the channel length of the unit transistor.
By forming a grooved character line structure in the character line groove, which has a raised structure, the contact area between the character line structure and the active structure is increased, the channel length is increased, and the leakage phenomenon is improved.
The increased channel length improved leakage current caused by the short channel effect and enhanced word line control capability.
Smart Images
Figure CN116600564B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor manufacturing technology, and in particular to a method for manufacturing a semiconductor structure and a semiconductor structure. Background Technology
[0002] Dynamic Random Access Memory (DRAM) is a type of semiconductor memory that primarily works by using the amount of charge stored in a capacitor to represent whether a binary bit is 1 or 0.
[0003] To improve the integration density of dynamic random access memory (DRAM) and accelerate device operation, the product linewidth of DRAM is continuously shrinking to meet these requirements. However, this shrinking linewidth also affects other performance aspects of the device, particularly increasing the likelihood of leakage current. Summary of the Invention
[0004] This disclosure provides a method for manufacturing a semiconductor structure, which aims to improve leakage current in the semiconductor structure.
[0005] According to some embodiments of this disclosure, an embodiment of this disclosure provides a method for manufacturing a semiconductor structure, comprising: providing a substrate, the substrate including an array of active structures and a stacked structure spaced apart, the stacked structure penetrating the active structures in a horizontal direction, the stacked structure including a first sacrificial layer and a second sacrificial layer alternately stacked along the thickness direction of the substrate; removing the first sacrificial layer to expose a portion of the active structures; etching the exposed portion of the active structures using the second sacrificial layer as a mask to form a plurality of grooves spaced apart from each other along the thickness direction of the substrate; removing the second sacrificial layer to form word line trenches having the grooves; forming word line structures within the word line trenches, the word line structures having protrusion structures located within the grooves.
[0006] In some embodiments, providing a substrate includes: providing a substrate, the substrate including an array of first active portions and a first isolation structure between the first active portions; and sequentially forming a stacked structure, a second active portion, and a second isolation structure on the substrate, wherein the second active portion is located on the first active portion, the second isolation structure is located on the first isolation structure, the stacked structure extends through the second active portion and the second isolation structure along the horizontal direction, and the first active portion and the second active portion constitute the active structure.
[0007] In some embodiments, the step of sequentially forming a stacked structure, a second active portion, and a second isolation structure on the substrate includes: forming a stacked layer on the substrate, the stacked layer including a first sacrificial film and a second sacrificial film alternately stacked along the thickness direction; etching the first sacrificial film and the second sacrificial film along the thickness direction to form a plurality of mutually spaced isolation trenches in the stacked layer, the remaining stacked layer between adjacent isolation trenches serving as the stacked structure; performing an epitaxial process on the first active portion to form a second active portion on the first active portion in the plurality of isolation trenches; and forming a second isolation structure on the first isolation structure in the plurality of isolation trenches.
[0008] In some embodiments, providing the substrate includes: providing a substrate including an array of initial active portions and initial isolation structures located between the initial active portions; forming a plurality of stacked structures spaced apart in the substrate, with the remaining initial active portions serving as active structures.
[0009] In some embodiments, the step of forming the plurality of stacked structures includes: forming a plurality of initial trenches spaced apart in the substrate, the initial trenches penetrating the active structure in a horizontal direction; forming a first sacrificial film in the plurality of initial trenches; removing a portion of the height of the first sacrificial film from the plurality of initial trenches, the remaining first sacrificial film serving as a first sacrificial layer; forming a second sacrificial film on the first sacrificial layer in the plurality of initial trenches; removing a portion of the height of the second sacrificial film from the plurality of initial trenches, the remaining second sacrificial film serving as a second sacrificial layer; and cyclically forming the first sacrificial layer and the second sacrificial layer in the plurality of initial trenches to form the plurality of stacked structures.
[0010] In some embodiments, the first sacrificial film covers the bottom and sidewalls of the plurality of initial trenches, and removing the first sacrificial film from the plurality of initial trenches of a certain height includes: forming a mask layer on the first sacrificial film that fills the plurality of initial trenches; using the mask layer as a mask, wet etching to remove the first sacrificial film on the sidewalls of the plurality of initial trenches; and removing the mask layer.
[0011] In some embodiments, removing the first sacrificial layer includes: etching through the stacked structure along the thickness direction to form a word line trench in the stacked structure, the word line trench exposing portions of the first sacrificial layer and the second sacrificial layer; and removing the first sacrificial layer along the word line trench.
[0012] In some embodiments, forming a word line structure within the word line trench includes: forming a gate dielectric layer on the inner wall of the word line trench; depositing a conductive material on the surface of the gate dielectric layer to fill the word line trench; removing the conductive material outside the word line trench, retaining the conductive material located within the word line trench as a conductive layer; etching back a portion of the conductive layer; forming a dielectric layer on the remaining conductive layer, wherein the dielectric layer and the remaining conductive layer fill the word line trench, and the gate dielectric layer, conductive layer, and dielectric layer constitute the word line structure.
[0013] According to some embodiments of this disclosure, this disclosure also provides a semiconductor structure, including: a substrate, the substrate including an array of active structures and an isolation structure located between the active structures; a word line trench, the word line trench penetrating the active structures in a horizontal direction, and the word line trench including a first word line trench located in the active structures and a second word line trench located in the isolation structure; the sidewall of the first word line trench has a plurality of grooves spaced apart from each other along the thickness direction of the substrate; a word line structure, the word line structure being located within the word line trench, the word line structure having a protrusion structure located within the groove.
[0014] In some embodiments, the plurality of grooves are spaced apart from each other at equal intervals along the thickness direction of the substrate.
[0015] In some embodiments, the sidewall of the second character line groove is perpendicular to the upper surface of the substrate; the minimum width of the character line structure located in the first character line groove is the same as the width of the character line structure located in the second character line groove; the width of the character line structure located in the first character line groove at the protrusion structure is greater than the width of the character line structure located in the second character line groove.
[0016] In some embodiments, the word line structure includes: a gate dielectric layer located on the surface of the word line trench; a gate dielectric layer located on the surface of the first word line trench; a conductive layer and a dielectric layer filling the word line trench, wherein the conductive layer and the dielectric layer are stacked sequentially.
[0017] The technical solution provided by the embodiments of this disclosure has at least the following advantages: In the semiconductor structure manufacturing method provided by the embodiments of this disclosure, by forming a word line trench with grooves, the word line structure formed in the word line trench also has a corresponding protruding structure, thereby increasing the contact area between the word line structure and the active structure, increasing the channel length, and improving the leakage phenomenon caused by the short channel effect. Attached Figure Description
[0018] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0019] Figures 1 to 7 This is a schematic diagram of the various steps corresponding to a semiconductor structure manufacturing method provided in an embodiment of this disclosure;
[0020] Figure 8 yes Figure 1 The top view corresponding to the structural schematic diagram shown;
[0021] Figure 9 yes Figure 7 The top view corresponding to the structural schematic diagram shown;
[0022] Figures 10 to 13 This is a schematic diagram of the structure of each step included in a step of providing a substrate according to an embodiment of the present disclosure;
[0023] Figures 14 to 21 This is a structural schematic diagram of the various steps included in a step of providing a substrate according to another embodiment of this disclosure. Detailed Implementation
[0024] As is known from the background technology, as the product linewidth of dynamic random access memory (DRAM) continues to shrink, it will also affect other performance aspects of the device itself, especially making the device prone to leakage.
[0025] Analysis revealed that the reason for the above phenomenon is that as the product linewidth of dynamic random access memory (DRAM) continues to shrink, the channel length of the memory's cell transistors also shrinks, resulting in a certain short-channel effect and causing leakage.
[0026] This disclosure provides a method for manufacturing a semiconductor structure. By forming a word line trench with grooves, the word line structure formed in the word line trench also has a corresponding protruding structure, thereby increasing the contact area between the word line structure and the active structure, increasing the channel length, and improving the leakage phenomenon caused by the short-channel effect.
[0027] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.
[0028] Figures 1-7 This is a schematic diagram of the various steps corresponding to a semiconductor structure manufacturing method provided in an embodiment of the present disclosure.
[0029] refer to Figure 1 A substrate 100 is provided, comprising an array of active structures 101 and spaced-apart stacked structures 102. The stacked structures 102 include a first sacrificial layer 112 and a second sacrificial layer 122 alternately stacked along the thickness direction of the substrate 100. Figure 1 The z-direction is shown. (Reference) Figure 8 , Figure 8 yes Figure 1 The top view corresponding to the structural schematic diagram shown, that is... Figure 8 The cross-sectional diagram at point bb is as follows Figure 1 The structural diagram shown is illustrated below. Figure 8 As shown, the stacked structure 102 penetrates the active structure 101 in a horizontal direction, and the horizontal direction is... Figure 8 The x-direction is shown in the diagram.
[0030] refer to Figure 3 Remove the first sacrificial layer 112 to expose part of the active structure 101.
[0031] refer to Figure 4 The exposed active structure 101 is etched using the second sacrificial layer 122 as a mask to form a plurality of grooves 114 spaced apart from each other along the thickness direction of the substrate 100.
[0032] refer to Figure 5 Remove the second sacrificial layer 122 to form a letter groove 104 with a recess 114;
[0033] refer to Figure 7 A character line structure is formed within the character line groove 104, and the character line structure has a protrusion structure 116 located within the groove 114.
[0034] In the semiconductor structure manufacturing method provided in this embodiment, by forming a word line trench 104 with a groove 114, the word line structure formed in the word line trench 104 also has a corresponding protrusion structure 116, thereby increasing the contact area between the word line structure and the active structure 101, increasing the channel length, and improving the leakage phenomenon caused by the short-channel effect. Moreover, when this semiconductor structure is used as a dynamic random access memory, the corresponding word line control capability can be improved.
[0035] The first sacrificial layer 112 and the second sacrificial layer 122 are made of different materials. By selecting different materials for the first sacrificial layer 112 and the second sacrificial layer 122, different etching rates can be achieved under the same etching conditions. For example, in this embodiment, the etching rate of the first sacrificial layer 112 is made greater than the etching rate of the second sacrificial layer 122, so that the first sacrificial layer 112 is removed while the second sacrificial layer 122 is retained.
[0036] In some embodiments, the material of the first sacrificial layer 112 may be polysilicon. The material of the second sacrificial layer 122 may be any one of silicon nitride, silicon oxide, silicon oxynitride, and silicon carbide. The material of the isolation structure 103 may be silicon oxide. The material of the active structure 101 may be silicon. It should be noted that if the material of the first sacrificial layer 112 is polysilicon and the material of the active structure 101 is silicon, since polysilicon and silicon have similar etching selectivity, after removing the first sacrificial layer 112, the active structure 101 can be etched directly along the gap left after removing the first sacrificial layer 112, using the same etching solution as when etching the first sacrificial layer 112. In one embodiment, when the material of the first sacrificial layer 112 is polysilicon and the material of the active structure 101 is silicon, the etching solution for etching the first sacrificial layer 112 and the active structure 101 may be a mixture containing nitric acid (HNO3) and hydrofluoric acid (HF).
[0037] In one embodiment, removing the first sacrificial layer 112 includes: referencing Figure 2 Along the thickness direction, etching is performed through the stacked structure 102 to form word line trenches 104 in the stacked structure 102, the word line trenches 104 exposing a portion of the first sacrificial layer 112 and the second sacrificial layer 122; the first sacrificial layer 112 is removed along the word line trenches 104.
[0038] Specifically, the first sacrificial layer 112 can be removed by wet etching. Since the materials of the first sacrificial layer 112 and the second sacrificial layer 122 are different, by selecting an etching solution with different etching rates for the first sacrificial layer 112 and the second sacrificial layer 122, the first sacrificial layer 112 can be removed by etching at a faster etching rate.
[0039] In one embodiment, a word line structure is formed within the word line groove 104, as referenced. Figures 6-7 The method includes: forming a gate dielectric layer 105 on the inner wall of the word line trench 104; depositing a conductive material on the surface of the gate dielectric layer 105 to fill the word line trench 104; removing the conductive material outside the word line trench 104 and retaining the conductive material inside the word line trench 104 as a conductive layer 106; etching back a portion of the conductive layer 106; forming a dielectric layer 107 on the remaining conductive layer 106, wherein the dielectric layer 107 and the remaining conductive layer 106 fill the word line trench 104, and the gate dielectric layer 105, the conductive layer 106 and the dielectric layer 107 constitute a word line structure.
[0040] In one embodiment, the gate dielectric layer 105 can be directly grown on the active structure 101 by thermal oxidation. In other embodiments, the gate dielectric layer 105 can also be directly deposited on the active structure 101 by atomic layer deposition. In this embodiment, the gate dielectric layer 105 can be silicon oxide. In some other embodiments, a high-k dielectric material (dielectric constant K greater than 7) can be used instead of the silicon oxide material. Commonly used high-k dielectric materials include Ta2O5, TiO2, Al2O3, Pr2O3, La2O3, LaAlO3, HfO2, ZrO2, or other metal oxides of different compositions.
[0041] Continue to refer to Figure 1 The substrate 100 may further include an isolation structure 103 for isolating the active structure 101 from the surrounding environment. The substrate 100 also includes isolation trenches (not shown) located in the substrate 100, and the isolation structure 103 is an isolation material filled in the isolation trenches.
[0042] In one embodiment, reference is made to... Figure 10 and Figure 13 Provides substrate 100, including: reference Figure 10 A substrate 100' is provided, the substrate 100' including an array of first active portions 111 and a first isolation structure 113 between the first active portions 111; Reference Figure 13 A stacked structure 102, a second active portion 121, and a second isolation structure 123 are sequentially formed on a substrate 100'. The second active portion 121 is located on the first active portion 111, and the second isolation structure 123 is located on the first isolation structure 113. The stacked structure 102 extends horizontally through the second active portion 121 and the second isolation structure 123. The first active portion 111 and the second active portion 121 constitute the active structure 101.
[0043] refer to Figures 11 to 13 A stacked structure 102, a second active portion 121, and a second isolation structure 123 are sequentially formed on a substrate 100', including: a reference Figure 11 A stacked layer 102' is formed on a substrate 100', the stacked layer 102' including a first sacrificial film 112' and a second sacrificial film 122' alternately stacked along the thickness direction; Reference Figure 12 The first sacrificial film 112' and the second sacrificial film 122' are etched along the thickness direction to form a plurality of spaced-apart isolation trenches 132 in the stacked layer 102', and the remaining stacked layer 102' between adjacent isolation trenches 132 serves as the stacked structure 102; Reference Figure 13 An epitaxial process is performed on the first active portion 111 to form a second active portion 121 on the first active portion 111 in the plurality of isolation trenches 132; and a second isolation structure 123 is formed on the first isolation structure 113 in the plurality of isolation trenches 132.
[0044] It should be noted that, in one embodiment, the width of the isolation trench 132 can be set according to the epitaxial process. For example, to avoid fluctuations in process conditions during the process that could cause the formed second active portions 121 to short-circuit in the horizontal direction, the width of the isolation trench 132 can be appropriately increased as needed. Alternatively, in other embodiments, the horizontal width of the stacked structure 102 located on the first isolation structure 113 can be reduced. Alternatively, in other embodiments, after the epitaxial process, wet etching is performed on the top protection of the second active portions 121 to remove the portion of the second active portions 121 that is short-circuited in the horizontal direction. Alternatively, an alternating epitaxial and etching process can be used to avoid short-circuiting of the second active portions 121 in the horizontal direction.
[0045] Specifically, substrate 100' may include, but is not limited to, semiconductor substrates such as silicon substrates, epitaxial silicon substrates, silicon-germanium substrates, or silicon-coated insulating substrates. Since the second active portion 121 is formed from the first active portion 111 through an epitaxial process, the first active portion 111 and the second active portion 121 have the same lattice arrangement. The first sacrificial film 112' and the second sacrificial film 122' can be deposited on substrate 100' using any one of chemical vapor deposition, physical vapor deposition, and atomic layer deposition processes. After the second active portion 121 has grown to a certain height epitaxially, the second isolation structure 123 can be formed on the first isolation structure 113 using an atomic layer deposition process. The second isolation structure 123 also fills the gap between the second active portion 121 and the stacked structure 102.
[0046] In one embodiment, the method of forming a plurality of spaced-apart isolation trenches 132 may include: forming a hard mask layer on a stacked layer 102', then coating a layer of photoresist on the hard mask layer, then defining a pattern for forming the isolation trenches 132 on the photoresist by exposure and development, then transferring the pattern on the photoresist to the hard mask layer, and then using the patterned hard mask layer as a mask to etch the stacked layer 102' to form the isolation trenches 132.
[0047] In one embodiment, the hard mask layer includes an organic mask material layer and a hard mask material layer stacked together. The organic mask material layer is typically formed using a carbon-containing organic material; the hard mask material layer is formed using one or more of silicon nitride, silicon oxynitride, silicon carbonitride, metal nitride, metal oxide, and metal carbide, preferably silicon nitride (SiN), because silicon nitride has advantages such as easy availability, low cost, and mature manufacturing methods.
[0048] In another embodiment, reference Figure 14 and Figure 1 Provides substrate 100, including: reference Figure 14 A substrate 100' is provided, the substrate 100' including an array of initial active portions 101' and initial isolation structures 103' located between the initial active portions 101'; Reference Figure 1 Multiple stacked structures 102 are formed in the substrate 100' at intervals, and the remaining initial active portion 101' serves as the active structure 101.
[0049] The 102 steps for forming multiple stacked structures include: (Refer to...) Figure 15 A plurality of initial trenches 108 are formed in the substrate 100' at intervals, and the initial trenches 108 penetrate the active structure 101 in a horizontal direction; Reference Figure 16 A first sacrificial membrane 112' is formed in multiple initial trenches 108; Reference Figure 18 The first sacrificial membrane 112' in a plurality of initial trenches 108 of a certain height is removed, and the remaining first sacrificial membrane 112' serves as the first sacrificial layer 112; Reference Figure 19 A second sacrificial film 122' is formed on the first sacrificial layer 112 in a plurality of initial trenches 108; Reference Figure 21 The second sacrificial membrane 122' in a plurality of initial trenches 108 with a portion of its height is removed, and the remaining second sacrificial membrane 122' serves as the second sacrificial layer 122; the first sacrificial layer 112 and the second sacrificial layer 122 are cyclically formed in the plurality of initial trenches to form a structure as shown in the figure. Figure 1 The multiple stacked structures 102 shown.
[0050] refer to Figure 16The first sacrificial membrane 112' covers the bottom and sidewalls of the plurality of initial trenches 108. In one embodiment, removing the first sacrificial membrane 112' from a portion of the height of the plurality of initial trenches 108 includes: referencing Figure 17 A mask layer 109 is formed on the first sacrificial film 112' to fill the plurality of initial trenches 108; the first sacrificial film 112' on the sidewalls of the plurality of initial trenches 108 is removed by wet etching using the mask layer 109 as a mask; and the mask layer 109 is removed.
[0051] Specifically, the material of the mask layer 109 is different from the material of the first sacrificial film 112', and the first sacrificial film 112' can be etched using an etching solution that has a strong selectivity for the first sacrificial film 112'. By controlling the etching time, the corresponding etching depth can be controlled. Due to the masking effect of the mask layer 109, the first sacrificial film 112' located at the bottom of the initial trench 108 will not be etched. Therefore, during the etching process, the first sacrificial film 112' will be etched along the thickness direction, that is, the first sacrificial film 112' on the sidewall of the initial trench 108 will be etched away, while the first sacrificial film 112' located at the bottom of the multiple initial trenches 108 will remain.
[0052] It should be noted that when the first sacrificial film 112' is formed in the plurality of initial trenches 108, the first sacrificial film 112' is also formed on the active structure 101. In one embodiment, after a mask layer 109 filling the plurality of initial trenches 108 is formed on the first sacrificial film 112', the first sacrificial film 112' formed on the active structure 101 can be removed by a chemical mechanical polishing process, so as... Figure 17 As shown, the first sacrificial film 112' covers only the bottom and sidewalls of the plurality of initial trenches 108. In other embodiments, the first sacrificial film 112' can be etched directly after a mask layer 109 filling the plurality of initial trenches 108 is formed on the first sacrificial film 112', thereby removing the first sacrificial film 112' formed on the active structure 101 first.
[0053] refer to Figure 19 The second sacrificial membrane 122' covers the sidewalls of the plurality of initial trenches 108 and the first sacrificial layer 112. In one embodiment, removing the second sacrificial membrane 122' from a portion of the height of the plurality of initial trenches 108 includes: referencing Figure 20 A mask layer 110 is formed on the second sacrificial film 122' to fill the plurality of initial trenches 108; the second sacrificial film 122' on the sidewalls of the plurality of initial trenches 108 is removed by wet etching using the mask layer 110 as a mask; and the mask layer 110 is removed.
[0054] Specifically, the material of the mask layer 110 is different from the material of the second sacrificial film 122', and the second sacrificial film 122' can be etched using an etching solution that has a strong selectivity for the second sacrificial film 122'. By controlling the etching time, the corresponding etching depth can be controlled. Due to the masking effect of the mask layer 110, the second sacrificial film 122' located on the first sacrificial film 112' will not be etched. Therefore, during the etching process, the second sacrificial film 122' will be etched along the thickness direction, that is, the second sacrificial film 122' on the sidewall of the initial trench 108 will be etched away, while the second sacrificial film 122' located on the first sacrificial film 112' will remain.
[0055] It should be noted that when the second sacrificial film 122' is formed on the first sacrificial layer 112 in the plurality of initial trenches 108, the second sacrificial film 122' is also formed on the active structure 101. In one embodiment, after a mask layer 110 filling the plurality of initial trenches 108 is formed on the second sacrificial film 122', the second sacrificial film 122' formed on the active structure 101 can be removed by a chemical mechanical polishing process, as follows: Figure 20 As shown, the second sacrificial film 122' covers only the sidewalls of the plurality of initial trenches 108 and the first sacrificial layer 112. In other embodiments, the second sacrificial film 122' can be etched directly after a mask layer 110 filling the plurality of initial trenches 108 is formed on the second sacrificial film 122', thereby removing the second sacrificial film 122' formed on the active structure 101 first.
[0056] According to some embodiments of this disclosure, this disclosure also provides a semiconductor structure that can be formed by the manufacturing method described above. (See reference...) Figure 7 The semiconductor structure includes a substrate 100, which includes an array of active structures 101 and isolation structures 103 located between the active structures 101. (Reference) Figure 5 The semiconductor structure also includes a word line trench 104 that extends horizontally through the active structure 101. The word line trench 104 includes a first word line trench 1041 located in the active structure 101 and a second word line trench 1042 located in the isolation structure. The sidewall of the first word line trench 1041 has a plurality of recesses 114 spaced apart from each other along the thickness direction of the substrate 100. The semiconductor structure also includes a word line structure located within the word line trench 104, and the word line structure has a protrusion structure 116 located within the recesses 114.
[0057] In the semiconductor structure provided in this embodiment, by designing the word line structure, the word line structure located in the groove 114 also has a corresponding protrusion structure 116, which increases the contact area between the word line structure and the active structure 101, increases the channel length, and improves the leakage phenomenon caused by the short-channel effect. Moreover, when this semiconductor structure is used as a dynamic random access memory, the corresponding word line control capability can be improved.
[0058] In some embodiments, reference Figure 5 The bottom and sidewalls of the groove 114 can be flat. In other embodiments, the bottom and / or sidewalls of the groove 114 can be curved, so that the corresponding protrusion 116 forms a structural profile with an arcuate shape, which can avoid leakage current caused by the tip effect. In the corresponding manufacturing method, the shape of the formed groove 114 can be controlled by controlling the etching conditions, such as the etching time of the active structure 101 and the composition of the etching solution.
[0059] In some embodiments, a plurality of grooves 114 are spaced apart from each other at equal intervals along the thickness direction of the substrate 100.
[0060] In some embodiments, the spacing between two adjacent grooves 114 gradually increases along the thickness direction of the substrate 100. In the corresponding manufacturing method, the thickness of each second sacrificial layer 122 formed can be controlled such that the thickness of each second sacrificial layer 122 gradually decreases from the top layer to the bottom layer, thereby causing the spacing between two adjacent grooves 114 to gradually increase. Figure 5 The sidewall of the second letter groove 1042 is perpendicular to the upper surface of the base 100; Reference Figure 9 The minimum width of the character line structure located in the first character line groove 1041 is the same as the width of the character line structure located in the second character line groove 1042, both being d1; (Reference) Figure 9 The width d2 of the character line structure at the protrusion in the first character line groove 1041 is greater than the width d1 of the character line structure in the second character line groove.
[0061] In some embodiments, reference Figure 7 The word line structure includes: a gate dielectric layer 105, which is located on the surface of the first word line trench 104; a conductive layer 106 and a dielectric layer 107, which fill the word line trench 104 and are stacked sequentially.
[0062] In one embodiment, the conductive layer 107 may include a metal material layer. In this embodiment, the metal material layer includes one or more metal materials with good electrical conductivity, such as tungsten, cobalt, manganese, niobium, nickel, and molybdenum.
[0063] In some other embodiments, the conductive layer 107 includes a stacked metal material layer and a semiconductor conductive material layer. In this embodiment, the semiconductor conductive material layer is made of any one or any combination of polysilicon, silicon germanide, gallium arsenide, gallium phosphide, cadmium sulfide, and zinc sulfide. The semiconductor conductive material layer and the metal material layer together constitute a double-function gate. This embodiment effectively solves the gate-induced drain-leakage problem by setting stacked conductive layers. For example, the structure of polysilicon and tungsten layers stacked together can reduce the gate-induced drain-leakage current.
[0064] Furthermore, the conductive layer 107 may also include an equipotential dielectric layer between the metal material layer and the semiconductor conductive material layer. This equipotential dielectric layer acts as a metal barrier layer 500 to prevent the conductive material in the metal material layer from diffusing into the semiconductor conductive material layer, while simultaneously connecting the metal material layer and the semiconductor conductive material layer to form an equipotential interface, thereby improving device performance. In this embodiment, any one or any combination of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride can be used to form the equipotential dielectric layer.
[0065] In some embodiments, the word line structure further includes a metal barrier layer (not shown) located between the gate dielectric layer 105 and the conductive layer 106. In this embodiment, the metal barrier layer prevents conductive material in the conductive layer 106 from diffusing to the gate dielectric layer 105, thereby affecting the performance of the gate dielectric layer. Furthermore, the metal barrier layer also enhances the adhesion between the conductive layer 106 and the gate dielectric layer 105.
[0066] In this embodiment, the semiconductor structure also includes a source / drain structure (not shown in the figure), wherein the overlapping area of the source / drain structure and the word line structure is offset from the area where the protrusion structure is located, thereby reducing the gate-induced drain current through a thicker gate dielectric layer 105. Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail can be made without departing from the spirit and scope of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure should be determined by the scope defined in the claims.
Claims
1. A method for manufacturing a semiconductor structure, characterized in that, include: A substrate is provided, the substrate comprising an array of active structures and a stacked structure arranged at intervals, the stacked structure extending through the active structures in a horizontal direction, the stacked structure comprising a first sacrificial layer and a second sacrificial layer alternately stacked along the thickness direction of the substrate; Remove the first sacrificial layer to expose part of the active structure; The exposed portion of the active structure is etched using the second sacrificial layer as a mask to form a plurality of grooves spaced apart from each other along the thickness direction of the substrate; Remove the second sacrificial layer to form a letter groove with the aforementioned recess; A character line structure is formed within the character line groove, and the character line structure has a protrusion structure located within the groove.
2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The provided substrate includes: A substrate is provided, the substrate including an array of first active portions and a first isolation structure between the first active portions; A stacked structure, a second active portion, and a second isolation structure are sequentially formed on the substrate, with the second active portion located on the first active portion and the second isolation structure located on the first isolation structure. The stacked structure extends through the second active portion and the second isolation structure along the horizontal direction, and the first active portion and the second active portion constitute the active structure.
3. The method for manufacturing a semiconductor structure according to claim 2, characterized in that, The step of sequentially forming a stacked structure, a second active portion, and a second isolation structure on the substrate includes: A stacked layer is formed on the substrate, the stacked layer comprising a first sacrificial film and a second sacrificial film alternately stacked along the thickness direction; The first sacrificial film and the second sacrificial film are etched along the thickness direction to form a plurality of mutually spaced isolation trenches in the stacked layers, and the remaining stacked layers between adjacent isolation trenches constitute the stacked structure; The first active portion is subjected to an epitaxial process to form the second active portion on the first active portion in the plurality of isolation trenches; The second isolation structure is formed on the first isolation structure in the plurality of isolation trenches.
4. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The provided substrate includes: A substrate is provided, the substrate comprising an initial active portion arranged in an array and an initial isolation structure located between the initial active portions; Multiple stacked structures are formed in the substrate at intervals, with the remaining initial active portion serving as the active structure.
5. The method for manufacturing a semiconductor structure according to claim 4, characterized in that, The steps for forming the plurality of stacked structures include: A plurality of initial trenches are formed in the substrate at intervals, the initial trenches penetrating the active structure in a horizontal direction; A first sacrificial membrane is formed in the plurality of initial trenches; The first sacrificial membrane in the plurality of initial trenches of a certain height is removed, and the remaining first sacrificial membrane serves as the first sacrificial layer. A second sacrificial film is formed on the first sacrificial layer in the plurality of initial trenches; The second sacrificial membrane in the plurality of initial trenches of a certain height is removed, and the remaining second sacrificial membrane serves as the second sacrificial layer. The first sacrificial layer and the second sacrificial layer are formed in the plurality of initial trenches in a cycle to form the plurality of stacked structures.
6. The method for manufacturing a semiconductor structure according to claim 5, characterized in that, The first sacrificial membrane covers the bottom and sidewalls of the plurality of initial trenches, and removing the first sacrificial membrane from the plurality of initial trenches at a certain height includes: A mask layer is formed on the first sacrificial membrane to fill the plurality of initial trenches; Using the mask layer as a mask, the first sacrificial film on the sidewalls of the plurality of initial trenches is removed by wet etching; Remove the mask layer.
7. The method for manufacturing a semiconductor structure according to any one of claims 1-6, characterized in that, Removing the first sacrificial layer includes: Along the thickness direction, etching is performed through the stacked structure to form word line trenches in the stacked structure, the word line trenches exposing portions of the first sacrificial layer and the second sacrificial layer; The first sacrificial layer is removed along the word line groove.
8. The method for manufacturing a semiconductor structure according to any one of claims 1-6, characterized in that, The process of forming a character line structure within the character line groove includes: A grid dielectric layer is formed on the inner wall of the word line groove; A conductive material is deposited on the surface of the gate dielectric layer to fill the word line trench; Remove the conductive material outside the word line groove, and retain the conductive material inside the word line groove as a conductive layer; The conductive layer described in the etched portion; A dielectric layer is formed on the remaining conductive layer, and the dielectric layer and the remaining conductive layer fill the word line trench. The gate dielectric layer, the conductive layer, and the dielectric layer constitute the word line structure.
9. A semiconductor structure, characterized in that, include: The substrate includes an array of active structures and isolation structures located between the active structures; The word line groove extends horizontally through the active structure, and the word line groove includes a first word line groove located in the active structure and a second word line groove located in the isolation structure. The first character line groove has a plurality of grooves spaced apart from each other along the thickness direction of the substrate on its sidewall, and the sidewall of the second character line groove is perpendicular to the upper surface of the substrate. The character line structure is located within the character line groove. The character line structure has a protrusion located within the groove. The minimum width of the character line structure located in the first character line groove is the same as the width of the character line structure located in the second character line groove. The width of the character line structure located in the first character line groove at the protrusion is greater than the width of the character line structure located in the second character line groove.
10. The semiconductor structure according to claim 9, characterized in that, Along the thickness direction of the substrate, the plurality of grooves are spaced apart from each other at equal intervals.
11. The semiconductor structure according to any one of claims 9-10, characterized in that, The word line structure includes: A gate dielectric layer, the gate dielectric layer being located on the surface of the first word line trench; A conductive layer and a dielectric layer, the conductive layer and the dielectric layer filling the word line trench, and the conductive layer and the dielectric layer being stacked sequentially.