Display panel and manufacturing method thereof

Abstract

The display panel provided by the application comprises a substrate and a mesh structure, the substrate has a display area; the mesh structure is located on one side of the substrate and at least in the display area, the mesh structure comprises a plurality of first signal lines and a plurality of second signal lines which are arranged in a cross manner and electrically connected; at least one signal line in the plurality of first signal lines and the plurality of second signal lines comprises a plurality of wire segments which are located in different film layers and electrically connected through vias. The first signal line and / or the second signal line in the mesh structure is arranged to alternately extend in different film layers, thereby avoiding short circuit with other wires. In this way, when the number of film layers used for arranging the signal lines in the display panel is small, the mesh structure with mutual connection can still be formed, the flexibility of the wire in the display panel is improved, and the working performance of the display panel is ensured.

Description

Technical Field

[0001] This application relates to the field of display technology, and more specifically, to a display panel and a method for manufacturing the display panel. Background Technology

[0002] Currently, the two main display technologies are liquid crystal displays (LCDs) and organic light-emitting diodes (OLEDs). OLEDs, due to their self-emissive nature, can be made thinner and lighter, and also feature low power consumption, high contrast, and high response speed. OLEDs are current-driven devices, requiring corresponding pixel circuits in the display panel. These pixel circuits contain multiple transistors that work together to drive the OLEDs.

[0003] Organic light-emitting diode (OLED) display panels typically consist of three or four metal layers, which are isolated from each other by insulating layers. The manufacturing cost of these display panels is relatively high, and their manufacturing efficiency is relatively low. Summary of the Invention

[0004] In order to overcome the above-mentioned shortcomings in the prior art, the purpose of this application is to provide a display panel, comprising:

[0005] The substrate has a display area;

[0006] A mesh structure is located on one side of the substrate and at least in the display area. The mesh structure includes multiple first signal lines and multiple second signal lines that are arranged in a cross pattern and electrically connected. At least one of the multiple first signal lines and multiple second signal lines includes multiple trace segments located in different film layers and electrically connected through vias.

[0007] In some possible implementations, the display panel further includes an active layer, a first conductive layer, and a second conductive layer stacked on one side of the substrate; an insulating layer is disposed between the active layer, the first conductive layer, and the second conductive layer.

[0008] The first signal line is located in the second conductive layer. The second signal line includes a first trace segment and a second trace segment arranged along the extension direction of the second signal line, located in different film layers, and electrically connected through vias. The first trace segment is located in the second conductive layer. The second trace segment is located in the first conductive layer or an active layer. The first signal line is connected to the first trace segment or electrically connected to the second trace segment through vias.

[0009] The orthographic projection of the first trace segment on the substrate overlaps with the orthographic projection of part of the active layer on the substrate.

[0010] In some possible implementations, the display panel further includes multiple third signal lines located on one side of the substrate and at least in the display area; the multiple third signal lines are intersected and insulated from multiple second signal lines, the orthographic projection of the third signal lines on the substrate overlaps with the orthographic projection of the second trace segments on the substrate, and the third signal lines are located in the second conductive layer;

[0011] Optionally, the third signal line includes one or more of data lines and power lines; the third signal line extends along a first direction and is arranged along a second direction, and the first direction and the second direction intersect.

[0012] Optionally, at least one of the multiple first signal lines and multiple second signal lines includes multiple trace segments arranged along their own extension direction, located in different film layers, and electrically connected through vias.

[0013] In some possible implementations, multiple first signal lines extend along a first direction and are arranged along a second direction, and multiple second signal lines extend along a second direction and are arranged along a first direction, with the first and second directions intersecting.

[0014] Optionally, the first signal line extends along a first direction in one or more combinations of a straight line, a curve, or a broken line; the second signal line extends along a second direction in one or more combinations of a straight line, a curve, or a broken line.

[0015] In some possible implementations, the mesh structure includes a first mesh structure, in which the first signal line and the second signal line are initialization voltage lines;

[0016] The display panel also includes multiple pixel units located on one side of the substrate and in the display area; each pixel unit includes a driving transistor, a light-emitting device, and at least one initialization transistor. The initialization transistor is electrically connected to a first signal line and a second signal line. The initialization transistor is used to initialize at least one of the gate, source, and drain of the driving transistor and / or the light-emitting device.

[0017] Optionally, the pixel unit includes a first initialization transistor and a second initialization transistor. The first initialization transistor is used to initialize the gate of the driving transistor; the second initialization transistor is used to initialize the light-emitting device; at least one of the first initialization transistor and the second initialization transistor is electrically connected to the first signal line and the second signal line in the first mesh structure; the initialization voltage for initializing the gate of the driving transistor is different from the initialization voltage for initializing the light-emitting device.

[0018] In some possible implementations, the first mesh structure includes an insulated first sub-mesh structure and a second sub-mesh structure, wherein the first signal line and the second signal line in the first sub-mesh structure are connected to a first initialization voltage; the first signal line and the second signal line in the second sub-mesh structure are connected to a second initialization voltage; the first initialization voltage and the second initialization voltage are different.

[0019] The first initialization transistor is electrically connected to the first signal line and the second signal line in the first sub-mesh structure, and the second initialization transistor is electrically connected to the first signal line and the second signal line in the second sub-mesh structure.

[0020] Optionally, the first signal line in the first sub-mesh structure and the first signal line in the second sub-mesh structure extend along a first direction and are alternately arranged along a second direction; the second signal line in the first sub-mesh structure and the second signal line in the second sub-mesh structure extend along a second direction and are alternately arranged along a first direction; the first direction and the second direction intersect.

[0021] Optionally, the first signal line in the adjacent first sub-mesh structure and the first signal line in the second sub-mesh structure are located on both sides of a column of pixel units; the second signal line in the adjacent first sub-mesh structure and the second signal line in the second sub-mesh structure are located on both sides of a row of pixel units, and the column of pixel units is arranged along a first direction; the row of pixel units is arranged along a second direction.

[0022] In some possible implementations, the mesh structure includes a second mesh structure, in which the first and second signal lines are power lines.

[0023] In some possible implementations, the display panel further includes an active layer, a first conductive layer, and a second conductive layer stacked on one side of the substrate; an insulating layer is disposed between the active layer, the first conductive layer, and the second conductive layer.

[0024] In the second mesh structure, the first signal line is located in the second conductive layer. The second signal line includes multiple first trace segments and multiple second trace segments located in different film layers and electrically connected through vias. The first trace segments are located in the second conductive layer and connected to the first signal line. The second trace segments are located in the first conductive layer or the active layer.

[0025] The display panel also includes a first scan line, a data line, and multiple pixel units, each pixel unit including a driving transistor and a data writing transistor;

[0026] The first scan line is electrically connected to the gate of the data writing transistor. The data line is connected to the driving transistor via the data writing transistor. The data writing transistor is used to transmit the data voltage on the data line to the driving transistor in response to the first scan signal on the first scan line.

[0027] In the second mesh structure, the orthographic projection of multiple second trace segments in the second signal line connected to a row of pixel units onto the substrate is located on opposite sides of the orthographic projection of the first scan line onto the substrate along the first direction.

[0028] In some possible implementations, the pixel unit also includes a capacitor that is electrically connected to the gate of the driving transistor;

[0029] The capacitor includes a first plate and a second plate. The first plate is multiplexed as the gate of a driving transistor and is located in the first conductive layer. The second plate is located in the second conductive layer and is electrically connected to the first signal line in the second mesh structure.

[0030] Optionally, a notch is provided on one of the two opposite sides of the first electrode plate along the second direction. In three adjacent pixel units in the same row, the notch of the middle first electrode plate is opposite to the notch of the first electrode plate on one side and opposite to the notch of the first electrode plate on the other side. At least one second trace segment of the second signal line in the second mesh structure is located between the notches of the adjacent first electrode plates with opposite notches.

[0031] Optionally, two adjacent pixel units in the same row can be arranged in a mirror-symmetric configuration.

[0032] In some possible implementations, the pixel unit further includes a light-emitting control transistor and a light-emitting device, and the display panel further includes a light-emitting control line located in the first conductive layer; the light-emitting control line is electrically connected to the gate of the light-emitting control transistor; the light-emitting control transistor, the driving transistor, the power supply line, and the light-emitting device are connected in series, and the first electrode is located between the light-emitting control line and the first scan line;

[0033] Optionally, at least one second trace segment of the second signal line in the second mesh structure is located between the light emission control line and the first scan line;

[0034] Optionally, the pixel unit further includes a first initialization transistor, and the display panel further includes a second scan line. The first initialization transistor is used to initialize the gate of the driving transistor. The gate of the first initialization transistor is electrically connected to the second scan line. The second scan line is located in the first conductive layer, and at least one second trace segment of the second signal line in the second mesh structure is located between the second scan line and the first scan line.

[0035] Optionally, the pixel unit further includes a second initialization transistor for initializing the light-emitting device; an initialization voltage line extending along the second direction and electrically connected to the second initialization transistor is located between the first scan line and the second scan line.

[0036] The mesh structure also includes a first mesh structure, wherein at least a portion of the first signal lines and second signal lines in the first mesh structure are electrically connected to the second initialization transistor; the second signal lines in the first mesh structure that are electrically connected to the second initialization transistor are located between the second scan lines and the second signal lines in the second mesh structure.

[0037] Optionally, in three adjacent columns of pixel units, two data lines, two power lines extending along the first direction, and an initialization voltage line extending along the first direction and electrically connected to the first initialization transistor are provided between two adjacent columns of pixel units, and a first signal line in the first mesh structure electrically connected to the second initialization transistor is provided between the other two adjacent columns of pixel units.

[0038] In some possible implementations, the display panel further includes a light-emitting device layer, which includes a first electrode layer, a light-emitting functional layer, and a second electrode layer stacked sequentially in a direction away from the substrate, and the film layer containing the mesh structure is located between the light-emitting device layer and the substrate.

[0039] Optionally, only two conductive layers are disposed between the light-emitting device layer and the substrate;

[0040] Optionally, the first conductive layer is located between the active layer and the second conductive layer.

[0041] In some possible implementations, the display panel further includes a plurality of pixel units arranged in an array; the active layers in at least one column of pixel units are continuously disposed, and the arrangement direction of the column of pixel units is parallel to the extension direction of the first signal line.

[0042] Another object of this application is to provide a method for manufacturing a display panel, comprising:

[0043] A patterned active layer is formed on a substrate, and the substrate has a display area;

[0044] A patterned first conductive layer is formed on the active layer.

[0045] The active layer is subjected to a doping process;

[0046] A patterned second conductive layer is formed on the first conductive layer;

[0047] The mesh structure is formed by at least one of a first conductive layer and an active layer, and a second conductive layer. The mesh structure is located on one side of the substrate and at least in the display area. The mesh structure includes multiple first signal lines and multiple second signal lines that are arranged in a cross pattern and electrically connected. At least one of the multiple first signal lines and multiple second signal lines includes multiple trace segments located in different film layers and electrically connected through vias.

[0048] Compared with the prior art, this application has the following beneficial effects:

[0049] This application provides a display panel and a method for manufacturing the display panel, wherein at least one of the first signal line and the second signal line in the mesh structure is arranged to extend alternately in different film layers, thereby avoiding cross-short circuits with other traces. In this way, even with a small number of film layers used for setting signal lines in the display panel, an interconnected mesh structure can be formed, reducing line impedance, ensuring the uniformity of the specific DC voltage provided to each pixel unit, improving the flexibility of the traces in the display panel, and thus ensuring the working performance of the display panel.

[0050] Furthermore, in the display panel provided in this embodiment, by using the above-mentioned mesh structure to transmit the initialization voltage and / or power supply voltage, the initialization voltage lines and / or power supply lines of the mesh structure can be formed even when the number of metal layers in the display panel is small, thereby reducing the line impedance and ensuring the uniformity of the initialization voltage and / or power supply voltage provided to each pixel unit, thus ensuring the working performance or display effect of the display panel. Attached Figure Description

[0051] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0052] Figure 1 This is one of the schematic diagrams of the film layer structure of the display panel provided in this embodiment;

[0053] Figure 2 This is one of the top views of the wiring layout of the display panel provided in this embodiment;

[0054] Figure 3 This is a second top view of the wiring layout of the display panel provided in this embodiment;

[0055] Figure 4 This is the third top view of the wiring layout of the display panel provided in this embodiment;

[0056] Figure 5 This is one of the circuit connection diagrams for the pixel unit provided in this embodiment;

[0057] Figure 6 This is the second schematic diagram of the circuit connection of the pixel unit provided in this embodiment;

[0058] Figure 7 This is the fourth top view of the wiring layout of the display panel provided in this embodiment;

[0059] Figure 8 This is the fifth top view of the wiring arrangement of the display panel provided in this embodiment;

[0060] Figure 9 This is the sixth top view of the wiring arrangement of the display panel provided in this embodiment;

[0061] Figure 10 Seventh top view of the wiring layout of the display panel provided in this embodiment;

[0062] Figure 11 This is the eighth top view schematic diagram of the wiring arrangement of the display panel provided in this embodiment;

[0063] Figure 12 This is the ninth top view of the wiring layout of the display panel provided in this embodiment;

[0064] Figure 13 This is the tenth top view schematic diagram of the wiring arrangement of the display panel provided in this embodiment;

[0065] Figure 14 This is eleventh top view of the wiring layout of the display panel provided in this embodiment;

[0066] Figure 15 This is the twelfth top view of the wiring arrangement of the display panel provided in this embodiment;

[0067] Figure 16 This is the thirteenth top view schematic diagram of the wiring arrangement of the display panel provided in this embodiment;

[0068] Figure 17 Fourteenth top view of the wiring arrangement of the display panel provided in this embodiment;

[0069] Figure 18 This is the fifteenth top view schematic diagram of the wiring arrangement of the display panel provided in this embodiment;

[0070] Figure 19 This is the second schematic diagram of the cross-sectional structure of the film layer of the display panel provided in this embodiment;

[0071] Figure 20 Sixteenth top view of the wiring layout of the display panel provided in this embodiment;

[0072] Figure 21 This is a flowchart illustrating the steps of the method for manufacturing the display panel provided in this embodiment;

[0073] Figure 22 This is one of the schematic diagrams of the electronic device provided in this embodiment.

[0074] Icons: 10-Substrate; 20-Active Layer; 30-First Insulating Layer; 40-First Conductive Layer; 50-Second Insulating Layer; 60-Second Conductive Layer; 70-Planarization Layer; 81-First Electrode Layer; 82-Light Emitting Layer; 83-Second Electrode Layer; 84-Pixel Delineation Layer; 310-First Signal Line; 210-Second Signal Line; 600-Via; 211-First Trace Segment; 212-Second Trace Segment; D1-First Direction; D2-Second Direction; 110-First Semiconductor Trace Segment; 320-Third Signal Line; 700-Pixel Unit; AA-Display Area; NA-Non-Display Area. Detailed Implementation

[0075] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0076] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0077] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0078] In the description of this application, it should be noted that the terms "center," "upper," "lower," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of the invention is in use. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. In addition, the terms "first," "second," and "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0079] It should be noted that, where there is no conflict, different features in the embodiments of this application can be combined with each other.

[0080] In some display panels, a solution of reducing the number of metal layers is adopted to reduce manufacturing costs or improve manufacturing efficiency. However, reducing the number of metal layers may result in the inability to set up certain traces that could otherwise be staggered in different metal layers, affecting the working performance or display effect of the display panel.

[0081] For example, in a display panel with multiple metal layers, in order to ensure that each driving unit receives a uniform reset initialization voltage, the traces that provide the initialization voltage (Vref) are set as a mesh.

[0082] Specifically, taking a display panel with three or four metal layers as an example, the scan signal traces, gate electrodes, etc., are located in the first metal layer; the laterally extending initialization voltage traces are located in the second metal layer; and the vertically extending initialization voltage traces, data signal traces, drive voltage (Vdd) traces, etc., are located in the third metal layer. The initialization voltage traces of the second and third metal layers are electrically connected through vias penetrating the insulating layer. In this way, the laterally extending initialization voltage traces in the second metal layer will not be too close to the active layer, nor will they cross and short-circuit with the vertical traces in the third metal layer.

[0083] However, in display panels with only two metal layers, the reduced number of metal layers means there are no horizontally extending initialization voltage traces, affecting the uniformity of the initialization voltage obtained by each driving unit, which may in turn affect the display effect of the display panel.

[0084] In view of this, this embodiment provides a solution that can ensure the working performance of the display panel while reducing the number of trace film layers in the display panel. The solution provided in this embodiment will be described in detail below.

[0085] This embodiment provides a display panel, which includes a substrate 10 and a mesh structure.

[0086] The substrate 10 may include a display area AA. Optionally, the substrate 10 may also include a non-display area NA surrounding at least a portion of the display area AA. The substrate may include a rigid substrate, for example, the material of the substrate may include sapphire or glass; or the substrate may also include a flexible substrate, for example, the material of the substrate may include polyimide (PI), which is not specifically limited in this embodiment.

[0087] The mesh structure is located on one side of the substrate 10 and at least in the display area AA. The mesh structure includes multiple first signal lines 310 and multiple second signal lines 210 that are arranged in a cross pattern and electrically connected.

[0088] At least one of the multiple first signal lines 310 and multiple second signal lines 210 includes multiple trace segments located in different film layers and electrically connected through vias. For example, at least one of the multiple first signal lines 310 and multiple second signal lines 210 includes multiple trace segments arranged along their own extension direction, located in different film layers, and electrically connected through vias. When some trace segments of the first signal lines 310 and the second signal lines 210 are located in the same film layer, they can be directly connected in that film layer, forming an integral structure. When some trace segments of the first signal lines 310 and the second signal lines 210 overlap in different film layers, they can be electrically connected through vias. For example, the first signal line 310 includes multiple trace segments arranged along its own extension direction, located in different film layers, and electrically connected through vias, and / or, the second signal line 210 includes multiple trace segments arranged along its own extension direction, located in different film layers, and electrically connected through vias.

[0089] Optionally, multiple first signal lines 310 extend along a first direction D1 and are arranged along a second direction D2, and multiple second signal lines 210 extend along the second direction D2 and are arranged along the first direction D1, wherein the first direction D1 and the second direction D2 intersect. Optionally, the first direction D1 and the second direction D2 are perpendicular.

[0090] Optionally, the first signal line 310 extends along a first direction in one or more combinations of a straight line, a curve, and a broken line, and / or the second signal line 210 extends along a second direction in one or more combinations of a straight line, a curve, and a broken line. The first direction may be the general extension direction of the first signal line 310. The second direction may be the general extension direction of the second signal line 210.

[0091] Based on the above design, in the display panel provided in this embodiment, the first signal line 310 and / or the second signal line 210 in the mesh structure are arranged to extend alternately in different film layers, thereby avoiding short circuits with other traces. In this way, even with a small number of film layers used for setting signal lines in the display panel, an interconnected mesh structure can be formed, reducing line impedance, ensuring the uniformity of the specific DC voltage provided to each pixel unit, improving the flexibility of the traces in the display panel, and thus ensuring the working performance of the display panel.

[0092] In one possible implementation, please refer to Figure 1In addition to the substrate 10, the display panel also includes an active layer 20, a first conductive layer 40, and a second conductive layer 60 stacked on one side of the substrate 10. An insulating layer is disposed between the active layer 20, the first conductive layer 40, and the second conductive layer 60. For example, a first insulating layer 30 is disposed between the active layer 20 and the first conductive layer 40, and a second insulating layer 50 is disposed between the first conductive layer 40 and the second conductive layer 60. Optionally, the active layer 20, the first conductive layer 40, and the second conductive layer 60 are stacked sequentially in a direction away from the substrate 10. The first conductive layer 40 is located between the active layer 20 and the second conductive layer 60.

[0093] The active layer 20 may include multiple semiconductor traces, such as traces formed of polysilicon (P-Si) or indium tin oxide (IGZO). A first insulating layer 30 may be located on the side of the active layer 20 away from the substrate 10. In this embodiment, the first insulating layer 30 may include a gate insulating layer. The first insulating layer 30 may include an inorganic layer and / or an organic layer. A first conductive layer 40 is located on the side of the first insulating layer 30 away from the substrate 10. The first conductive layer 40 may include multiple signal traces or at least some power traces, and may be a metal layer or indium tin oxide (ITO). A second insulating layer 50 may be located on the side of the first conductive layer 40 away from the substrate 10. The second insulating layer 50 may include an inorganic layer and / or an organic layer. A second conductive layer 60 is located on the side of the second insulating layer 50 away from the substrate 10. The second conductive layer 60 may include multiple signal traces or at least some power traces, and may be a metal layer or indium tin oxide (ITO).

[0094] Please refer to Figure 2 The first signal line 310 is located in the second conductive layer 60. The second signal line 210 includes a first trace segment 211 and a second trace segment 212 arranged along the extension direction of the second signal line 210, located in different film layers, and electrically connected through a via 600 (which may be referred to as the first via). The first trace segment 211 is located in the second conductive layer 60, and the second trace segment 212 is located in the first conductive layer 40 or the active layer 20. Please refer again. Figure 2 The first signal line 310 can be connected to the first trace segment 211, or please refer to... Figure 3 The first signal line 310 can be electrically connected to the second trace segment 212 through a via 600 (which may be referred to as the second via). Multiple specific structures, such as traces, located on the same film layer can be obtained by patterning the same film layer, thereby simplifying the process. The via 600 can penetrate the first insulating layer 30 and / or the second insulating layer 50 to achieve electrical connection between trace segments located on different film layers.

[0095] The orthographic projection of the first trace segment 211 on the substrate 10 overlaps with the orthographic projection of a portion of the active layer 20 on the substrate 10. For example, please refer to... Figure 4 The orthographic projection of the first trace segment 211 on the substrate 10 can overlap with the orthographic projection of the first semiconductor trace segment 110 extending along the first direction D1 on the substrate 10. That is, in this embodiment, the position where the second signal line 210 overlaps with the active layer 20 is switched to extend in the second conductive layer 60, i.e., the first trace segment 211 is disposed in the second conductive layer 60, thereby avoiding the situation where the first trace segment 211 and the active layer 20 form unwanted transistors when the first trace segment 211 is disposed in the first conductive layer. Here, the patterned first conductive layer can be used as a mask to perform a doping process on the active layer to form the source and drain regions of each transistor in the pixel unit. The area of ​​the active layer not covered by the first conductive layer forms the source and drain regions, and the area of ​​the active layer covered by the first conductive layer forms the channel region. The area of ​​the first conductive layer opposite to the channel region is equivalent to the gate of the transistor. If the first trace segment 211 is placed on the first conductive layer, the area of ​​the first semiconductor trace segment 110 that is blocked by the first trace segment 211 will form a channel region, which will form unwanted transistors and affect the performance of the display panel.

[0096] Please refer again to some possible implementation methods. Figure 4 The display panel also includes multiple third signal lines 320, located on one side of the substrate 10 and at least in the display area AA. The multiple third signal lines 320 are intersected and insulated from multiple second signal lines 210. For example, the third signal lines 320 extend along a first direction D1 and are arranged along a second direction D2, with the first direction D1 and the second direction D2 intersecting. Optionally, the first direction D1 and the second direction D2 are perpendicular. The orthographic projection of the third signal line 320 on the substrate 10 overlaps with the orthographic projection of the second trace segment 212 on the substrate 10. The third signal line 320 is located in the second conductive layer 60. Thus, the second signal lines 210 can be switched at locations where they might intersect with the third signal lines 320, extending into either the first conductive layer 40 or the active layer 20, thereby avoiding short circuits with the third signal lines 320.

[0097] Optionally, the third signal line 320 includes one or more of a data line and a power line.

[0098] Optionally, the display panel also includes scan lines and / or light emission control lines (not shown) located on the first conductive layer 40. The scan lines and light emission control lines extend along the second direction D2 and are arranged along the first direction D1.

[0099] In some possible implementations, the display panel further includes a plurality of pixel units located on one side of the substrate 10 and in the display area. Each pixel unit includes a driving transistor, a light-emitting device, and at least one initialization transistor. The initialization transistor is electrically connected to a first signal line 310 and a second signal line 210, and is used to initialize at least one of the gate, source, and drain of the driving transistor and / or the light-emitting device.

[0100] Optionally, the pixel unit includes a first initialization transistor and a second initialization transistor. The first initialization transistor is used to initialize the gate of the driving transistor. The second initialization transistor is used to initialize the light-emitting device. The initialization voltage used to initialize the gate of the driving transistor may be the same as or different from the initialization voltage used to initialize the light-emitting device.

[0101] Optional, please refer to Figure 5 A pixel unit may include a driving transistor M1, and may also include a first initialization transistor M4 and / or a second initialization transistor M7. The first initialization transistor M4 connects the gate of transistor M1 to the trace transmitting the first initialization voltage Vref1 according to the second scan signal of the second scan line S1, thereby initializing the voltage of the gate of the driving transistor M1. The second initialization transistor M7 connects the first electrode (e.g., the anode) of the light-emitting device to the trace transmitting the second initialization voltage Vref2 according to the third scan signal of the third scan line S1' (which may be equivalent to the second scan signal of the second scan line S1 of the previous row of pixel units), thereby initializing the voltage of the first electrode (e.g., the anode) of the light-emitting device EL. The second electrode (e.g., the cathode) of the light-emitting device EL may be connected to a second power line Vss. One of the power lines Vdd and Vss may be connected to a high potential, and the other may be connected to a low potential. The potential of the power line Vdd may be high. The potential of the second power line Vss may be low.

[0102] Optionally, in other implementations of this embodiment, the initialization transistor can also be used to initialize or provide a bias voltage to the source and / or drain of the driving transistor. For example, please refer to... Figure 6The pixel unit may further include a third initialization transistor M8. The third initialization transistor M8 connects the source of the driving transistor M1 to the trace transmitting the third initialization voltage Vref3 according to the third scan signal of the third scan line S3, thereby initializing the voltage at the source of the driving transistor M1. The third initialization voltage Vref3 can be a positive voltage, so that the gate and drain of the driving transistor M1 have a positive bias voltage during initialization reset, thereby accelerating the release of carriers on the driving transistor M1 and eliminating the influence of the previous frame's display. Optionally, the gates of the second initialization transistor M7 and the third initialization transistor M8 are electrically connected to the same scan line.

[0103] Optionally, the mesh structure includes a first mesh structure, in which the first signal line 310 and the second signal line 210 are initialization voltage lines. One or more of the first initialization transistor, the second initialization transistor, and the third initialization transistor M8 are electrically connected to the first signal line 310 and the second signal line 210 in the first mesh structure. That is, in this embodiment, one or more of the traces used to transmit the first initialization voltage Vref1, the second initialization voltage Vref2, and the third initialization voltage Vref3 can be set as a mesh, thereby ensuring that the initialization voltage obtained by each pixel unit is uniform, thus guaranteeing the display stability and display effect of the display panel. The first initialization voltage Vref1, the second initialization voltage Vref2, and the third initialization voltage Vref3 may be equal or unequal. The first initialization voltage Vref1 and the third initialization voltage Vref3 may be equal or unequal. The second initialization voltage Vref2 and the third initialization voltage Vref3 may be equal or unequal.

[0104] In some examples, please refer to Figure 7 The traces used to transmit the first initialization voltage Vref1 can form a mesh, but the traces used to transmit the second initialization voltage Vref2 do not need to form a mesh. The traces used to transmit the second initialization voltage Vref2 can extend along a first direction and be arranged along a second direction, or extend along a second direction and be arranged along a first direction. Multiple third signal lines 320 are intersected and insulated from multiple second signal lines 210 in the first mesh structure used to transmit the first initialization voltage Vref1. The third signal lines 320 may include one or more of the following: a data line (data), a power line (Vdd), an initialization voltage line used to transmit the second initialization voltage Vref2, and an initialization voltage line used to transmit the third initialization voltage Vref3, all extending along the first direction.

[0105] In other examples, please refer to Figure 8The traces used to transmit the second initialization voltage Vref2 can form a mesh, but the traces used to transmit the first initialization voltage Vref1 do not need to form a mesh. The traces used to transmit the first initialization voltage Vref1 can extend along a first direction and be arranged along a second direction, or extend along a second direction and be arranged along a first direction. Multiple third signal lines 320 are intersected and insulated from the multiple second signal lines 210 in the first mesh structure used to transmit the second initialization voltage Vref2. The third signal lines 320 may include one or more of the following: a data line (data), a power line (Vdd), an initialization voltage line used to transmit the first initialization voltage Vref1, and an initialization voltage line used to transmit the third initialization voltage Vref3, all extending along the first direction.

[0106] Optionally, the traces used to transmit the third initialization voltage Vref3 can be formed into a mesh, and the multiple third signal lines 320 are intersected and insulated from the multiple second signal lines 210 used to transmit the third initialization voltage Vref3 in the first mesh structure. The third signal lines 320 may include one or more of the following: a data line (data), a power line (Vdd), an initialization voltage line used to transmit the first initialization voltage Vref1, and an initialization voltage line used to transmit the second initialization voltage Vref2, all extending in the first direction.

[0107] For some possible implementations, please refer to Figure 9 The first mesh structure includes an insulated first sub-mesh structure and a second sub-mesh structure. In the first sub-mesh structure, the first signal line 310 and the second signal line 210 are connected to a first initialization voltage Vref1 to improve the uniformity of the first initialization voltage Vref1, reduce line voltage drop, and enhance display uniformity. In the second sub-mesh structure, the first signal line 310 and the second signal line 210 are connected to a second initialization voltage Vref2 to improve the uniformity of the second initialization voltage Vref2, reduce line voltage drop, and enhance display uniformity. The first initialization voltage Vref1 and the second initialization voltage Vref2 are different.

[0108] Optionally, the first mesh structure may include an insulated first sub-mesh structure and a third sub-mesh structure. The first signal line 310 and the second signal line 210 in the third sub-mesh structure are connected to a third initialization voltage Vref3 to improve the uniformity of the third initialization voltage Vref3, reduce line voltage drop, and enhance display uniformity. Optionally, the first mesh structure may include an insulated second sub-mesh structure and a third sub-mesh structure. Optionally, the first mesh structure may include an insulated first sub-mesh structure, a second sub-mesh structure, and a third sub-mesh structure.

[0109] The first initialization transistor is electrically connected to the first signal line 310 and the second signal line 210 in the first sub-mesh structure, and the second initialization transistor is electrically connected to the first signal line 310 and the second signal line 210 in the second sub-mesh structure. That is, in this embodiment, the traces used to transmit the first initialization voltage Vref1 and the second initialization voltage Vref2 can both be set as independent meshes.

[0110] For example, please refer to Figure 10 At least a portion of the second trace segment 212 of the second signal line 210 transmitting the first initialization voltage Vref1 overlaps with the first signal line 310 transmitting the second initialization voltage Vref2 and is located in a different film layer, thereby avoiding their cross-short circuit.

[0111] Optionally, please refer to again Figure 9 The first signal line 310 in the first sub-mesh structure and the first signal line 310 in the second sub-mesh structure extend along the first direction D1 and are alternately arranged along the second direction D2. Optionally, the second signal line 210 in the first sub-mesh structure and the second signal line 210 in the second sub-mesh structure extend along the second direction D2 and are alternately arranged along the first direction D1. The first direction D1 and the second direction D2 intersect.

[0112] Optionally, please refer to again Figure 9 The first signal line 310 in the first sub-mesh structure and the first signal line 310 in the second sub-mesh structure are located on both sides of a column of pixel units 700. That is, a column of pixel units 700 is located between the first signal line 310 of the first sub-mesh structure and the first signal line 310 of the second mesh structure. Two columns of pixel units 700 can be arranged between two adjacent first signal lines 310 in the first sub-mesh structure. Two columns of pixel units 700 can be arranged between two adjacent first signal lines 310 in the second sub-mesh structure.

[0113] Optionally, the second signal lines 210 in the adjacent first sub-mesh structure and the second signal lines 210 in the second sub-mesh structure are located on both sides of a row of pixel units 700, and a column of pixel units 700 is arranged along a first direction D1. A row of pixel units is arranged along a second direction D2 of 700. A row of pixel units 700 can be arranged between two adjacent second signal lines 210 in the first sub-mesh structure. A row of pixel units 700 can be arranged between two adjacent second signal lines 210 in the second sub-mesh structure.

[0114] In some examples, please refer to Figure 11The first signal line 310 in the first sub-mesh structure and the first signal line 310 in the second sub-mesh structure extend along the first direction D1 and are alternately arranged along the second direction D2. Each row of pixel units 700 extending along the second direction D2 has a corresponding first signal line 310 in the first sub-mesh structure and a first signal line 310 in the second sub-mesh structure.

[0115] In other examples, please refer to Figure 12 To reduce wiring space, a second signal line 210 for transmitting the first initialization voltage Vref1 can be provided for every two rows of pixel units, and a second signal line 210 for transmitting the second initialization voltage Vref2 can be provided for every two rows of pixel units. That is, any row of pixel units is located between the second signal lines 210 of the first sub-mesh structure and the second signal lines 210 of the second sub-mesh structure. Two rows of pixel units can be provided between two adjacent second signal lines 210 in the first sub-mesh structure. Two rows of pixel units can be provided between two adjacent second signal lines 210 in the second sub-mesh structure.

[0116] Specifically, taking the second trace segment 212 of the second signal line 210 located in the first conductive layer 40 as an example, please refer to... Figures 13 to 15 .in, Figure 13 This is a schematic diagram of the routing of active layer 20.

[0117] Figure 14 This is a schematic diagram of the wiring of the first conductive layer 40, wherein the first conductive layer 40 may include a first scan line S2, a second scan line S1, a light emission control line EM, and an initialization voltage line, wherein... Figure 14 Only the routing for transmitting the second initialization voltage Vref2 is shown. Figure 14 The dashed elliptical box in the middle shows the second trace segment 212 of the second signal line 210 of the first mesh structure.

[0118] Figure 15 This is a schematic diagram of the routing of the second conductive layer 60, which may include a power line Vdd, a data line data, and an initialization voltage line (including routing for transmitting the first initialization voltage Vref1 and the second initialization voltage Vref2). Figure 15 The dashed box in the middle shows the first trace segment 211 of the second signal line 210 of the first mesh structure.

[0119] Therefore, please refer to Figure 16 The first conductive layer 40 and the second conductive layer 60 work together to form a structure like... Figure 16 The first mesh structure is shown by the dashed line. Figure 16 Can be with Figure 5 The circuit structure corresponds to this.

[0120] In some possible implementations, the mesh structure includes a second mesh structure, where the first signal line 310 and the second signal line 210 in the second mesh structure are power lines (Vdd). That is, in this embodiment, the power line Vdd can also be configured as a mesh, thereby improving the uniformity of the power supply voltage obtained by each pixel unit. Multiple third signal lines 320 are intersected and insulated from the multiple second signal lines 210 in the second mesh structure. The third signal lines 320 may include one or more of the following: a data line extending along a first direction, an initialization voltage line for transmitting a first initialization voltage Vref1, and an initialization voltage line for transmitting a second initialization voltage Vref2.

[0121] In some possible implementations, in the second mesh structure, the first signal line 310 is located in the second conductive layer 60. The second signal line 210 includes multiple first trace segments 211 (Vdd) and multiple second trace segments 212 (Vdd) located in different film layers and electrically connected through vias 600. The first trace segments 211 are located in the second conductive layer 60 and connected to the first signal line 310. The second trace segments 212 are located in the first conductive layer 40 or the active layer 20.

[0122] The display panel also includes a first scan line, a data line, and multiple pixel units. Each pixel unit includes a driving transistor and a data writing transistor. The first scan line S2 is electrically connected to the gate of the data writing transistor M2. The data line is connected to the driving transistor M1 via the data writing transistor M2. The data writing transistor M2 is used to write the data voltage on the data line data to the driving transistor M2 in response to a first scan signal on the first scan line S2.

[0123] For example, the first scan line S2 transmits the first scan signal, and the data line data transmits the data signal. Optionally, the data line data is electrically connected to the gate of the driving transistor M1 via the data writing transistor M2, such as in a 2T1C circuit, or the data line data is electrically connected to the first electrode of the driving transistor M1 via the data writing transistor M2.

[0124] Optional, see Figure 5 The pixel unit also includes a threshold compensation transistor M3, which is connected between the gate and the second terminal of the driving transistor M1. The data line is electrically connected to the first terminal of the driving transistor M1 via the data writing transistor M2. The gate of the threshold compensation transistor M3 can be electrically connected to the same scan line as the gate of the data writing transistor M2.

[0125] Optional, see Figure 6 The gate of the threshold compensation transistor M3 is electrically connected to the fourth scan line S2'. The gate of the threshold compensation transistor M3 can be electrically connected to different scan lines than the gate of the data writing transistor M2. Figure 5 and Figure 6 The specific operating timing of the circuit can be the same as or similar to that of the existing technology, and will not be elaborated here.

[0126] Optional, see Figure 5 The pixel unit also includes a capacitor Cst. The capacitor Cst is electrically connected to the gate of the driving transistor M1. The capacitor Cst is connected between the power supply line Vdd and the gate of the driving transistor M1.

[0127] Please refer to the following: Figure 14 and Figure 15 The capacitor includes a first plate Cst1 and a second plate Cst2. The first plate Cst1 is multiplexed as the gate G1 of the driving transistor M1 and is located in the first conductive layer 40. Optionally, the second plate Cst2 is located in the second conductive layer 60 and is electrically connected to the first signal line 310 in the second mesh structure. The second plate Cst2 can be connected between the first signal line 310 (Vdd) and the first trace segment 211 (Vdd) in the second mesh structure. The second plate Cst2 can be a part of the second signal line 21 (Vdd) in the second mesh structure.

[0128] Optional, please refer to again Figure 14 The first electrode plate Cst1 has a notch on one of its two opposite sides along the second direction. Among three adjacent pixel units in the same row, the notch of the middle first electrode plate Cst1 is opposite to the notch of the first electrode plate Cst1 on one side and opposite to the notch of the first electrode plate Cst1 on the other side. At least one second trace segment 212 of the second signal line 210 in the second mesh structure is located between the notches of the adjacent first electrode plates Cst1 with opposite notches.

[0129] Optionally, two adjacent pixel units in the same row can be arranged in a mirror-symmetric configuration.

[0130] In the second mesh structure, the orthographic projections of multiple second trace segments 212 in the second signal line 210 connected to a row of pixel units onto the substrate 10 are located on opposite sides of the orthographic projection of the first scan line onto the substrate 10 along the first direction D1. By rationally setting the positions of the multiple second trace segments 212 in the second signal line 210 in the second mesh structure, space is utilized effectively to ensure a high pixel resolution (PPI).

[0131] Please see Figure 17The orthographic projection of the first trace segment 211 in the first mesh structure onto the substrate 10 can overlap with the orthographic projection of the first semiconductor trace segment 110 extending along the first direction D1 onto the substrate 10. The orthographic projection of the first trace segment 211 and the second trace segment 212 in the first mesh structure onto the substrate 10 overlaps with the orthographic projection of the third signal line 320 transmitting data signals and the first signal line 310 serving as a power line (Vdd) in the second mesh structure onto the substrate 10.

[0132] For example, taking the second trace segment 212 of the second signal line 210 in the second mesh structure located in the first conductive layer 40 as an example, please refer again. Figure 14 The second signal line 210 in the second mesh structure may include Figure 14 The multiple second routing segments 212 shown.

[0133] Therefore, please refer to Figure 18 The first conductive layer 40 and the second conductive layer 60 work together to form a structure like... Figure 18 The second mesh structure is shown by the dashed line. The second signal line 21 (Vdd) in the second mesh structure can be extended in a serpentine or other curved or broken line manner.

[0134] Optionally, please see again Figure 5 The pixel unit also includes a light-emitting control transistor (e.g., at least one of a first light-emitting control transistor M5 and a second light-emitting control transistor M6) and a light-emitting device EL.

[0135] The display panel also includes an EM (Emitting Light Control Line), please refer to [link / reference] again. Figure 14 The light-emitting control line EM is located in the first conductive layer. The light-emitting control line EM is electrically connected to the gate of a light-emitting control transistor (e.g., at least one of a first light-emitting control transistor M5 and a second light-emitting control transistor M6). The light-emitting control transistor (e.g., at least one of a first light-emitting control transistor M5 and a second light-emitting control transistor M6), the driving transistor M1, the power supply line Vdd, and the light-emitting device EL are connected in series. The first electrode Cst is located between the light-emitting control line EM and the first scan line S2. The first light-emitting control transistor M5 may be connected between the power supply line Vdd and the first electrode (e.g., the source) of the driving transistor M1. The second light-emitting control transistor M6 may be connected between the second electrode (e.g., the drain) of the driving transistor M1 and the first electrode of the light-emitting device.

[0136] Optional, see Figure 14 At least one second trace segment 212 (Vdd) in the second signal line 210 of the second mesh structure is located between the light emission control line EM and the first scan line S2.

[0137] Optional, please refer to again Figure 14The second scan line S1 is located in the first conductive layer 40, and at least one second trace 212 in the second signal line 210 of the second mesh structure is located between the second scan line S1 and the first scan line S2.

[0138] Optionally, an initialization voltage line (such as a trace that transmits the second initialization voltage Vref2) extending along the second direction and electrically connected to the second initialization transistor M7 is located between the first scan line S2 and the second scan line S1.

[0139] Optionally, at least a portion of the first signal line 310 and the second signal line 210 in the first mesh structure are electrically connected to the second initialization transistor M7. The second signal line 210 in the first mesh structure that is electrically connected to the second initialization transistor M7 is located between the second scan line S1 and the second signal line 210 in the second mesh structure.

[0140] Optional, please see again Figure 15 In the three adjacent columns of pixel units, two data lines (data), two power lines (Vdd) extending along the first direction, and an initialization voltage line (e.g., a trace for transmitting the first initialization voltage Vref1) extending along the first direction and electrically connected to the first initialization transistor M4 are arranged between two adjacent columns of pixel units. A first signal line 310 (e.g., a trace for transmitting the second initialization voltage Vref2) in the first mesh structure is arranged between the other two adjacent columns of pixel units.

[0141] The more first signal lines 310 and second signal lines 210 there are in each mesh structure, the better it is to reduce line impedance. However, in order to avoid interference between signal lines and ensure the required electrical distance between signal lines, a large amount of planar space will be occupied, which is not conducive to improving pixel resolution. Therefore, the spacing, number and density of the first signal lines 310 and the spacing, number and density of the second signal lines 210 in each mesh structure can be reasonably set according to the requirements.

[0142] For some possible implementations, please refer to Figure 19 The display panel also includes a light-emitting device layer, which includes a first electrode layer 81, a light-emitting functional layer 82, and a second electrode layer 83 stacked sequentially along a direction away from the substrate 10.

[0143] A planarization layer 70 may be disposed above the second conductive layer 60, and a first electrode layer 81 may be formed on the planarization layer 70. A pixel defining layer 84 with a pixel opening may be disposed above the first electrode layer 81, and a light-emitting functional layer 82 may be formed within the pixel opening. The light-emitting functional layer 82 may be an organic light-emitting material. In addition, at least one of a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer may be disposed within the pixel opening, and at least one of the hole injection layer, hole transport layer, and electron blocking layer may be located between the first electrode layer 81 and the light-emitting functional layer 82. At least one of the hole blocking layer, electron transport layer, and electron injection layer may be located between the second electrode layer 83 and the light-emitting functional layer 82. The first direction D1 and the second direction D2 are perpendicular to the thickness direction of the substrate 10. Optionally, the film layer containing the mesh structure is located between the light-emitting device layer and the substrate 10.

[0144] Optionally, in this embodiment, only two conductive layers may be disposed between the light-emitting device layer and the substrate 10, for example, a first conductive layer 40 and a second conductive layer 60. The film layer containing the mesh structure includes at least one of the active layer 20 and the first conductive layer 40, and the second conductive layer 60.

[0145] In this active layer 20, the portion covered by the first conductive layer 40 is shielded during ion implantation doping, forming the channel region 22 of the transistor. The portion of the first conductive layer 40 directly opposite the channel region 22 along the thickness direction of the substrate 10 forms the gate G1 of the transistor. The portions of the active layer 20 not covered by the first conductive layer 40 can form the source region 21 and drain region 23. The second conductive layer 60 can be electrically connected to the source region 21 and drain region 23 at other locations via vias, thereby forming the source and drain electrodes. Figure 5 The gate G1 of the driving transistor M1 shown can also serve as the first electrode Cst1, which, together with the second electrode Cst2 in the second conductive layer 60, forms a capacitor Cst. Other locations in the first conductive layer 40 and the second conductive layer 60 can be used to form signal or power traces.

[0146] It should be noted that in the display panel provided in this embodiment, since the display panel uses only a small number of conductive layers, the manufacturing steps of the entire display panel can be reduced. For example, in the entire display panel manufacturing process, only seven mask processes are needed to form the active layer 20, the first conductive layer 40, the second insulating layer 50, the second conductive layer 60, the planarization layer 70, the first electrode layer (which can be an anode layer) 81, and the pixel defining layer 84, respectively. This improves the manufacturing efficiency of the display panel and reduces manufacturing costs. At the same time, the display effect of the display panel can be guaranteed by the second metal traces that can extend continuously laterally. The second electrode layer 83 can be a cathode layer. Optionally, the display panel may also include a support pillar located on the side of the pixel defining layer away from the substrate. The pixel defining layer and the support pillar can be fabricated simultaneously using a half-tone mask process.

[0147] In some possible implementations, the display panel also includes multiple pixel units 700 arranged in an array. Please refer to... Figure 20 At least one column of pixel units 700 has an active layer 20 continuously arranged, and the arrangement direction of the column of pixel units 700 is parallel to the extension direction of the first signal line 310.

[0148] This embodiment also provides a method for manufacturing a display panel, please refer to... Figure 21 The method may include the following steps.

[0149] In step S110, a patterned active layer 20 is formed on the substrate 10, and the substrate 10 has a display area.

[0150] Step S120: A patterned first conductive layer 40 is formed on the active layer 20.

[0151] Optionally, in this embodiment, a first insulating layer 30 may be formed on the active layer 20, and then a first conductive layer 40 may be formed on the first insulating layer 30 and the first conductive layer 40 may be patterned and etched to form scan lines, light emission control lines, second trace segments 212 located on the first conductive layer, etc.

[0152] Step S130: Perform a doping process on the active layer 20.

[0153] In this process, the patterned first conductive layer can serve as a mask to perform doping on the active layer, forming the source and drain regions of each transistor in the pixel unit, the first semiconductor wiring segment 110, and the second wiring segment 212 located in the active layer. Ions can be implanted into the areas of the active layer not shielded by the first conductive layer to form the source and drain regions, the first semiconductor wiring segment 110, and the second wiring segment 212 located in the active layer. The areas of the active layer shielded by the first conductive layer form channel regions because the first conductive layer prevents ion implantation in these areas. The area of ​​the first conductive layer opposite to the channel region corresponds to the gate of the transistor.

[0154] In step S140, a patterned second conductive layer 60 is formed on the first conductive layer 40.

[0155] In this embodiment, a second insulating layer 50 can be formed on the first conductive layer 40, and then a second conductive layer 60 can be formed on the second insulating layer 50 and patterned and etched on the second conductive layer 60 to form a first signal line, a third signal line, etc., such as a data line data, a second electrode plate Cst2, etc.

[0156] A mesh structure is formed by at least one of a first conductive layer 40 and an active layer 20, and a second conductive layer 60. The mesh structure is located on one side of the substrate 10 and at least in the display area. The mesh structure includes multiple first signal lines 310 and multiple second signal lines 210 that are arranged in a cross pattern and electrically connected. At least one of the multiple first signal lines 310 and multiple second signal lines 210 includes multiple trace segments located in different film layers and electrically connected through vias.

[0157] The method for manufacturing this display panel can be used to manufacture the display panel in the above embodiments, and has the beneficial effects of the above embodiments, which will not be repeated here.

[0158] Optionally, after forming a patterned second conductive layer 60 on the first conductive layer 40, the method further includes forming a light-emitting device layer on the side of the second conductive layer 60 away from the substrate 10.

[0159] This embodiment also provides an electronic device, which includes the display panel provided in this embodiment. The electronic device may include mobile phones, laptops, tablets, smart wearable devices, etc.

[0160] In summary, the display panel and its manufacturing method provided in this application configure the first signal line and / or the second signal line in the mesh structure to extend alternately in different film layers, thereby avoiding short circuits with other traces. This allows for the formation of an interconnected mesh structure even with a small number of film layers used for signal lines in the display panel, reducing line impedance, ensuring the uniformity of the specific DC voltage provided to each pixel unit, improving the flexibility of the traces in the display panel, and thus guaranteeing the working performance of the display panel.

[0161] Furthermore, in the display panel provided in this embodiment, by using the above-mentioned mesh structure to transmit initialization voltage and / or power supply voltage, initialization voltage lines and / or power supply lines of the mesh structure can be formed even when the number of metal layers in the display panel is small, ensuring the uniformity of the initialization voltage and / or power supply voltage provided to each pixel unit, thereby ensuring the working performance or display effect of the display panel.

[0162] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0163] The above embodiments merely illustrate several implementation methods of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A display panel, characterized in that, include: The substrate has a display area; A mesh structure is located on one side of the substrate and at least in the display area. The mesh structure includes a plurality of first signal lines and a plurality of second signal lines that are arranged in a cross pattern and electrically connected. At least one of the plurality of first signal lines and the plurality of second signal lines includes a plurality of trace segments located in different film layers and electrically connected through vias. The display panel further includes an active layer, a first conductive layer, and a second conductive layer stacked on one side of the substrate; an insulating layer is disposed between the active layer, the first conductive layer, and the second conductive layer; The first signal line is located in the second conductive layer. The second signal line includes a first trace segment and a second trace segment arranged along the extension direction of the second signal line, located in different film layers, and electrically connected through vias. The first trace segment is located in the second conductive layer. The second trace segment is located in the first conductive layer or an active layer. The first signal line is connected to the first trace segment or electrically connected to the second trace segment through vias. The orthographic projection of the first trace segment on the substrate overlaps with the orthographic projection of a portion of the active layer on the substrate.

2. The display panel according to claim 1, characterized in that, The display panel further includes multiple third signal lines located on one side of the substrate and at least in the display area; the multiple third signal lines are intersected and insulated from the multiple second signal lines, the orthographic projection of the third signal lines on the substrate overlaps with the orthographic projection of the second trace segment on the substrate, and the third signal lines are located in the second conductive layer.

3. The display panel according to claim 2, characterized in that, The third signal line includes one or more of data lines and power lines; the third signal line extends along a first direction and is arranged along a second direction, wherein the first direction and the second direction intersect.

4. The display panel according to claim 3, characterized in that, The display panel further includes scan lines and / or light emission control lines located in the first conductive layer; the scan lines and the light emission control lines extend along the second direction and are arranged along the first direction.

5. The display panel according to claim 1, characterized in that, At least one of the plurality of first signal lines and the plurality of second signal lines includes multiple trace segments arranged along their own extension direction, located in different film layers, and electrically connected by vias.

6. The display panel according to claim 5, characterized in that, The plurality of first signal lines extend along a first direction and are arranged along a second direction, and the plurality of second signal lines extend along the second direction and are arranged along the first direction, wherein the first direction and the second direction intersect.

7. The display panel according to claim 6, characterized in that, The first signal line extends along the first direction in one or more combinations of a straight line, a curve, or a broken line; the second signal line extends along the second direction in one or more combinations of a straight line, a curve, or a broken line.

8. The display panel according to claim 1, characterized in that, The mesh structure includes a first mesh structure, wherein the first signal line and the second signal line in the first mesh structure are initialization voltage lines; The display panel further includes a plurality of pixel units located on one side of the substrate and in the display area; the pixel unit includes a driving transistor, a light-emitting device and at least one initialization transistor, the initialization transistor being electrically connected to the first signal line and the second signal line, and the initialization transistor being used to initialize at least one of the gate, source and drain of the driving transistor and / or the light-emitting device.

9. The display panel according to claim 8, characterized in that, The pixel unit includes a first initialization transistor and a second initialization transistor. The first initialization transistor is used to initialize the gate of the driving transistor; the second initialization transistor is used to initialize the light-emitting device; at least one of the first initialization transistor and the second initialization transistor is electrically connected to the first signal line and the second signal line in the first mesh structure; the initialization voltage for initializing the gate of the driving transistor is different from the initialization voltage for initializing the light-emitting device.

10. The display panel according to claim 9, characterized in that, The first mesh structure includes a first sub-mesh structure and a second sub-mesh structure that are insulated from each other. The first signal line and the second signal line in the first sub-mesh structure are connected to a first initialization voltage. The first signal line and the second signal line in the second sub-mesh structure are connected to a second initialization voltage. The first initialization voltage and the second initialization voltage are different. The first initialization transistor is electrically connected to the first signal line and the second signal line in the first sub-mesh structure, and the second initialization transistor is electrically connected to the first signal line and the second signal line in the second sub-mesh structure.

11. The display panel according to claim 10, characterized in that, The first signal line in the first sub-mesh structure and the first signal line in the second sub-mesh structure extend along a first direction and are alternately arranged along a second direction; the second signal line in the first sub-mesh structure and the second signal line in the second sub-mesh structure extend along the second direction and are alternately arranged along the first direction; the first direction and the second direction intersect.

12. The display panel according to claim 11, characterized in that, The first signal lines in adjacent first sub-mesh structures and the first signal lines in adjacent second sub-mesh structures are located on both sides of a column of pixel units; the second signal lines in adjacent first sub-mesh structures and the second signal lines in adjacent second sub-mesh structures are located on both sides of a row of pixel units, and the column of pixel units is arranged along the first direction; the row of pixel units is arranged along the second direction.

13. The display panel according to any one of claims 1-12, characterized in that, The mesh structure includes a second mesh structure, wherein the first signal line and the second signal line in the second mesh structure are power lines.

14. The display panel according to claim 13, characterized in that, The display panel further includes an active layer, a first conductive layer, and a second conductive layer stacked on one side of the substrate; an insulating layer is disposed between the active layer, the first conductive layer, and the second conductive layer; In the second mesh structure, the first signal line is located in the second conductive layer. The second signal line includes multiple first trace segments and multiple second trace segments located in different film layers and electrically connected through vias. The first trace segments are located in the second conductive layer and connected to the first signal line. The second trace segments are located in the first conductive layer or the active layer. The display panel further includes a first scan line, a data line, and multiple pixel units, wherein the pixel unit includes a driving transistor and a data writing transistor; The first scan line is electrically connected to the gate of the data writing transistor, and the data line is connected to the driving transistor via the data writing transistor. The data writing transistor is used to transmit the data voltage on the data line to the driving transistor in response to a first scan signal on the first scan line. In the second mesh structure, the orthographic projection of multiple second trace segments in the second signal line connected to a row of pixel units on the substrate is located on opposite sides of the orthographic projection of the first scan line on the substrate along a first direction.

15. The display panel according to claim 14, characterized in that, The pixel unit also includes a capacitor, which is electrically connected to the gate of the driving transistor; The capacitor includes a first plate and a second plate, the first plate being reused as the gate of the driving transistor, and the first plate being located in the first conductive layer. The second electrode is located in the second conductive layer and is electrically connected to the first signal line in the second mesh structure.

16. The display panel according to claim 15, characterized in that, The first electrode plate has a notch on one of its two opposite sides along the second direction. Among the three adjacent pixel units in the same row, the notch of the middle first electrode plate is opposite to the notch of the first electrode plate on one side and opposite to the notch of the first electrode plate on the other side. At least one second trace segment of the second signal line in the second mesh structure is located between the notches of the adjacent first electrode plates with opposite notches. The first direction and the second direction intersect.

17. The display panel according to claim 8, characterized in that, The two adjacent pixel units located in the same row are arranged in a mirror symmetric configuration.

18. The display panel according to claim 15, characterized in that, The pixel unit further includes a light-emitting control transistor and a light-emitting device. The display panel further includes a light-emitting control line, which is located in the first conductive layer. The light-emitting control line is electrically connected to the gate of the light-emitting control transistor. The light-emitting control transistor, the driving transistor, the power line, and the light-emitting device are connected in series. The first electrode plate is located between the light-emitting control line and the first scan line.

19. The display panel according to claim 18, characterized in that, At least one of the second signal lines in the second mesh structure is located between the light emission control line and the first scan line.

20. The display panel according to claim 18, characterized in that, The pixel unit further includes a first initialization transistor, and the display panel further includes a second scan line. The first initialization transistor is used to initialize the gate of the driving transistor. The gate of the first initialization transistor is electrically connected to the second scan line. The second scan line is located in the first conductive layer. At least one of the second signal lines in the second mesh structure is located between the second scan line and the first scan line.

21. The display panel according to claim 20, characterized in that, The pixel unit further includes a second initialization transistor, which is used to initialize the light-emitting device; an initialization voltage line extending along a second direction and electrically connected to the second initialization transistor is located between the first scan line and the second scan line, and the first direction and the second direction intersect. The mesh structure further includes a first mesh structure, wherein at least a portion of the first signal line and the second signal line in the first mesh structure are electrically connected to the second initialization transistor; the second signal line in the first mesh structure that is electrically connected to the second initialization transistor is located between the second scan line and the second signal line in the second mesh structure.

22. The display panel according to claim 21, characterized in that, In the three adjacent columns of pixel units, two data lines, two power lines extending along the first direction, and an initialization voltage line extending along the first direction and electrically connected to the first initialization transistor are provided between two adjacent columns of pixel units. A first signal line in the first mesh structure and electrically connected to the second initialization transistor is provided between the other two adjacent columns of pixel units.

23. The display panel according to claim 1, characterized in that, The display panel further includes a light-emitting device layer, which includes a first electrode layer, a light-emitting functional layer, and a second electrode layer stacked sequentially along a direction away from the substrate; the film layer containing the mesh structure is located between the light-emitting device layer and the substrate.

24. The display panel according to claim 23, characterized in that, Only two conductive layers are disposed between the light-emitting device layer and the substrate.

25. The display panel according to claim 1, characterized in that, The first conductive layer is located between the active layer and the second conductive layer.

26. The display panel according to claim 1, characterized in that, The display panel further includes a plurality of pixel units arranged in an array; at least one column of the pixel units has an active layer continuously disposed therein, and the arrangement direction of the column of the pixel units is parallel to the extension direction of the first signal line.

27. A method for manufacturing a display panel, characterized in that, The method for manufacturing a display panel according to any one of claims 1-26 includes: A patterned active layer is formed on a substrate, the substrate having a display area; A patterned first conductive layer is formed on the active layer. The active layer is subjected to a doping process; A patterned second conductive layer is formed on the first conductive layer; The mesh structure is formed by at least one of the first conductive layer and the active layer, and the second conductive layer. The mesh structure is located on one side of the substrate and at least in the display area. The mesh structure includes a plurality of first signal lines and a plurality of second signal lines that are arranged in a cross pattern and electrically connected. At least one of the plurality of first signal lines and the plurality of second signal lines includes a plurality of trace segments located in different film layers and electrically connected through vias.

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