A quantum chip and a fabrication method of flip chip

Abstract

The application discloses a quantum chip and a manufacturing method of the flip chip, and belongs to the field of quantum computing. The chip manufacturing method comprises the following steps: providing a substrate with a quantum circuit; and etching the substrate to form a stepped hole. The stepped hole comprises proximal holes and distal holes which are distributed at different distances relative to the quantum circuit, and the aperture of the proximal hole is smaller than that of the distal hole. A through-hole interconnect connected with the quantum circuit is manufactured in the proximal hole, and an adapter connected with the through-hole interconnect and not exposed to the surface of the substrate is formed in the distal hole. By using the manufacturing method, the connecting part can be arranged inside the substrate, so that the solder pad is allowed to be free from extrusion damage when pressure is applied to the surface of the substrate during the manufacturing process, thereby helping to improve the quality and stability of the lead wire matched with the solder pad.

Description

Technical Field

[0001] This application belongs to the field of quantum information, especially the field of quantum computing. In particular, this application relates to a method for manufacturing a quantum chip and a flip chip. Background Technology

[0002] Flip-chip bonding is an important method for improving the integration density of qubits in superconducting quantum chips. The flip-chip bonding process uses two layers of chips to achieve interconnection via interconnects. However, even with flip-chip bonding, there are still issues such as crowded layouts of various circuits and components within the chip, or difficulties in connecting them. Therefore, combining it with through-silicon via (TSV) technology becomes a beneficial option.

[0003] Through-silicon via (TSV) technology allows components to be moved from one surface of a chip to another by forming through-holes that extend through the chip's thickness, thus making fuller use of the chip's limited surface space.

[0004] However, this introduces process difficulties to flip-chip soldering. For example, flip-chip soldering may cause some components on the back of the chip to be squeezed and damaged, which in turn affects the quality of the chip, such as the stable transmission of signals. Summary of the Invention

[0005] This application provides an example of a method for fabricating a quantum chip and a flip chip. This method involves configuring pads for operations such as wire bonding inside the chip substrate, thus preventing the pads from being exposed to the substrate surface. Therefore, the pressure applied through the substrate surface during flip bonding operations does not affect the pads. Because the pads are inside the substrate, they are protected from compression operations, thereby ensuring the quality of the circuit connections when using these pads for subsequent wire bonding.

[0006] The solution presented in this application is implemented through the following steps.

[0007] In the first aspect, examples of this application present a method for fabricating a quantum chip.

[0008] The production method includes:

[0009] A substrate is provided with a metal layer disposed on its surface, and a portion of the metal layer is configured as a quantum circuit;

[0010] The substrate is etched to create stepped holes that align with the quantum circuit and penetrate the substrate. The stepped holes have a proximal hole close to the quantum circuit and a distal hole far from the quantum circuit, with the diameter of the proximal hole being smaller than that of the distal hole.

[0011] Fabricating through-hole interconnects for connection to quantum circuits within proximal holes; and

[0012] An adapter portion is formed within the distal hole to connect to the through-hole interconnect, and the adapter portion is not exposed to the surface of the substrate.

[0013] In flip chip fabrication, each chip layer typically needs to be fabricated independently before flip bonding; and during the flip bonding process, pressure needs to be applied to the chip surface. Due to this pressure method, various components on the chip surface (such as solder pads) may be damaged by compression. This is detrimental to the quality of the flip chip. This is especially true for quantum chips, which have higher sensitivity and lower tolerance to signals and the states of various components.

[0014] In the example of this application, a single-layer chip capable of flip-chip bonding is configured. By configuring stepped vias on the substrate, some components (such as signal lines or various elements) on both surfaces of the chip (such as the front and back sides) can be configured with through-hole interconnects using the stepped vias (the proximal holes), thereby enabling communication or optimized routing connections.

[0015] Furthermore, because the connector (which can be implemented as a pad, for example) connected to the through-hole interconnect is positioned inside the stepped hole (far-end hole) rather than exposed to the substrate surface, when this quantum chip is used to fabricate a flip chip, the force applied to the chip substrate surface will not contact the connector located inside the chip substrate, thus preventing damage to the connector due to compression. Based on this, leads formed through the undamaged connectors, such as those used for wire bonding, can provide continuous and stable transmission of microwave and electrical signals.

[0016] According to some examples of this application, the manufacturing method also includes: the adapter is entirely located at the bottom of the distal hole.

[0017] According to some examples of this application, the manufacturing method also includes: the through-hole interconnect is a hollow column.

[0018] According to some examples of this application, the manufacturing method also includes: the depth of the proximal hole is greater than the depth of the distal hole.

[0019] In a second aspect, examples of this application present a method for fabricating a quantum chip, comprising:

[0020] A substrate configured with quantum circuitry is provided, having opposing first and second surfaces;

[0021] A first etching is performed from the first surface to create a first hole recessed to a portion of the thickness of the substrate, and a through-hole interconnect is deposited within the first hole;

[0022] A second etching is performed from the second surface to create a second hole recessed to the remaining thickness of the substrate. The second hole communicates with the first hole at its end, has a bottom surface at its end, and a pad for connection to the through-hole interconnect is deposited on the bottom surface.

[0023] After the via interconnect is deposited, the quantum circuit is connected to the via interconnect in an optional step.

[0024] According to some examples of this application, the first hole and the second hole are coaxial; or, the axis of the first hole and the axis of the second hole are spaced apart from each other and parallel, and the depth of the first hole is greater than the depth of the second hole.

[0025] According to some examples of this application, either or both of the first hole and the second hole are through holes.

[0026] In a third aspect, the method for fabricating flip chips proposed in the examples of this application includes:

[0027] A first chip is obtained by implementing the above-described quantum chip fabrication method; and the first chip is connected to a second chip via flip-chip interconnects by flip-chip bonding.

[0028] According to some examples of this application, the method for fabricating a second chip includes the steps of the method for fabricating the quantum chip described above.

[0029] According to some examples of this application, a method for connecting a first chip to a second chip via a flip-chip interconnect by flip-chip bonding includes: configuring an interconnect structure between the first chip and the second chip and positioning them together between two extrusion plates, and then applying extrusion pressure through the extrusion plates while the interconnect structure is heated, so that the interconnect structure is transformed into a flip-chip interconnect.

[0030] According to some examples of this application, in the step of making the first chip flip-chip interconnected with the second chip via flip-chip interconnects, the first chip is processed to pre-form a first interconnect pillar, and at least a portion of the flip-chip interconnects is provided by the first interconnect pillar.

[0031] According to some examples of this application, in the step of making the first chip flip-chip interconnected with the second chip via flip-chip interconnects, the second chip has a second interconnect post pre-fabricated, and the flip-chip interconnect is provided by both the first interconnect post and the second interconnect post.

[0032] According to some examples of this application, the second chip has pads that are opposite to the first chip and bonded to the surface, and the flip-chip bonding method includes:

[0033] Two heating plates are configured to be spaced apart from each other, one of which has a barrier hole with a depth greater than the thickness of the pads bonded to the surface;

[0034] The first chip and the second chip are constrained between two heating plates, so that the first interconnect post and the second interconnect post are aligned, and the pads bonded to the surface are positioned in the obstacle avoidance hole.

[0035] A heating plate applies force to the first chip and the second chip, and the heating plate heats the first interconnect post and the second interconnect post by heat transfer, so that the first interconnect post and the second interconnect post are connected to each other to form a flip-chip interconnect.

[0036] Beneficial effects:

[0037] Typically, to fabricate flip-chips, two layers of chips are stacked together, and then force is applied by directly pressing the heated surfaces of the two chips together to form a flip-chip interconnect.

[0038] To accommodate more circuitry and components, through-silicon via (TSV) technology may be used in chips to place components in the area where two chips face each other onto the back of the chip, or to connect to other devices or components via leads on the back. Pads can be optionally configured to facilitate lead connections. However, as mentioned earlier, applying force directly to the chip surface may cause the pads to break, preventing effective lead connections.

[0039] Correspondingly, in the example of this application, the aforementioned pads on the surface of the chip substrate are adjusted and configured to be inside the substrate. Therefore, the operation of applying force by directly pressing on the chip surface will not cause mechanical damage to the pads, thus ensuring effective lead connections. Attached Figure Description

[0040] To illustrate this more clearly, the accompanying drawings used in the description will be briefly introduced below.

[0041] Figure 1 This is a schematic diagram of the first process for fabricating a quantum chip in this application example;

[0042] Figure 2 This is a schematic diagram of the second process for fabricating a quantum chip in this application example;

[0043] Figure 3 This is a schematic diagram of the substrate with stepped holes in the example of this application. Detailed Implementation

[0044] To integrate more qubits into quantum chips, flip-chip bonding and through-silicon via (TSV) technologies are often considered. These methods allow planar chips to be redesigned into three-dimensional layouts. For example, planar structures from a single chip can be distributed across the back and front sides of a single-layer chip; or planar structures from a single chip can be distributed across multiple layers; or a combination of both can be used, distributing planar structures originally located on a single-layer chip's surface (e.g., the front side) on the front and back sides of a single-layer chip, as well as on different layers of chips.

[0045] While the above approach enables more convenient layout and design of various quantum circuits and components, it may present some difficulties in process implementation, potentially leading to issues such as process consistency and yield.

[0046] For example, in practice, the inventors discovered that when combining flip-chip bonding technology and through-silicon via (TSV) technology to fabricate quantum chips, issues such as poor circuit connection quality would occasionally occur during the process, leading to the failure of some signal transmissions in the fabricated chips.

[0047] One specific manifestation of this is:

[0048] When different components are assigned to different layers of chips based on flip-chip bonding technology, and different components are configured on the front and back sides of a single chip using through-silicon via (TSV) technology, the contact bonding operation during the flip-chip bonding process can cause damage to some of the pads (used for signal connections between different lines or components).

[0049] The main reason is that the contact bonding operation with the pad can crush the pad, making it impossible to complete subsequent connection operations based on the pad with high quality.

[0050] In response to the above situation, the inventors have proposed a new method for manufacturing quantum chips. This method can effectively overcome the problem of pad damage mentioned above.

[0051] In essence, this solution is achieved by placing the pads inside the chip. During flip-chip bonding, the bonding pads primarily contact the main body of the chip, while placing the pads inside the chip avoids compression and does not hinder the smooth progress of the flip-chip bonding process.

[0052] For an example, please refer to Figure 1 The manufacturing method includes:

[0053] Step S101: Provide a substrate.

[0054] The substrate is typically made of a dielectric material. For example, the substrate may be a silicon substrate or a sapphire substrate. As a reference in quantum chips, a metal layer is disposed on the surface of this substrate. A portion of this metal layer is constructed as a quantum circuit. In the case of a superconducting quantum chip, the metal layer may be, for example, an aluminum layer. The corresponding quantum circuits may include, for example, capacitors, inductors, transmission lines such as coplanar waveguides, qubits, resonators, etc.

[0055] Step S102: Create holes in the substrate.

[0056] By combining micro- and nano-fabrication techniques, such as those used in semiconductor manufacturing, it is possible to create holes in the substrate.

[0057] In the example, the substrate is etched (either by dry etching or wet etching, etc.). To obtain an etched pattern with a specific morphology, photolithography can often be used in combination.

[0058] In this step, stepped holes aligning with the aforementioned quantum circuit and penetrating the substrate are fabricated by etching, such as... Figure 3 As shown. It is also worth noting that during etching, when the area of ​​the substrate to be etched is covered by the aforementioned metal layer, it can be understood that the etching operation also includes etching that metal layer. Alternatively, in some examples, if a metal layer disposed on the substrate at the location where a hole is to be formed covers that area, then it is also possible to choose not to etch the metal layer when etching the substrate to form the hole. These can be flexibly selected according to specific needs.

[0059] Based on the requirements of the example scheme in this application, the stepped aperture has two parts. One part is a near-end aperture and a far-end aperture. The near-end aperture is close to the quantum circuit, while the far-end aperture is far from the quantum circuit. Therefore, it can be understood that the proximity of the two parts of the stepped aperture is distinguished relative to the quantum circuit. For example, a substrate has two surfaces in the thickness direction, and a metal layer is located on one of these surfaces (e.g., referred to as a functional surface). Then, the end of the stepped aperture axially close to the metal layer can be described as a near-end aperture, and the end of the stepped aperture axially away from the metal layer (closer to the other surface) can be described as a far-end aperture.

[0060] Furthermore, the diameter of the proximal hole is smaller than that of the distal hole. This allows structures to be configured within the stepped hole, thus enabling platforms to be positioned within the stepped hole as attachment and configuration sites for the aforementioned structures. For example, pads can be configured within the stepped hole.

[0061] In terms of fabrication, stepped vias can be formed by creating two holes on two separate surfaces along the thickness direction of the substrate, thus combining the two holes. Alternatively, in other examples, the vias can be created in stages from one surface along the thickness direction of the substrate. For example, a larger diameter distal via can be created first, followed by a smaller diameter proximal via.

[0062] From a process implementation perspective, process conditions can be chosen such that the depth of the proximal hole is greater than the depth of the distal hole; however, this is not without limitations. Therefore, in other examples, the depth of the proximal hole can also be equal to or greater than the depth of the distal hole.

[0063] Step S103: Fabricate a through-hole interconnect that connects to the quantum circuit within the near-end hole.

[0064] After fabricating the stepped holes described above, the corresponding components can be fabricated within the holes. In this example, based on the requirement to connect components from one surface of the chip to another surface, this is achieved by configuring connection structures within the stepped holes. Through-hole interconnects are configured within the proximal end of the stepped holes.

[0065] Through-hole interconnects are electrical and signal conductors, allowing for electrical and signal conduction. Their material is not particularly limited and can be selected based on the specific application. For example, they can be made of copper, silver, etc., while for applications in superconducting quantum chips, superconducting materials such as Al, TiN, and NbTiN can be chosen. Alternatively, other composite structures of through-hole interconnects may be used.

[0066] Furthermore, in the specific implementation of through-hole interconnects, the through-hole interconnect can be a central hole structure or a solid structure. Its shape is, for example, a roughly columnar structure; therefore, a hollow column can be provided as a through-hole interconnect.

[0067] Step S104: Fabricate an adapter that connects to the through-hole interconnect.

[0068] To facilitate signal or electrical connections between through-hole interconnects and other pads or components via methods such as wire bonding, components connected to the through-hole interconnects can be fabricated after the through-hole interconnects are fabricated.

[0069] For example, in this application example, the adapter is formed within the distal via. This adapter connects to the end of the via interconnect and is not yet exposed to the substrate surface. That is, the adapter is located within the substrate. In other words, an adapter connected to the via interconnect is formed within the distal via, and the adapter is not exposed to the substrate surface. One possible form of the adapter is a pad, or a solder pad, solder ball, etc.; in other examples, it can also be configured as various non-pad or similar structures.

[0070] In different examples, the adapter can be constructed with different distributions. The adapter can be entirely located at the bottom of the distal hole, or partially located at the bottom of the distal hole, with the other parts correspondingly located on the sidewall of the distal hole.

[0071] The above description discloses a method for fabricating a quantum chip, which is another method for fabricating a quantum chip. The fabrication method can also be implemented in the following ways; please refer to [link / reference]. Figure 2 .

[0072] Step S201: Provide a substrate configured with quantum circuits, having opposing first and second surfaces.

[0073] The first and second surfaces can be the surfaces of the substrate itself that avoid the quantum circuit, or the surfaces of a metal layer or dielectric layer covering the substrate.

[0074] Step S202: Perform a first etching from the first surface to create a first hole recessed to a portion of the thickness of the substrate, and deposit a through-hole interconnect within the first hole.

[0075] As described in the previous example of fabricating stepped holes, holes can be fabricated through etching. Therefore, a first hole, recessed from the first surface to a portion of the substrate thickness, can be created through a first etching operation, and subsequently, through-hole interconnects can be fabricated within this first hole. It is understood that this first hole has the same function and usage as the aforementioned proximal hole.

[0076] In the aforementioned example of fabricating stepped holes, the near-end hole and the far-end hole were fabricated first, followed by the fabrication of the through-hole interconnect and the adapter. In this example, after fabricating the first hole, the through-hole interconnect is fabricated immediately (at this point, the adapter corresponding to the far-end hole has not yet been fabricated).

[0077] Step S203: Perform a second etching from the second surface to create a second hole recessed to the remaining thickness of the substrate. The second hole communicates with the first hole at its end and has a bottom surface at its end. A pad for connection with the through-hole interconnect is deposited on the bottom surface.

[0078] After completing the first hole and its internal through-hole interconnect, the second hole and corresponding pad structure can be fabricated. Alternatively, the pads can be fabricated first, followed by the through-hole interconnect connected to them. There is no particular restriction on the order in which the through-hole interconnect and pads are fabricated; the choice can be made adaptively based on actual process requirements or the ease of implementation.

[0079] Electrical or signal communication is achieved by connecting the pads to the through-hole interconnects. The shape and size of the pads can be selected according to the actual situation without any particular limitation. The manufacturing process can also use micro-nano fabrication technology, which will not be elaborated here.

[0080] In terms of spatial distribution, the first and second holes can be coaxial, such as coaxial cylindrical or prismatic holes. Alternatively, the axes of the first and second holes can be spaced apart and parallel to each other, with the spacing matching the hole diameters to form the connection between the pad and the via interconnect. For example, in the thickness direction of the substrate, the first and second holes have an overlapping projection area along the same plane.

[0081] Additionally, the depth of the first hole can be greater than the depth of the second hole to control the difficulty of drilling the holes. Of course, in other examples, as mentioned above, the first and second holes can also be configured with other relative depths, and this application does not have any particular limitations on this.

[0082] In addition to limiting the depth of the hole, the shape of the hole can also be selected. For example, in some examples, the first and second holes have the same shape, such as a through hole; or one of them is a through hole, while the other is a non-through hole, such as an angled through hole, exemplarily a through hole with a trapezoidal cross-section, that is, the first and second holes are holes with different shapes. For examples such as trapezoidal holes, for example, if the second hole is a trapezoidal hole, it is possible to choose to bring the end with the larger diameter closer to the first hole and the end with the smaller diameter closer to the second hole; or vice versa.

[0083] To facilitate subsequent pad configuration and wire bonding operations, for examples with trapezoidal holes, it's preferable to position the larger diameter end of the second trapezoidal hole closer to the first hole. This makes it easier for the bonding machine's probes to insert and perform the bonding operation.

[0084] Step S204: After depositing and forming the via interconnect, optionally connect the quantum circuit to the via interconnect.

[0085] Quantum circuits can be implemented in various ways; for example, in a superconducting quantum chip, they can be qubits, resonators, capacitors, etc. However, not all of these quantum circuits need to be configured in other three-dimensional distribution examples. Therefore, in this step, the quantum circuit connected to the via interconnect usually refers to components that need to be three-dimensionally distributed, or components that need to be distributed across different planes, or electrical components that need to be connected to other components in a non-coplanar space.

[0086] Furthermore, it can be understood that, given a pre-fabricated quantum circuit, the quantum circuit can be connected to the via interconnect after the via interconnect has been completed. That is, the optional step can be after the via interconnect is fabricated and before the second via is fabricated. Alternatively, in some other examples, the optional step can be after the second via is fabricated; or, in still other examples, the optional step can be after the pads are fabricated.

[0087] Furthermore, based on the description of the above scheme, the example also proposes a method for fabricating flip chips.

[0088] The fabrication method includes: obtaining a first chip by implementing the above-described quantum chip fabrication method; and connecting the first chip to a second chip via flip-chip interconnects by flip-chip bonding.

[0089] In other words, a newly constructed chip is fabricated using the quantum chip fabrication method described above, and then a conventional chip (as opposed to a chip with pads or similar features arranged inside holes in the substrate) is flip-chip bonded. The flip-chip bonding can be performed using existing or industry-known methods.

[0090] In other examples, the fabrication of the second chip may also employ the quantum chip fabrication method described above, either partially or entirely. Therefore, in these examples, the method for fabricating the second chip may also include steps of performing the quantum chip fabrication method described above (such as steps S101 to S104; or steps S201 to S204).

[0091] As an alternative example of the above-described flip-chip bonding process, a method for implementing flip-chip bonding to connect the first chip to the second chip via flip-chip interconnects includes:

[0092] An interconnect structure is configured between the first chip and the second chip and positioned together between two extrusion plates. Then, while the interconnect structure is heated, extrusion pressure is applied through the extrusion plates to transform the interconnect structure into a flip interconnect.

[0093] For example, the first chip, the second chip, and the interconnect structure are aligned and positioned respectively. Then, the interconnect structure is heated directly or indirectly, and subsequently or simultaneously squeezed in opposite directions, so that the interconnect structure is attached to the predetermined position of the two chips. At the same time, the interconnect structure, which is compressed, shortened and thickened, and connected to the two chips, forms a flip-chip interconnect.

[0094] In the above example, the interconnect structure is configured independently of the first chip and the second chip. In other examples, the interconnect structure can also be configured to be attached to one or both of the first chip and the second chip.

[0095] For example, in the step of flip-chip interconnecting the first chip with the second chip via a flip interconnect, the first chip is processed to pre-form a first interconnect pillar, and at least a portion of the flip interconnect is provided by the first interconnect pillar.

[0096] Alternatively, in the step of flip-chip interconnecting the first chip with the second chip via a flip-chip interconnect, the second chip has a pre-fabricated second interconnect post, and the flip-chip interconnect is provided by both the first and second interconnect posts.

[0097] In the example above, the first interconnect pillar can be an interconnect structure independently, or the first and second interconnect pillars can together form an interconnect structure. Furthermore, during the subsequent thermoforming process, the two chips (the first chip and the second chip) are connected, and the interconnect undergoes a shortening and thickening process to transform into a flip-chip interconnect present in the fabricated flip chip.

[0098] Furthermore, during thermocompression bonding, the bonding effect can be controlled by configuring the temperature and pressure during bonding. For example, the above explanation uses a first chip and a second chip. When one of the chips is also a flip-chip, it is possible to select relatively higher pressure and temperature during the fabrication of the first and second flip-chips, and lower temperature and pressure during the flip-chip bonding of the first and second chips.

[0099] This method can be achieved by using a thermoplate that contacts the chip and by controlling the temperature and pressure of the thermoplate. For example, when the first chip is also a flip-chip and the second chip is a single-layer chip, a first thermoplate is configured to mate with the first chip, and a second thermoplate is configured to mate with the second chip. When such a first chip and second chip are mated, the temperature of the first thermoplate is lower than the temperature of the second thermoplate, and the pressure of the first thermoplate is lower than the pressure of the second thermoplate.

[0100] Depending on the materials used, flip-chip interconnects can be implemented in various ways, such as solder joints and bumps. In superconducting quantum chips, flip-chip interconnects are, for example, indium pillars. Furthermore, if the indium pillars need to contact and mesh with a superconducting material such as aluminum, an insulating material such as titanium nitride can be placed between the indium pillars and the aluminum.

[0101] Furthermore, in some examples, the surface of the second chip may also have pads as needed. Therefore, when the second chip has pads that are opposite to the first chip and bonded to its surface, the method for flip-chip bonding the first and second chips includes:

[0102] Two heating plates (such as the first and second hot press plates mentioned above) are configured to be spaced apart from each other, and one of the heating plates (which cooperates with the second chip) has a barrier hole with a depth greater than the thickness of the pad located on the surface.

[0103] Based on this, the first chip and the second chip are constrained between the two heating plates, so that the first interconnect post and the second interconnect post corresponding to each of the two chips are aligned, and the pads attached to the surface are positioned in the obstacle avoidance hole.

[0104] Then, a force can be applied to the first chip and the second chip through the heating plate, and the first interconnect post and the second interconnect post can be heated by the heating plate through heat transfer, so that the first interconnect post and the second interconnect post are connected to each other to form a flip interconnect.

[0105] Performing flip-chip bonding operations using the above-mentioned methods can effectively avoid the problem of pads being squeezed and damaged, thereby helping to improve the quality of flip-chip bonding and ensuring the quality of the wire bonding produced.

[0106] Furthermore, the presence of holes in the substrate allows for modulation of the dielectric constant of the substrate, which serves as the dielectric material, thereby mitigating unwanted stray coupling and other issues in the quantum chip.

[0107] The embodiments described above with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0108] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, one or more embodiments have been described above with reference to the accompanying drawings. Throughout the description, similar reference numerals are used to denote similar components. In the foregoing description, numerous specific details have been set forth for illustrative purposes in order to provide a more thorough understanding of one or more embodiments. However, it will be apparent that one or more embodiments may be practiced in various circumstances without these specific details, and the embodiments may be combined with and referenced to each other without contradiction.

[0109] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0110] Additionally, it should be understood that when a layer (or film), region, pattern, or structure is referred to as being "on" a substrate, layer (or film), region, and / or pattern, it can be located directly on another layer or substrate, and / or intercalation layers may also be present. Furthermore, it should be understood that when a layer is referred to as being "under" another layer, it can be located directly under that layer, and / or one or more intercalation layers may also be present. Additionally, references to "on" and "under" the layers may be made based on the accompanying drawings.

[0111] The above description, based on the embodiments shown in the drawings, details the structure, features, and effects of this application. The above description is only a preferred embodiment of this application, but this application does not limit the scope of implementation to what is shown in the drawings. Any changes made in accordance with the concept of this application, or modifications to equivalent embodiments, that do not exceed the spirit covered by the specification and drawings, should be within the protection scope of this application.

Claims

1. A method for fabricating a quantum chip, characterized in that, The manufacturing method includes: A substrate configured with quantum circuitry is provided, having opposing first and second surfaces; A first etching is performed from the first surface to create a first hole recessed to a portion of the substrate thickness, and a through-hole interconnect is deposited within the first hole; A second etching is performed from the second surface to create a second hole recessed to the remaining thickness of the substrate. The second hole communicates with the first hole at its end, has a bottom surface at its end, and a pad for connection to the through-hole interconnect is deposited on the bottom surface. Quantum circuits are connected to the via interconnects after they are deposited and formed.

2. The method for fabricating a quantum chip according to claim 1, characterized in that, The first hole and the second hole are coaxial; Alternatively, the axis of the first hole and the axis of the second hole are spaced apart from each other and parallel, and the depth of the first hole is greater than the depth of the second hole.

3. The method for fabricating a quantum chip according to claim 1 or 2, characterized in that, Either or both of the first hole and the second hole are through holes.

4. A method for fabricating a flip chip, characterized in that, The manufacturing method includes: A first chip is obtained by implementing the method for fabricating a quantum chip according to any one of claims 1 to 3; and the first chip is connected to a second chip via flip-chip interconnect by flip-chip bonding.

5. The method for fabricating a flip chip according to claim 4, characterized in that, The method for fabricating the second chip includes the steps of performing the method for fabricating a quantum chip as described in any one of claims 1 to 3; Alternatively, a method for connecting a first chip to a second chip via flip-chip interconnects by flip-chip bonding includes: configuring an interconnect structure between the first chip and the second chip and positioning them together between two extrusion plates, and then applying extrusion pressure through the extrusion plates while the interconnect structure is heated, so that the interconnect structure is transformed into a flip-chip interconnect.

6. The method for fabricating a flip chip according to claim 4, characterized in that, In the step of flip-chip interconnecting the first chip with the second chip via a flip interconnect, the first chip is processed to pre-form a first interconnect pillar, and at least a portion of the flip interconnect is provided by the first interconnect pillar.

7. The method for fabricating a flip chip according to claim 6, characterized in that, In the step of flip-chip interconnecting the first chip with the second chip via a flip-chip interconnect, the second chip has a pre-fabricated second interconnect post, and the flip-chip interconnect is provided by both the first and second interconnect posts.

8. The method for fabricating a flip chip according to claim 7, characterized in that, The second chip has pads that are opposite to the first chip and bonded to the surface. The flip-chip bonding method includes: Two heating plates are configured to be spaced apart from each other, one of which has a barrier hole with a depth greater than the thickness of the pads bonded to the surface; The first chip and the second chip are constrained between the two heating plates, so that the first interconnect post and the second interconnect post are aligned, and the pads bonded to the surface are positioned in the obstacle avoidance hole. A heating plate applies force to the first chip and the second chip, and the heating plate heats the first interconnect post and the second interconnect post by heat transfer, so that the first interconnect post and the second interconnect post are connected to each other to form a flip-chip interconnect.

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