Method and apparatus for performing memory operations

Abstract

A method and device for executing a memory operation, the method comprising: generating an operation command, the operation command comprising a universal flash storage protocol information unit (UPIU) frame header and an extended header field (EHS); wherein the UPIU frame header comprises an EHS total length field, the EHS total length field indicating that the length of the EHS is not 0, and the EHS is used to indicate storage addresses corresponding to a plurality of EHS operation commands respectively; and sending the operation command to a universal flash storage (UFS) device controller. The number of interactions of commands can be reduced, the overall command overhead can be saved, and the efficiency of the memory operation can be improved.

Description

Technical Field

[0001] This application relates to storage technology, and more particularly to a method and apparatus for performing memory operations. Background Technology

[0002] In Universal Flash Storage (UFS) technology, data and information are transmitted between the UFS host controller and the UFS device controller through command interaction. However, the current UFS Protocol Information Unit (UPIU) has a limited command length, resulting in a limited information capacity per command. This can hinder the full realization of the performance advantages of UFS technology, especially for complex functionalities.

[0003] Related technologies offer accelerated read commands that support 4K data, triggering the UFS device controller to perform continuous accelerated reads and return the data all at once. However, for large-scale data storage operations, this technology still requires multiple command interactions, increasing the overhead of command interaction and failing to demonstrate the performance advantages of UFS technology. Summary of the Invention

[0004] This application provides a method and apparatus for performing memory operations to reduce command interaction, save command overhead overall, and improve the efficiency of memory operations.

[0005] In a first aspect, this application provides a method for executing memory operations, comprising: a UFS host controller generating operation commands, the operation commands including a Universal Flash Memory Protocol Information Unit (UPIU) frame header and an Extended Header (EHS) field; wherein the length of the UPIU frame header is a first length (32 bytes), and the total length of the EHS is N KB-32 bytes, which is greater than the difference between 4 KB and the first length, and the EHS is used to indicate the memory addresses corresponding to multiple EHS operation commands respectively; the UFS host controller sending the operation commands to a UFS device controller; the UFS device controller determining the memory addresses corresponding to the multiple EHS operation commands according to the operation commands, and performing corresponding memory operations on the memory addresses corresponding to the multiple EHS operation commands; and the UFS device controller returning the processing result to the UFS host controller.

[0006] In related technologies, the UFS host controller detects commands transmitted between itself and the UFS device controller. When the command length exceeds a set length (e.g., 4KB), the UFS host controller executes corresponding logic control to truncate the command, retaining only 4KB of the command for transmission to the UFS device controller. The remaining portion can be included in the next command or discarded. The UFS device controller can also execute the same method to generate 4KB commands or data. In this application, the set length is expanded, allowing the UFS host controller and UFS device controller to support the transmission of N KB commands or data, where N is greater than 4. Of these N KB, 32 bytes are used for the UPIU frame header, and the remaining length (N KB - 32 bytes) can be used for the extended header segment (EHS). An EHS of N KB - 32 bytes is not present in related technologies; therefore, commands transmitted between the UFS host controller and UFS device controller can carry more information. Correspondingly, the UPIU frame header includes an EHS total length field, indicating that the EHS length is not zero.

[0007] As described above, the operation commands of this application include a UPIU frame header and an EHS, with a total command length of N KB (N > 4). The UPIU frame header has a length of 32 bytes, and the EHS has a total length of N KB - 32 bytes. Therefore, compared to operation commands in the prior art, the operation commands of this application can carry more information. Based on this, the UFS host controller can send multiple EHS operation commands to the UFS device controller via a single operation command when multiple EHS operation commands need to be executed.

[0008] The aforementioned UPIU frame header includes an EHS total length field, which indicates that the EHS length is not zero. The EHS is used to indicate the storage addresses corresponding to multiple EHS operation commands. Multiple EHS operation commands can indicate multiple read operations, multiple write operations, or multiple erase operations. That is, multiple EHS operation commands can be sent to the UFS device controller at once through a single operation command, and they can all be read operations, all be write operations, or all be erase operations.

[0009] The maximum length of an EHS can be N KB-32B, meaning the total length of the EHS is less than or equal to N KB-32B. The specific value of this total length can be determined by the length of the data actually written into the EHS. The memory address corresponding to any one of multiple EHS operation commands can be represented by adding the starting address to the data length. For example, in a read operation, the starting address is the address of the first memory location of the data to be read, and the data length is the length of data to be read starting from that address.

[0010] The UFS host controller obtains the storage addresses corresponding to multiple EHS operation commands. In the operation commands sent to the UFS device controller, relevant information can be included to indicate the storage addresses corresponding to the multiple EHS operation commands.

[0011] After receiving the operation command, the UFS device controller can extract information from the corresponding bytes according to the format of the operation command, including the number of multiple EHS operation commands, the total length of the EHS, and the storage address and data length corresponding to each of the multiple EHS operation commands.

[0012] The UFS device controller performs corresponding operations on the multiple storage areas determined in the above steps according to the operation type indicated in the operation instruction, such as a read operation, write operation, or erase operation. When the memory operation is a read operation, the UFS device controller retrieves the stored data from the indicated multiple storage areas; when the memory operation is a write operation, the UFS device controller writes the data sent by the UFS host controller into the indicated multiple storage areas; when the memory operation is an erase operation, the UFS device controller erases the data from the indicated multiple storage areas.

[0013] When the memory operation is a read operation, the UFS device controller returns the read data to the UFS host controller; when the memory operation is a write operation, the UFS device controller returns a write success response to the UFS host controller; when the memory operation is an erase operation, the UFS device controller returns an erase success response to the UFS host controller.

[0014] It should be noted that, in addition to the fields mentioned above, the operation commands in this application may also include other fields. For example, the UPIU frame header may also include the index field (xx00 0001b) and the flag field (Flags) of the operation command. These fields can follow the relevant provisions in the protocol, and this application does not make any specific restrictions on them.

[0015] This application, based on extended operation commands, allows a single operation command to carry the storage addresses and data lengths corresponding to multiple EHS operation commands. This necessitates minimal command interaction to request and execute memory operations targeting multiple addresses, reducing command interactions. Furthermore, since the UFS host controller and UFS device controller can support larger data transfer volumes, the UFS device controller can carry more data in a single command when receiving or returning data, thus reducing the number of return commands and saving overall command overhead. Moreover, during memory operation execution, each command requires scheduling at the block level, and transmission at the driver and physical layers. Using the method of this application, I / O aggregation can be achieved for multiple EHS operation commands, merging the aforementioned scheduling and transmission processes, further reducing the memory operation processing flow and improving memory operation efficiency.

[0016] In one possible implementation, the UPIU frame header also includes the number of EHS operation commands; the EHS includes the starting address and data length of the logical block address (LBA) corresponding to each of the multiple EHS operation commands. That is, the EHS contains multiple LBAs, and each LBA corresponds to a data length.

[0017] In one possible implementation, the UPIU frame header also includes the logical block start address and total data length corresponding to multiple EHS operation commands; the EHS includes the physical page number (PPN) corresponding to each of the multiple EHS operation commands.

[0018] Secondly, this application provides a UFS host controller, including: a processor and an interface circuit; wherein, the processor is used to generate operation commands, the operation commands including a Universal Flash Memory Protocol Information Unit (UPIU) frame header and an Extension Header (EHS) field; wherein, the UPIU frame header includes an EHS total length field, the EHS total length field indicating that the length of the EHS is not 0, and the EHS is used to indicate the storage addresses corresponding to multiple EHS operation commands respectively; the interface circuit is used to send the operation commands to the Universal Flash Memory UFS device controller.

[0019] In one possible implementation, the UPIU frame header includes the number of the plurality of EHS operation commands.

[0020] In one possible implementation, the UPIU frame header includes the logical block start address and total data length corresponding to the plurality of EHS operation commands.

[0021] In one possible implementation, the plurality of EHS operation commands are used to indicate a plurality of read operations, a plurality of write operations, or a plurality of erase operations; the memory addresses corresponding to the plurality of EHS operation commands are either contiguous or non-contiguous.

[0022] In one possible implementation, the EHS includes the logical block start address and data length corresponding to the plurality of EHS operation commands.

[0023] In one possible implementation, the plurality of EHS operation commands are used to indicate a plurality of read operations; the memory addresses corresponding to the plurality of EHS operation commands are contiguous.

[0024] In one possible implementation, the EHS includes the physical page numbers corresponding to the plurality of EHS operation commands.

[0025] Thirdly, this application provides a UFS device, including: a processor, an interface circuit, and a storage medium; wherein, the interface circuit is configured to receive operation commands from a Universal Flash Storage UFS host controller, the operation commands including a Universal Flash Storage Protocol Information Unit (UPIU) frame header and an Extension Header (EHS) field; wherein, the UPIU frame header includes an EHS total length field, the EHS total length field indicating that the length of the EHS is not 0, and the EHS is used to indicate the storage addresses corresponding to multiple EHS operation commands respectively; the processor is configured to determine the storage addresses corresponding to the multiple EHS operation commands according to the operation commands; and perform corresponding memory operations on the storage medium at the storage addresses corresponding to the multiple EHS operation commands respectively.

[0026] In one possible implementation, the UPIU frame header includes the number of the plurality of EHS operation commands.

[0027] In one possible implementation, the UPIU frame header includes the logical block start address and total data length corresponding to the plurality of EHS operation commands.

[0028] In one possible implementation, the plurality of EHS operation commands are used to indicate a plurality of read operations, a plurality of write operations, or a plurality of erase operations; the memory addresses corresponding to the plurality of EHS operation commands are either contiguous or non-contiguous.

[0029] In one possible implementation, the EHS includes the logical block start address and data length corresponding to the plurality of EHS operation commands.

[0030] In one possible implementation, the plurality of EHS operation commands are used to indicate a plurality of read operations; the memory addresses corresponding to the plurality of EHS operation commands are contiguous.

[0031] In one possible implementation, the EHS includes the physical page numbers corresponding to the plurality of EHS operation commands.

[0032] Fourthly, this application provides a UFS host control device, comprising: a processing module and a sending module. The processing module is used to generate operation commands, the operation commands including a Universal Flash Memory Protocol Information Unit (UPIU) frame header and an Extension Header (EHS) field; wherein the UPIU frame header includes an EHS total length field, the EHS total length field indicating that the length of the EHS is not 0, and the EHS is used to indicate the storage addresses corresponding to multiple EHS operation commands; the sending module is used to send the operation commands to a Universal Flash Memory (UFS) device controller.

[0033] In one possible implementation, the UPIU frame header includes the number of the plurality of EHS operation commands.

[0034] In one possible implementation, the UPIU frame header includes the logical block start address and total data length corresponding to the plurality of EHS operation commands.

[0035] In one possible implementation, the plurality of EHS operation commands are used to indicate a plurality of read operations, a plurality of write operations, or a plurality of erase operations; the memory addresses corresponding to the plurality of EHS operation commands are either contiguous or non-contiguous.

[0036] In one possible implementation, the EHS includes the logical block start address and data length corresponding to the plurality of EHS operation commands.

[0037] In one possible implementation, the plurality of EHS operation commands are used to indicate a plurality of read operations; the memory addresses corresponding to the plurality of EHS operation commands are contiguous.

[0038] In one possible implementation, the EHS includes the physical page numbers corresponding to the plurality of EHS operation commands.

[0039] Fifthly, this application provides a UFS device, comprising: a receiving module and a processing module. The receiving module is configured to receive operation commands from a Universal Flash Storage UFS host controller, the operation commands including a Universal Flash Storage Protocol Information Unit (UPIU) frame header and an Extension Header (EHS) field; wherein the UPIU frame header includes an EHS total length field, the EHS total length field indicating that the length of the EHS is not zero, and the EHS is used to indicate storage addresses corresponding to multiple EHS operation commands respectively; the processing module is configured to determine the storage addresses corresponding to the multiple EHS operation commands according to the operation commands; and perform corresponding memory operations on the storage medium at the storage addresses corresponding to the multiple EHS operation commands respectively.

[0040] In one possible implementation, the UPIU frame header includes the number of the plurality of EHS operation commands.

[0041] In one possible implementation, the UPIU frame header includes the logical block start address and total data length corresponding to the plurality of EHS operation commands.

[0042] In one possible implementation, the plurality of EHS operation commands are used to indicate a plurality of read operations, a plurality of write operations, or a plurality of erase operations; the memory addresses corresponding to the plurality of EHS operation commands are either contiguous or non-contiguous.

[0043] In one possible implementation, the EHS includes the logical block start address and data length corresponding to the plurality of EHS operation commands.

[0044] In one possible implementation, the plurality of EHS operation commands are used to indicate a plurality of read operations; the memory addresses corresponding to the plurality of EHS operation commands are contiguous.

[0045] In one possible implementation, the EHS includes the physical page numbers corresponding to the plurality of EHS operation commands.

[0046] In a sixth aspect, this application provides a computer-readable storage medium including a computer program that, when executed on a computer, causes the computer to perform the method described in any one of the first aspects above. Attached Figure Description

[0047] Figure 1 An exemplary flowchart for accelerating reading in related technologies;

[0048] Figure 2 This is an exemplary structural diagram of the hardware system of this application;

[0049] Figure 3This is an exemplary flowchart of a method for performing memory operations according to this application;

[0050] Figure 4 This is an exemplary structural diagram of the operation commands in this application;

[0051] Figure 5 This is an exemplary structural diagram of the operation commands in this application;

[0052] Figure 6 This is an exemplary flowchart of the method for performing a read operation in this application;

[0053] Figure 7 This is an exemplary structural diagram of the UFS host control device of this application;

[0054] Figure 8 This is an exemplary structural diagram of the UFS device control device of this application. Detailed Implementation

[0055] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0056] The terms "first," "second," etc., used in the specification, embodiments, claims, and drawings of this application are for distinguishing purposes only and should not be construed as indicating or implying relative importance or order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, such as including a series of steps or units. A method, system, product, or apparatus is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or apparatuses.

[0057] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0058] Figure 1 An exemplary flowchart for accelerating reading of related technologies, such as Figure 1 As shown, in Phase 1, when the UFS host controller detects that a large number of IO reads have hit the table entries, it sends a dedicated sequence of Write Buffer DPIU, Ready to transfer, and Data out commands, followed by read operation commands for multiple physical page numbers (PPNs). In Phase 2, the UFS host controller sends an accelerated read command, triggering the UFS device controller to perform continuous accelerated reads and return the data all at once.

[0059] However, completing the aforementioned accelerated read operation requires two stages and at least eight UPIU command interactions. If the required functionality is complex, this can prevent the overall performance advantages of UFS technology from being fully realized. Furthermore, the concurrent command interactions across multiple slots necessitate adding command ownership markers to both the UFS host controller and the UFS device controller to prevent command confusion, leading to complex processing and significant overhead from command interactions.

[0060] To address the aforementioned technical problems, this application provides a method for performing memory operations, which is illustrated through the following embodiments.

[0061] Figure 2 Here is an exemplary structural diagram of the hardware system of this application, such as Figure 2 As shown, a UFS Host includes an application, a UFS driver, a UFS host controller, and interface circuitry, while a UFS Device includes user storage, a UFS device controller, and interface circuitry.

[0062] Commands and data are transmitted between the UFS Host and the UFS Device through their interface circuitry. The UFS host controller is responsible for generating operation commands, while the UFS device controller is responsible for parsing the commands and controlling the execution of memory operations.

[0063] Based on the above structure, in related technologies, the UFS host controller detects commands transmitted between itself and the UFS device controller. When the command length exceeds a set length (e.g., 4KB), the UFS host controller executes corresponding logic control to truncate the command, retaining only 4KB of the command for transmission to the UFS device controller. The remaining portion can be included in the next command or discarded. The UFS device controller can also execute the same method to generate 4KB commands or data. In this application, the set length is expanded, enabling the UFS host controller and UFS device controller to support the transmission of NKB commands or data. N is greater than 4, with 32 bytes of N KB used for the UPIU frame header, and the remaining length (N KB - 32 bytes) used for the extended header segment (EHS). An EHS of N KB - 32 bytes is not present in related technologies; therefore, commands transmitted between the UFS host controller and UFS device controller can carry more information. Correspondingly, the UPIU frame header includes an EHS total length field, indicating that the EHS length is not zero.

[0064] It should be noted that the UFS Host and UFS Device of this application can be integrated into the same electronic device to jointly complete memory operations, and the electronic device has storage capabilities; the UFS Host and UFS Device can also be set on different electronic devices, for example, the UFS Host can be set on user devices such as mobile phones and tablets, and the UFS Device can be set on storage devices such as hard disks, registers, and flash memory.

[0065] Figure 3 An exemplary flowchart of the method for performing memory operations according to this application is shown below. Figure 3 As shown, the method in this embodiment can be jointly executed by the UFS host controller and the UFS device controller described above. The method for performing memory operations may include:

[0066] Step 301: The UFS host controller generates operation commands.

[0067] As described above, the operation commands of this application include a UPIU frame header and an EHS, with a total command length of N KB (N > 4). The UPIU frame header has a length of 32 bytes, and the EHS has a total length of N KB - 32 bytes. Therefore, compared to operation commands in the prior art, the operation commands of this application can carry more information. Based on this, the UFS host controller can send multiple EHS operation commands to the UFS device controller via a single operation command when multiple EHS operation commands need to be executed.

[0068] The aforementioned UPIU frame header includes an EHS total length field, which indicates that the EHS length is not zero. The EHS is used to indicate the storage addresses corresponding to multiple EHS operation commands. Multiple EHS operation commands can indicate multiple read operations, multiple write operations, or multiple erase operations. That is, multiple EHS operation commands can be sent to the UFS device controller at once through a single operation command, and they can all be read operations, all be write operations, or all be erase operations.

[0069] The maximum length of an EHS can be N KB-32B, meaning the total length of the EHS is less than or equal to N KB-32B. The specific value of this total length can be determined by the length of the data actually written into the EHS. The memory address corresponding to any one of multiple EHS operation commands can be represented by adding the starting address to the data length. For example, in a read operation, the starting address is the address of the first memory location of the data to be read, and the data length is the length of data to be read starting from that address.

[0070] Step 302: The UFS host controller sends an operation command to the UFS device controller.

[0071] The UFS host controller obtains the storage addresses corresponding to multiple EHS operation commands. In the operation commands sent to the UFS device controller, relevant information can be included to indicate the storage addresses corresponding to the multiple EHS operation commands.

[0072] In one possible implementation, the UPIU frame header also includes the number of EHS operation commands; the EHS includes the starting address and data length of the logical block address (LBA) corresponding to each of the multiple EHS operation commands. That is, the EHS contains multiple LBAs, and each LBA corresponds to a data length.

[0073] In this embodiment, the memory addresses corresponding to multiple EHS operation commands may be contiguous or non-contiguous. For example, multiple EHS operation commands indicate multiple read operations. Taking read operation 1, read operation 2, and read operation 3 as examples, read operation 1 corresponds to LBA 1 and data length 1, read operation 2 corresponds to LBA 2 and data length 2, and read operation 3 corresponds to LBA 3 and data length 3. LBA 1, LBA 2, and LBA 3 can be contiguous, meaning the data to be read by read operation 1, read operation 2, and read operation 3 are stored in adjacent memory regions; or LBA 1, LBA 2, and LBA 3 can be non-contiguous, meaning the data to be read by read operation 1, read operation 2, and read operation 3 are stored in separate memory regions. It should be understood that the LBAs corresponding to multiple EHS operation commands can also be partially contiguous and partially non-contiguous.

[0074] For example, Figure 4 Here is an exemplary structural diagram of the operation commands in this application, such as Figure 4 As shown, the UPIU frame header in the operation command occupies bytes 0 to 31, a total of 32 bytes. Byte 8 is filled with the EHS length (Total EHS Length), for example, 32 bytes, and byte 9 is filled with the number of multiple EHS operation commands (Total EHS Num), for example, 4.

[0075] The EHS in the operation command occupies 32 bytes. Bytes 0-3 are filled with LBA0 for the first memory operation, and bytes 4-7 with LEN0 for the first memory operation; bytes 8-11 with LBA1 for the second memory operation, and bytes 12-15 with LEN1 for the second memory operation; bytes 16-19 with LBA2 for the third memory operation, and bytes 20-23 with LEN2 for the third memory operation; bytes 24-27 with LBA3 for the fourth memory operation, and bytes 28-31 with LEN3 for the fourth memory operation. In this embodiment, the row number in the EHS represents the index number of the first byte in every group of four bytes, and the column number represents the offset of the index number of each byte in that group relative to the index number of the first byte. It should be noted that the byte index numbers in the EHS can also be represented in other ways, and this application does not specifically limit this.

[0076] In one possible implementation, the UPIU frame header also includes the logical block start address and total data length corresponding to multiple EHS operation commands; the EHS includes the physical page number (PPN) corresponding to each of the multiple EHS operation commands.

[0077] In this embodiment, the storage addresses corresponding to multiple EHS operation commands are consecutive, and the starting addresses of the PPNs and LBAs corresponding to multiple EHS operation commands are corresponding. Based on this, the UPIU frame header can only contain the LBAs corresponding to the multiple EHS operation commands. Thus, the total length of the data corresponding to the multiple EHS operation commands, plus the LBA, can indicate the storage area in memory for all the data to be processed by the multiple EHS operation commands. Furthermore, the UFS host controller can only obtain the correspondence between LBAs and PPNs when performing a read operation. This is because the data has already been stored in memory, and its storage location is determined, thus allowing the correspondence between LBAs and PPNs to be established.

[0078] For example, Figure 5 Here is an exemplary structural diagram of the operation commands in this application, such as Figure 5 As shown, the UPIU frame header in the operation command occupies bytes 0 to 31, totaling 32 bytes. Byte 8 is filled with the total length of the EHS (Total EHSLength), for example, 32 bytes. Bytes 18 to 21 are filled with the starting addresses of the logical blocks corresponding to multiple read operations (LBA[3] to LBA[0]). Bytes 26 to 29 are filled with the total length of the data corresponding to multiple read operations (Length[3] to Length[0]).

[0079] The EHS in the operation command occupies 32 bytes. Among them, bytes 0 to 3 are filled with PPN0 (PPN0[3] to PPN0[0]) of the first read operation, bytes 4 to 7 are filled with PPN1 (PPN1[3] to PPN1[0]) of the second read operation, bytes 8 to 11 are filled with PPN2 (PPN2[3] to PPN2[0]) of the third read operation, and bytes 12 to 15 are filled with PPN3 (PPN3[3] to PPN3[0]) of the fourth read operation.

[0080] Figure 6 An exemplary flowchart of the method for performing the read operation of this application is shown below. Figure 6 As shown, the UFS host controller sends a read operation command to the UFS device controller. This read operation command includes a UPIU frame header and an EHS. The EHS contains the addresses of the storage areas in memory where the data to be read is located. After retrieving the stored data from the aforementioned addresses, the UFS device controller returns the data to the UFS host controller via the Data In UPIU command, completing the entire read operation. It can be seen that... Figure 1Compared to the process shown, the method in this application only requires a single operation command to request the reading of data from multiple addresses, reducing command interactions. Furthermore, since the UFS host controller and UFS device controller can support larger data transfer volumes, the UFS device controller can carry more data in a single command when returning data, thus reducing the number of return commands and saving overall command overhead.

[0081] Step 303: The UFS device controller determines the storage address corresponding to each of the multiple EHS operation commands based on the operation commands.

[0082] After receiving the operation command, the UFS device controller can extract information from the corresponding bytes according to the format of the operation command, including the number of multiple EHS operation commands, the total length of the EHS, and the storage address and data length corresponding to each of the multiple EHS operation commands.

[0083] In one possible implementation, according to Figure 4 As shown in the structure, the UFS device controller extracts the length of the EHS from byte 8 of the UPIU frame header and the number of multiple EHS operation commands from byte 9. It then extracts the LBA0 for the first memory operation from bytes 0-3 of the EHS, the LEN0 for the first memory operation from bytes 4-7, the LBA1 for the second memory operation from bytes 8-11, the LEN1 for the second memory operation from bytes 12-15, the LBA2 for the third memory operation from bytes 16-19, the LEN2 for the third memory operation from bytes 20-23, the LBA3 for the fourth memory operation from bytes 24-27, and the LEN3 for the fourth memory operation from bytes 28-31.

[0084] In one possible implementation, according to Figure 5 The structure shown shows that the UFS device controller extracts the length of the EHS from byte 8 of the UPIU frame header, extracts the starting address LBA (LBA[3]~LBA[0]) corresponding to multiple read operations from bytes 18 to 21, and extracts the total data length (Length[3]~Length[0]) corresponding to multiple read operations from bytes 26 to 29. It extracts the PPN0 of the first read operation (PPN0[3]~PPN0[0]) from bytes 0 to 3 of the EHS, the PPN1 of the second read operation (PPN1[3]~PPN1[0]) from bytes 4 to 7, the PPN2 of the third read operation (PPN2[3]~PPN2[0]) from bytes 8 to 11, and the PPN3 of the fourth read operation (PPN3[3]~PPN3[0]) from bytes 12 to 15.

[0085] Based on the above information, the UFS device controller can determine the storage area in the memory where the data to be processed by each memory operation is located.

[0086] Step 304: The UFS device controller performs the corresponding memory operations on the storage addresses corresponding to the multiple EHS operation commands.

[0087] The UFS device controller performs corresponding operations on the multiple storage areas determined in the above steps according to the operation type indicated in the operation instruction, such as a read operation, write operation, or erase operation. When the memory operation is a read operation, the UFS device controller retrieves the stored data from the indicated multiple storage areas; when the memory operation is a write operation, the UFS device controller writes the data sent by the UFS host controller into the indicated multiple storage areas; when the memory operation is an erase operation, the UFS device controller erases the data from the indicated multiple storage areas.

[0088] Step 305: The UFS device controller returns the processing result to the UFS host controller.

[0089] When the memory operation is a read operation, the UFS device controller returns the read data to the UFS host controller; when the memory operation is a write operation, the UFS device controller returns a write success response to the UFS host controller; when the memory operation is an erase operation, the UFS device controller returns an erase success response to the UFS host controller.

[0090] It should be noted that, in addition to the fields mentioned above, the operation commands in this application may also include other fields. For example, the UPIU frame header may also include the index field (xx00 0001b) and the flag field (Flags) of the operation command. These fields can follow the relevant provisions in the protocol, and this application does not make any specific restrictions on them.

[0091] This application, based on extended operation commands, allows a single operation command to carry the storage addresses and data lengths corresponding to multiple EHS operation commands. This necessitates minimal command interaction to request and execute memory operations targeting multiple addresses, reducing command interactions. Furthermore, since the UFS host controller and UFS device controller can support larger data transfer volumes, the UFS device controller can carry more data in a single command when receiving or returning data, thus reducing the number of return commands and saving overall command overhead. Moreover, during memory operation execution, each command requires scheduling at the block level, and transmission at the driver and physical layers. Using the method of this application, I / O aggregation can be achieved for multiple EHS operation commands, merging the aforementioned scheduling and transmission processes, further reducing the memory operation processing flow and improving memory operation efficiency.

[0092] Figure 7 This is an exemplary structural diagram of the UFS host control device of this application, as shown below. Figure 7 As shown, the device in this embodiment can be the UFS host controller in the above embodiments. The device includes: a processing module 701 and a sending module 702. Wherein,

[0093] Processing module 701 is used to generate operation commands, the operation commands including a Universal Flash Memory Protocol Information Unit (UPIU) frame header and an Extension Header (EHS) field; wherein, the UPIU frame header includes an EHS total length field, the EHS total length field indicating that the length of the EHS is not 0, and the EHS is used to indicate the storage address corresponding to each of the multiple EHS operation commands; sending module 702 is used to send the operation commands to the Universal Flash Memory (UFS) device controller.

[0094] In one possible implementation, the UPIU frame header includes the number of the plurality of EHS operation commands.

[0095] In one possible implementation, the UPIU frame header includes the logical block start address and total data length corresponding to the plurality of EHS operation commands.

[0096] In one possible implementation, the plurality of EHS operation commands are used to indicate a plurality of read operations, a plurality of write operations, or a plurality of erase operations; the memory addresses corresponding to the plurality of EHS operation commands are either contiguous or non-contiguous.

[0097] In one possible implementation, the EHS includes the logical block start address and data length corresponding to the plurality of EHS operation commands.

[0098] In one possible implementation, the plurality of EHS operation commands are used to indicate a plurality of read operations; the memory addresses corresponding to the plurality of EHS operation commands are contiguous.

[0099] In one possible implementation, the EHS includes the physical page numbers corresponding to the plurality of EHS operation commands.

[0100] The apparatus of this embodiment can be used to perform Figure 3 The technical solutions of the method embodiments shown are similar in principle and in effect, and will not be described again here.

[0101] Figure 8 This is an exemplary structural diagram of the UFS device control device of this application, as shown below. Figure 8 As shown, the device in this embodiment can be the UFS device controller in the above embodiments. The device includes: a receiving module 801 and a processing module 802. Wherein,

[0102] The receiving module 801 is configured to receive operation commands from the Universal Flash Storage (UFS) host controller, the operation commands including a Universal Flash Storage Protocol Information Unit (UPIU) frame header and an Extension Header (EHS) field; wherein, the UPIU frame header includes an EHS total length field, the EHS total length field indicating that the length of the EHS is not 0, and the EHS is used to indicate the storage addresses corresponding to the multiple EHS operation commands respectively; the processing module 802 is configured to determine the storage addresses corresponding to the multiple EHS operation commands according to the operation commands; and perform corresponding memory operations on the storage medium at the storage addresses corresponding to the multiple EHS operation commands respectively.

[0103] In one possible implementation, the UPIU frame header includes the number of the plurality of EHS operation commands.

[0104] In one possible implementation, the UPIU frame header includes the logical block start address and total data length corresponding to the plurality of EHS operation commands.

[0105] In one possible implementation, the plurality of EHS operation commands are used to indicate a plurality of read operations, a plurality of write operations, or a plurality of erase operations; the memory addresses corresponding to the plurality of EHS operation commands are either contiguous or non-contiguous.

[0106] In one possible implementation, the EHS includes the logical block start address and data length corresponding to the plurality of EHS operation commands.

[0107] In one possible implementation, the plurality of EHS operation commands are used to indicate a plurality of read operations; the memory addresses corresponding to the plurality of EHS operation commands are contiguous.

[0108] In one possible implementation, the EHS includes the physical page numbers corresponding to the plurality of EHS operation commands.

[0109] The apparatus of this embodiment can be used to perform Figure 3 The technical solutions of the method embodiments shown are similar in principle and in effect, and will not be described again here.

[0110] In implementation, each step of the above method embodiments can be completed by integrated logic circuits in the processor hardware or by instructions in software form. The processor can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. A general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in this application can be directly implemented by a hardware encoding processor, or by a combination of hardware and software modules in the encoding processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method.

[0111] The memory mentioned in the above embodiments can be volatile memory or non-volatile memory, or may include both. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM). It should be noted that the memory used in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0112] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0113] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0114] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0115] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0116] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0117] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0118] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for executing memory operations, used to execute multiple aggregated memory operations, characterized in that, include: The Universal Flash Storage (UFS) host controller generates operation commands, which include a Universal Flash Storage Protocol Information Unit (UPIU) frame header and an Extension Header (EHS) field. The UPIU frame header includes an EHS total length field, indicating that the length of the EHS is not zero. The EHS is used to indicate the storage addresses corresponding to multiple EHS operation commands. These multiple EHS operation commands indicate an aggregation of multiple read operations, multiple write operations, or multiple erase operations planned for execution and sent from the UFS host controller to the Universal Flash Storage (UFS) device controller via a single operation command. The UFS host controller sends the operation command to the general flash storage UFS device controller; The UFS host controller receives from the UFS device controller the results of performing corresponding memory operations at the storage addresses corresponding to the plurality of EHS operation commands.

2. The method according to claim 1, characterized in that, The UPIU frame header includes the number of the plurality of EHS operation commands.

3. The method according to claim 1 or 2, characterized in that, The UPIU frame header includes the logical block start address and total data length corresponding to the multiple EHS operation commands.

4. The method according to claim 1 or 2, characterized in that, The multiple EHS operation commands are used to indicate multiple read operations, multiple write operations, or multiple erase operations; the memory addresses corresponding to the multiple EHS operation commands are either consecutive or non-consecutive.

5. The method according to claim 4, characterized in that, The EHS includes the logical block start address and data length corresponding to the multiple EHS operation commands.

6. The method according to claim 1 or 2, characterized in that, The multiple EHS operation commands are used to indicate multiple read operations; the memory addresses corresponding to the multiple EHS operation commands are consecutive.

7. The method according to claim 6, characterized in that, The EHS includes the physical page numbers corresponding to the plurality of EHS operation commands.

8. A method for executing memory operations, used to execute multiple aggregated memory operations, characterized in that, include: The Universal Flash Storage (UFS) device controller receives operation commands from the Universal Flash Storage (UFS) host controller. These operation commands include a Universal Flash Storage Protocol Information Unit (UPIU) frame header and an Extension Header (EHS) field. The UPIU frame header includes a total length field for the EHS, indicating that the length of the EHS is not zero. The EHS is used to indicate the storage addresses corresponding to multiple EHS operation commands. These multiple EHS operation commands indicate an aggregation of multiple read operations, multiple write operations, or multiple erase operations planned for execution and sent from the UFS host controller to the Universal Flash Storage (UFS) device controller via a single operation command. The UFS device controller determines the storage address corresponding to the plurality of EHS operation commands according to the operation command; The UFS device controller performs corresponding memory operations on the storage addresses corresponding to the multiple EHS operation commands respectively; The UFS device controller returns to the UFS host controller the result of performing the corresponding memory operation at the memory address corresponding to the plurality of EHS operation commands.

9. The method according to claim 8, characterized in that, The UPIU frame header includes the number of the plurality of EHS operation commands.

10. The method according to claim 8 or 9, characterized in that, The UPIU frame header includes the logical block start address and total data length corresponding to the multiple EHS operation commands.

11. The method according to claim 8 or 9, characterized in that, The multiple EHS operation commands are used to indicate multiple read operations, multiple write operations, or multiple erase operations; the memory addresses corresponding to the multiple EHS operation commands are either consecutive or non-consecutive.

12. The method according to claim 11, characterized in that, The EHS includes the logical block start address and data length corresponding to the multiple EHS operation commands.

13. The method according to claim 8 or 9, characterized in that, The multiple EHS operation commands are used to indicate multiple read operations; the memory addresses corresponding to the multiple EHS operation commands are consecutive.

14. The method according to claim 13, characterized in that, The EHS includes the physical page numbers corresponding to the plurality of EHS operation commands.

15. A universal flash storage UFS host controller, characterized in that, include: Processor and interface circuits; among which, The processor is configured to perform the method as described in any one of claims 1 to 7.

16. A universal flash storage (UFS) device for performing multiple aggregated memory operations, characterized in that, include: Processor, interface circuitry, and storage media; among which, The interface circuit is used to receive operation commands from the Universal Flash Storage (UFS) host controller. The operation commands include a Universal Flash Storage Protocol Information Unit (UPIU) frame header and an Extension Header (EHS) field. The UPIU frame header includes an EHS total length field, which indicates that the length of the EHS is not zero. The EHS is used to indicate the storage address corresponding to each of the multiple EHS operation commands. The multiple EHS operation commands indicate an aggregation of multiple read operations, multiple write operations, or multiple erase operations that are planned to be executed and sent from the UFS host controller to the Universal Flash Storage (UFS) device controller through a single operation command. The processor is configured to determine the storage addresses corresponding to the plurality of EHS operation commands according to the operation commands; perform corresponding memory operations on the storage medium at the storage addresses corresponding to the plurality of EHS operation commands; and return the results of performing the corresponding memory operations at the storage addresses corresponding to the plurality of EHS operation commands to the UFS host controller.

17. The device according to claim 16, characterized in that, The UPIU frame header includes the number of the plurality of EHS operation commands.

18. The device according to claim 16 or 17, characterized in that, The UPIU frame header includes the logical block start address and total data length corresponding to the multiple EHS operation commands.

19. The device according to claim 16 or 17, characterized in that, The multiple EHS operation commands are used to indicate multiple read operations, multiple write operations, or multiple erase operations; the memory addresses corresponding to the multiple EHS operation commands are either consecutive or non-consecutive.

20. The device according to claim 19, characterized in that, The EHS includes the logical block start address and data length corresponding to the multiple EHS operation commands.

21. The device according to claim 16 or 17, characterized in that, The multiple EHS operation commands are used to indicate multiple read operations; the memory addresses corresponding to the multiple EHS operation commands are consecutive.

22. The device according to claim 21, characterized in that, The EHS includes the physical page numbers corresponding to the plurality of EHS operation commands.

23. A computer-readable storage medium, characterized in that, Includes a computer program, which, when executed on a computer, causes the computer to perform the method of any one of claims 1-14.

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