Receiver detection system and receiver detection device

Abstract

A receiver detection apparatus and a receiver detection system are disclosed. The receiver detection system includes a media access control circuit, a common mode voltage detector and a receiver detector. The common mode voltage detector is arranged to detect whether a common mode voltage satisfies a voltage condition, and to send a ready completion signal to the receiver detector when the common mode voltage satisfies the voltage condition. The receiver detector is arranged to start a detection procedure in response to the ready completion signal and a detection start signal from the media access control circuit. In the detection procedure, the receiver detector sends a detection signal for determining whether a receiver exists, and outputs a detection result to the media access control circuit, wherein the detection result indicates whether the receiver exists. The receiver detection system can avoid starting the detection procedure by the receiver detector before the common mode voltage satisfies the voltage condition.

Description

Technical Field

[0001] This invention relates to detection systems and apparatus, and more particularly to detection systems and apparatus capable of detecting the presence of a receiver. Background Technology

[0002] According to the Peripheral Component Interconnect Express (PCIe) protocol or the Universal Serial Bus (USB) protocol, when a transmitter is inactive, it enters a suspend state to conserve power. During this state, the transmitter's common-mode voltage (i.e., the sum of its pair of differential output signals) drops to zero volts (0V). When the transmitter is awakened, it transitions from the suspend state to a resume state, during which the common-mode voltage gradually rises from 0V to... After the common-mode voltage begins to rise, the transmitter sends a detection signal to determine whether a receiver is present.

[0003] In practice, this common-mode voltage climbs from 0V to... The rise time is affected by the impedance (e.g., resistors and capacitors) on an external printed circuit board and the length of a transmission line. Depending on the impedance and length, the rise time can range from tens of nanoseconds to milliseconds, with a significant difference between the minimum and maximum rise times. If the common-mode voltage rises to... Before that, the transmitter sends the detection signal, and the transmitter may receive an incorrect detection result.

[0004] To address the uncertain rise time, current technology involves delaying the transmitter's media access control (MAC) circuitry as much as possible when the transmitter sends the detection signal, allowing the common-mode voltage sufficient time to rise. However, if the media access control circuit consistently delays the time when the transmitter sends the detection signal, this will cause the time for the transmitter to transition from the idle state to the recovery state to increase, thereby reducing the performance of the transmitter. Summary of the Invention

[0005] One of the purposes of this disclosure is to provide a receiver detection system and a receiver detection device to avoid the problems of the aforementioned prior art.

[0006] One embodiment of the receiver detection system disclosed herein includes a media access control circuit, a common-mode voltage detector, and a receiver detector. The common-mode voltage detector detects whether a common-mode voltage meets a voltage condition, and upon meeting the voltage condition, sends a readiness completion signal to the receiver detector. The receiver detector initiates a detection procedure based on the readiness completion signal and a detection start signal from the media access control circuit. In this detection procedure, the receiver detector sends a detection signal to determine the presence of a receiver, and then outputs a detection result to the media access control circuit, wherein the detection result indicates the presence of the receiver.

[0007] In the above embodiments, the voltage condition includes: the common-mode voltage is not less than 70% of a standard common-mode voltage; and the common-mode voltage is not greater than 130% of the standard common-mode voltage, wherein the standard common-mode voltage is 50% of a power supply voltage.

[0008] One embodiment of the receiver detection apparatus disclosed herein includes the aforementioned common-mode voltage detector and receiver detector.

[0009] The features, implementation, and technical effects of the present invention are described in detail below with reference to the accompanying drawings, and preferred embodiments are described in detail. Attached Figure Description

[0010] Figure 1 An embodiment of the receiver detection system of this disclosure is shown; and

[0011] Figure 2 This invention illustrates one embodiment of the receiver detection apparatus of the present disclosure.

[0012] Symbol Explanation

[0013] 100: Receiver Detection System

[0014] 110: Media Access Control Circuit

[0015] 120: Common-mode voltage detector

[0016] 130: Receiver Detector

[0017] RCV_DETECT: Detect start signal

[0018] VCM_READY: Ready signal complete

[0019] DET_SIGNAL: Detection signal

[0020] RXDET: Detection Results

[0021] ENDDET: Detection end signal

[0022] 200: Receiver detection device

[0023] 210: Common-mode voltage detector

[0024] 220: Receiver Detector Detailed Implementation

[0025] This specification discloses a receiver detection system and a receiver detection device. The system and device prevent a receiver detector from prematurely starting to detect the presence of a receiver, thereby avoiding erroneous detection results.

[0026] Figure 1 This invention illustrates one embodiment of the receiver detection system disclosed herein. Figure 1 The receiver detection system 100 includes a media access control (MAC) circuit 110, a common-mode voltage detector 120, and a receiver detector 130.

[0027] Please see Figure 1 The media access control circuit 110 transmits a detection start signal (RCV_DETECT) to the receiver detector 130. In one implementation example, the receiver detection system 100 is applied to a transmitter (not shown) that conforms to the Peripheral Component Interconnect Express (PCIe) protocol or the Universal Serial Bus (USB) protocol. The media access control circuit 110 sends the detection start signal when the transmitter enters a resume state from a suspend state. It is worth noting that, where feasible, the receiver detection system 100 can be applied to devices conforming to other protocols.

[0028] Please see Figure 1 A common-mode voltage detector 120 is used to detect whether a common-mode voltage meets a voltage condition, and after the common-mode voltage meets the voltage condition, sends a readiness signal (VCM_READY) to the receiver detector 130. In one implementation example, the common-mode voltage detector 120 includes a known / custom-developed comparator; the comparator is used to compare the common-mode voltage with at least one voltage threshold, so that the common-mode voltage detector 120 can determine whether the common-mode voltage meets the voltage condition. In one implementation example, the common-mode voltage detector 120 includes a known / custom-developed analog-to-digital converter; the analog-to-digital converter is used to convert the common-mode voltage into a digital value, so that the common-mode voltage detector 120 can know the magnitude of the common-mode voltage based on the digital value, thereby determining whether the common-mode voltage meets the voltage condition.

[0029] As described above, in one implementation example, the voltage condition includes "the common-mode voltage reaches a standard common-mode voltage." In another implementation example, the voltage condition includes "the common-mode voltage is not less than 70% of a standard common-mode voltage." In yet another implementation example, the voltage condition includes "the common-mode voltage is not greater than 130% of the standard common-mode voltage." In one implementation example, the standard common-mode voltage is 50% of a power supply voltage (VDD). In yet another implementation example, the standard common-mode voltage is the sum of a pair of differential output signals of the aforementioned transmitter (e.g., a high-speed output positive signal (HSOP) and a high-speed output negative signal (HSON) conforming to the PCIe / USB protocol). It is worth noting that the aforementioned voltage conditions and standard common-mode voltage may be determined according to implementation requirements. It is also worth noting that the media access control circuit 110 sends the detection start signal at a first time point, and the common mode voltage detector 120 detects that the common mode voltage meets the voltage condition at a second time point. The first time point is usually earlier than the second time point.

[0030] Please see Figure 1 The receiver detector 130 is used to initiate a detection procedure based on the aforementioned detection start signal (RCV_DETECT) and readiness completion signal (VCM_READY). In this detection procedure, the receiver detector 130 sends a detection signal (DET_SIGNAL) to determine the presence of a receiver, and then outputs a detection result (RXDET) to the media access control circuit 110, indicating the presence of the receiver. For example, when the receiver is present, the detection result is a first level (e.g., high level) voltage, and when the receiver is not present, the detection result is a second level (e.g., low level) voltage. It is worth noting that the receiver detector 130 itself can be used to determine the presence of a receiver, or a device containing the receiver detector 130 (e.g., the aforementioned transmitter) can be used to determine the presence of a receiver and then report a determination result to the receiver detector 130. Since this invention focuses on when the detection procedure begins rather than how to determine the presence of a receiver, the technical details of determining the presence of a receiver are omitted here.

[0031] As described above, in one implementation example, the detection procedure conforms to the PCIe / USB protocol; however, this is not a limitation of the present invention. In one implementation example, the receiver detector 130 itself is used to determine the presence of a receiver, and the detection signal is a pulse signal; the intermediate voltage of the signal range of the pulse signal is substantially equal to the common-mode voltage. In one implementation example, the detection signal is a notification signal; the notification signal is used to request the device including the receiver detector 130 to determine the presence of a receiver. In one implementation example, the receiver detector 130 is further used to send a detection end signal (ENDDET) to the media access control circuit 130 when the detection sequence ends; however, this is not a limitation of the present invention.

[0032] Figure 2 This invention illustrates one embodiment of the receiver detection apparatus of the present disclosure. Figure 2 The receiver detection device 200 includes a common-mode voltage detector 210 and a receiver detector 220. One embodiment of the common-mode voltage detector 210 is... Figure 1 The common-mode voltage detector 120. One embodiment of the receiver detector 220 is... Figure 1 The receiver detector 130. The detection start signal (RCV_DETECT) is generated by... Figure 1 The media access control circuit 110 or its equivalent circuit is emitted. As can be seen by those skilled in the art... Figure 1 The details and variations of the receiver detection device 200 are explained through embodiments; repetitive and redundant descriptions are omitted here.

[0033] It is worth noting that, where implementation is possible, those skilled in the art may selectively implement some or all of the technical features in any of the foregoing embodiments, or selectively implement a combination of some or all of the technical features in the foregoing multiple embodiments, in order to achieve the flexibility of implementation of the present invention.

[0034] In summary, the receiver detection system and apparatus disclosed herein can prevent a receiver detector from prematurely starting to detect the presence of a receiver, thereby avoiding erroneous detection results.

[0035] While the embodiments of the present invention have been described above, these embodiments are not intended to limit the present invention. Those skilled in the art can make changes to the technical features of the present invention based on the explicit or implicit content of the present invention, and all such changes may fall within the scope of patent protection sought by the present invention. In other words, the scope of patent protection of the present invention shall be determined by the claims of this specification.

Claims

1. A receiver detection system, comprising a media access control circuit, a common-mode voltage detector, and a receiver detector, wherein: The common-mode voltage detector is used to detect whether a common-mode voltage meets a voltage condition, and after the common-mode voltage meets the voltage condition, it sends a preparation completion signal to the receiver detector. The receiver detector is used to start a detection procedure based on the preparation completion signal and a detection start signal from the media access control circuit. as well as In this detection procedure, the receiver detector sends a detection signal to determine whether a receiver exists, and then outputs a detection result to the media access control circuit, wherein the detection result indicates whether the receiver exists, and the receiver detection system is applied to a transmitter; when the transmitter enters a recovery state from a standby state, the media access control circuit sends the detection start signal.

2. The receiver detection system of claim 1, wherein the receiver detector is further configured to send a detection end signal to the media access control circuit when the detection procedure ends.

3. The receiver detection system as claimed in claim 1, wherein the voltage condition includes: the common-mode voltage is not less than 70% of a standard common-mode voltage.

4. The receiver detection system of claim 1, wherein the media access control circuit sends the detection start signal at a first time point, the common-mode voltage detector detects that the common-mode voltage meets the voltage condition at a second time point, and the first time point is earlier than the second time point.

5. A receiver detection device, comprising a common-mode voltage detector and a receiver detector, wherein: The common-mode voltage detector is used to detect whether a common-mode voltage meets a voltage condition, and after the common-mode voltage meets the voltage condition, it sends a preparation completion signal to the receiver detector. The receiver detector is used to start a detection procedure based on the preparation completion signal and a detection start signal of a media access control circuit. as well as In this detection procedure, the receiver detector sends a detection signal to determine the presence of a receiver, and then outputs a detection result to the media access control circuit, wherein the detection result indicates whether the receiver exists. The receiver detection device is applied to a transmitter; when the transmitter enters a recovery state from a standby state, the common-mode voltage detector receives the detection start signal.

6. The receiver detection apparatus of claim 5, wherein the receiver detector is further configured to send a detection end signal to the media access control circuit when the detection procedure ends.

7. The receiver detection device as claimed in claim 5, wherein the voltage condition includes: the common-mode voltage is not less than 70% of a standard common-mode voltage.

8. The receiver detection apparatus of claim 5, wherein the common-mode voltage detector receives the detection start signal at a first time point, the common-mode voltage detector detects that the common-mode voltage meets the voltage condition at a second time point, and the first time point is earlier than the second time point.

Images