Overlay mark mask layout

Abstract

The application provides a mask layout of overlay marks, comprising a main pattern area and a scribe lane pattern area surrounding the main pattern area, wherein the main pattern area comprises a first mark pattern for corresponding formation of a first overlay mark in a device area of a chip, and the scribe lane pattern area comprises a second mark pattern for corresponding formation of a second overlay mark in a scribe lane area of the chip. The mask layout of overlay marks is used to form the first overlay mark in the device area and the second overlay mark in the scribe lane area, so that overlay variation in the device area can be accurately simulated, and overlay variation of each layer of photolithography patterns in the center position of the device area can be accurately measured.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a mask layout with overlapping marks. Background Technology

[0002] In existing semiconductor manufacturing processes, before semiconductor devices are fabricated from wafers, wafer layout design is required. This involves dividing the wafer into several dies and scribe lanes located between the dies. The dies are used to subsequently form semiconductor devices, while the scribe lanes serve as dividing lines for the dies during the packaging stage after semiconductor device fabrication. When designing the photolithographic pattern used to divide the wafer surface into dies and scribe lanes, photolithographic patterns required for the photolithography process, such as alignment marks and overlay marks, are typically formed on the scribe lanes.

[0003] As the integration level of semiconductor devices continues to increase and the feature size of devices continues to shrink, the accuracy of the overlay between photolithographic patterns of each layer has an increasingly important impact on the overall yield of the wafer. Summary of the Invention

[0004] The purpose of this invention is to provide a mask pattern with overlapping marks to solve the problem of low overlap accuracy between photolithographic patterns of different layers.

[0005] To solve the above-mentioned technical problems, the present invention provides a mask layout for overlapping marks, including a main pattern area and a dicing pattern area surrounding the main pattern area, wherein the main pattern area includes a first mark pattern for correspondingly forming a first overlapping mark in the device area of ​​the chip, and the dicing pattern area includes a second mark pattern for correspondingly forming a second overlapping mark in the dicing area of ​​the chip.

[0006] Preferably, in the mask layout of the overlapping marks, the first mark pattern includes a marked graphic area and a dummy graphic area surrounding the marked graphic area, wherein any position on the edge of the dummy graphic area is equidistant from the marked graphic area.

[0007] Preferably, in the mask layout of the overlapping marks, the marking graphic area includes: four sub-graphic areas of equal area, the four sub-graphic areas being diagonally distributed in pairs, wherein two of the diagonally distributed sub-graphic areas each include a plurality of first strip patterns arranged along a first direction and parallel to each other, and the other two diagonally distributed sub-graphic areas each include a plurality of second strip patterns arranged along a second direction and parallel to each other, wherein the first direction and the second direction are perpendicular to each other.

[0008] Preferably, in the mask layout of the overlapping marks, the marking graphic area is a square area.

[0009] Preferably, in the mask layout of the overlapping marks, the mask layout includes a plurality of first mark patterns, which are spaced apart in the main graphic area.

[0010] Preferably, in the mask layout of the overlapping marks, at least one of the first mark patterns is formed at the center of the main graphic area.

[0011] Preferably, in the mask layout of the overlapping marks, the critical size of the first overlapping mark formed by the first mark pattern is the same as the critical size of the second overlapping mark formed by the second mark pattern.

[0012] Preferably, in the mask layout of the overlapping marks, the size of the first mark pattern is x times the size of the second mark pattern, and the x times is designed according to the layout transformation rules.

[0013] Preferably, in the mask layout of the overlapping marks, the second mark pattern is formed at a position where the cutting pattern area is equidistant from the two adjacent main pattern areas.

[0014] Preferably, in the mask layout of the stacking marks, the film layer forming the device region of the first stacking mark and the film layer forming the dicing region of the second stacking mark using the mask layout have the same structure, so that the stacking change of the chip can be measured simultaneously through the first stacking mark and the second stacking mark.

[0015] In summary, the present invention provides a mask layout for overlay marks, including a main pattern area and a dicing pattern area surrounding the main pattern area. The main pattern area includes a first mark pattern for correspondingly forming a first overlay mark within a chip device area, and the dicing pattern area includes a second mark pattern for correspondingly forming a second overlay mark within a chip dicing area. The mask layout for overlay marks is used to form the first overlay mark in the device area and the second overlay mark in the dicing area. By forming the first overlay mark in the device area and the second overlay mark in the dicing area, overlay variations within the device area can be accurately simulated, thus improving the accuracy of measuring the overlay between different lithographic patterns. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of a first overlapping mark formed by a first mark pattern according to an embodiment of the present invention;

[0017] Figure 2This is a schematic diagram showing the distribution of overlapping marks in the device area and the dicing area according to an embodiment of the present invention;

[0018] Figure 3 This is a schematic diagram of the first stack pair marker merging rule according to an embodiment of the present invention;

[0019] Figure 4 This is a schematic diagram of the initial target size of the first stacked pair of marks according to an embodiment of the present invention;

[0020] Figure 5 This is a schematic diagram of the enlarged target size of the first stacked pair of marks according to an embodiment of the present invention;

[0021] Figure 6 This is a schematic diagram showing the reduced size of the enlarged target size of the first stacked pair of marks according to an embodiment of the present invention;

[0022] The labels for the attached figures are as follows:

[0023] 1-First overlapping mark; 2-Second overlapping mark; 3-First mark pattern;

[0024] 30 - Identified graphic area; 31 - Dummy graphic area;

[0025] 301 - First bar pattern; 302 - Second bar pattern. Detailed Implementation

[0026] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a more detailed explanation of the mask layout for overlapping marks proposed in this invention. The advantages and features of this invention will become clearer from the following description and claims. It should be noted that the drawings are all in a very simplified form and use non-precise scales, intended only to facilitate and clarify the illustration of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structure. In particular, different figures may emphasize different aspects and sometimes use different scales.

[0027] It should be understood that when describing the structure of a device, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above another layer or region, or that other layers or regions are contained between it and another layer or region. Furthermore, if the device is flipped, the layer or region will be located "below" or "under" another layer or region. Additionally, the terms "first," "second," etc., describe various elements, components, areas, layers, and / or portions, but these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below can be referred to as a second element, component, area, layer, or portion.

[0028] In chip manufacturing, structurally speaking, it's similar to building a house, where layers are stacked one on top of the substrate. A certain level of alignment must be maintained between each layer to ensure the final chip functions correctly. The alignment accuracy between layers is defined as the stacking variation precision. Currently, existing stacking variation measurement technologies only use stacking marks in the chip dicing area to measure the stacking variation between layers.

[0029] However, when simulating the overlap changes between the photolithographic patterns of each layer of a large-size chip, the chip device area is large while the number of chip dicing areas is reduced, resulting in a reduction in the number of overlap marks located in the chip dicing areas. If the overlap changes between layers are measured only by the overlap marks located in the chip dicing areas, the overlap changes within the chip device area cannot be accurately measured, especially the overlap changes at the center position inside the device area cannot be accurately measured.

[0030] To address the aforementioned technical problems, this embodiment provides a mask layout with overlapping markers. Please refer to [link to relevant documentation]. Figure 1 and Figure 2 It includes: a main pattern area and a slit pattern area surrounding the main pattern area, wherein the main pattern area includes a first mark pattern 3 for correspondingly forming a first stacked pair mark 1 in the device area of ​​the chip, and the slit pattern area includes a second mark pattern for correspondingly forming a second stacked pair mark 2 in the slit pattern area of ​​the chip.

[0031] The first marking pattern 3 includes a marking graphic area 30 and a dummy graphic area 31 surrounding the marking graphic area 30, wherein any position on the edge of the dummy graphic area 31 is equidistant from the marking graphic area 30. Preferably, the marking graphic area 30 is a square area.

[0032] For example, the side length a of the first stacked mark 1 is 30 micrometers, the side length b of the marking graphic area 30 is 18 micrometers, and the minimum distance d between any position on the edge of the dummy graphic area 31 and the edge of the marking area is 6 micrometers.

[0033] It is worth noting that the function of the dummy pattern area 31 is to prevent the first stacked pair of markers 1 formed on the chip device area from affecting the integrated capacitors and resistors on the chip, and further affecting the final electrical properties of the chip.

[0034] For further details, please continue to see Figure 1 The identification graphic area 30 includes four sub-graphic areas of equal area, which are diagonally distributed in pairs. Two of the diagonally distributed sub-graphic areas each include multiple first stripe patterns 301 arranged parallel to each other along a first direction, and the other two diagonally distributed sub-graphic areas each include multiple second stripe patterns 302 arranged parallel to each other along a second direction. The first and second directions are perpendicular. This facilitates the measurement of overlap changes of the first overlap mark 1 formed in the chip device area in the first and second directions.

[0035] Furthermore, the mask layout includes a plurality of first mark patterns 3, which are spaced apart in the main pattern area, with at least one first mark pattern 3 formed at the center of the main pattern area. The plurality of first mark patterns 3 improves the measurement accuracy of overlap variations in the device area.

[0036] Please see Figure 3 , Figure 3 This is a schematic diagram of the first stack pair mark merging rule. To facilitate layout routing, there is a distance L between two adjacent first stack pair marks 1. Optionally, L is 30μm.

[0037] The key dimensions of the first overlapping mark 1 formed by the first mark pattern 3 are the same as the key dimensions of the second overlapping mark 2 formed by the second mark pattern.

[0038] Specifically, in one embodiment of the present invention, the mask pattern fabrication process is as follows: First, a chromium film substrate is formed by depositing chromium nitride-chromium oxynitride photosensitive material on a smooth glass (or quartz) substrate using DC magnetron sputtering; then, a layer of photoresist or electron beam resist is uniformly coated onto the chromium film substrate to form a top-coated chromium plate, which is the photomask substrate and an ideal photosensitive blank for fabricating miniature geometric patterns; finally, miniature geometric patterns derived from the original integrated circuit design are printed on the photomask substrate using photolithography, thus completing the mask pattern fabrication process. After obtaining the mask pattern, wafer production can then commence.

[0039] It's worth noting that the aforementioned layout conversion process generates data for mask fabrication through layer calculations. This primarily involves designing the cut lines according to the chip dimensions based on the mask's size specifications. During layout setup, the standard critical dimension for overlay markers is divided using an equal-division method to obtain the required overlay markers. For example, if the standard critical dimension is 8 micrometers, the width occupied by the standard critical dimension can be divided into three width regions: 2.6 micrometers, 2.8 micrometers, and 2.6 micrometers, to set the overlay markers.

[0040] After the above layout conversion process, due to the layout conversion rules, the structure of the device area will be reduced by 1 / x times. Therefore, in order to ensure that the key dimensions of the first stacked pair mark 1 formed in the device area and the second stacked pair mark 2 formed in the cut channel area are consistent, it is preferable that the size of the first mark pattern 3 is x times the size of the second mark pattern, and the x times is designed according to the layout conversion rules.

[0041] For example, after layout conversion, the structure of the device area will be reduced by 0.9 times. In order to ensure that the key dimensions of the first stack pair mark 1 and the second stack pair mark 2 are consistent, the size of the first mark pattern 3 will be increased by 1 / 0.9 times.

[0042] Please refer to Table 1 below (the unit in Table 1 is nm) and follow the instructions. Figures 4-6 , Figures 4-6 These are schematic diagrams showing the initial target size of the first stack of markers, the enlarged target size of the first stack of markers, and the reduced size of the enlarged target size of the first stack of markers.

[0043] Initial target 800 171 429 200 Enlarged target 889 190 477 200 Enlarged target after shrink 800.1 171 429.3 180

[0044] Table 1

[0045] Pitch refers to the distance between the centers of two target graphics, namely D1, which is the sum of the line width and space of the target graphics. In this embodiment, the line width includes CD_CT and CD_P1, namely D2 and D3; the space between them is Bias, namely D4+D5.

[0046] Based on the table above, the initial target size pitch is 800. Since the structure of the device area will shrink by 0.9 times after layout conversion, the target size pitch is 800*(1 / 0.9)=889. Similarly, the target sizes of CD_CT and CD_P1 can be obtained, which will not be elaborated here.

[0047] Furthermore, when measuring the overlap change of the photolithography patterns of each layer of the chip using the first overlap mark 1 and the second overlap mark 2, it is necessary to detect the first overlap mark 1 and the second overlap mark 2 simultaneously to obtain the corresponding optical signals. Based on the optical signals, the position information of the first overlap mark 1 and the second overlap mark 2 is obtained. Preferably, the second mark pattern is formed at a position where the distance between the dicing pattern area and the two adjacent main pattern areas is equal, so that the distance between the second overlap mark 2 formed in the dicing pattern area of ​​the chip and the two adjacent chip device areas is equal. This ensures that when acquiring the optical signal, the distance between the photoresist above the second overlap mark 2 and the chip device areas on both sides is equal, the photoresist has high flatness, and thus the measured signal intensity is high.

[0048] In this embodiment, the film layer forming the device region of the first stacking mark 1 and the film layer forming the dicing region of the second stacking mark 2 using the mask layout have the same structure, so that the stacking change of the chip can be measured simultaneously through the first stacking mark 1 and the second stacking mark 2.

[0049] The specific forms of the first stacking mark 1 and the second stacking mark 2 can be varied. For example, the stacking mark has one or more non-flat structures, where "non-flat structure" can be either a depression or a protrusion. When the stacking mark has multiple non-flat structures, these multiple non-flat structures can be the same or different. Furthermore, the protruding and recessed structures themselves can also be varied. Taking a recessed structure as an example, the recessed structure can be a circular hole, a square hole, or a rectangular groove. In some embodiments, the stacking marks are parallel grating structures with a certain interval between them. The width and height of the stacking marks can be set according to actual needs, and the embodiments of the present invention do not impose specific limitations.

[0050] When performing stacking change measurement, it is necessary to simultaneously measure the stacking change of the first stacking mark 1 located in the device area and the second stacking mark 2 located in the dicing area of ​​the same layer relative to the corresponding stacking mark of the previous layer. Therefore, it is necessary to ensure that the first stacking mark 1 and the second stacking mark 2 have the same underlying film layer structure.

[0051] In summary, embodiments of the present invention provide a mask layout for overlapping marks, including a main pattern area and a dicing pattern area surrounding the main pattern area. The main pattern area includes a first mark pattern for correspondingly forming a first overlapping mark within a chip device area, and the dicing pattern area includes a second mark pattern for correspondingly forming a second overlapping mark within a chip dicing area. By using the mask layout for overlapping marks to form the first overlapping mark in the device area and the second overlapping mark in the dicing area, the overlapping changes within the device area can be accurately simulated, particularly enabling accurate measurement of the overlapping changes of each layer of photolithography pattern at the center of the device area.

[0052] Furthermore, it should be understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention shall still fall within the scope of protection of the present invention.

Claims

1. A mask layout with overlapping markers, characterized in that, include: The main pattern area and the dicing pattern area surrounding the main pattern area, wherein the main pattern area includes a plurality of first mark patterns for correspondingly forming a first stacked pair of marks in the device area of ​​the chip, and the dicing pattern area includes a second mark pattern for correspondingly forming a second stacked pair of marks in the dicing area of ​​the chip. In this configuration, multiple first mark patterns are spaced apart in the main graphic area, and at least one first mark pattern is formed at the center of the main graphic area. The size of the first mark pattern is x times the size of the second mark pattern. The x times is designed according to the layout conversion rules so that the critical size of the first overlapping mark formed by the first mark pattern is the same as the critical size of the second overlapping mark formed by the second mark pattern.

2. The mask layout with overlapping marks as described in claim 1, characterized in that, The first marking pattern includes: The graphic area is a designated graphic area and a virtual graphic area surrounding the designated graphic area, wherein any position on the edge of the virtual graphic area is equidistant from the designated graphic area.

3. The mask layout with overlapping marks as described in claim 2, characterized in that, The identification graphic area includes four sub-graphic areas of equal area, which are diagonally distributed in pairs. Two of the diagonally distributed sub-graphic areas each include multiple first strip patterns arranged along a first direction and parallel to each other. The other two diagonally distributed sub-graphic areas each include multiple second strip patterns arranged along a second direction and parallel to each other. The first direction and the second direction are perpendicular to each other.

4. The mask layout with overlapping marks as described in claim 2, characterized in that, The graphic area of ​​the logo is a square area.

5. The mask layout with overlapping marks as described in claim 1, characterized in that, The second marking pattern is formed at a position where the cutting pattern area is equidistant from the two adjacent main pattern areas.

6. The mask layout with overlapping marks as described in claim 1, characterized in that, The film layer forming the device region of the first stacked pair mark and the film layer forming the dicing region of the second stacked pair mark are structurally identical, so that the stacking changes of the chip can be measured simultaneously through the first stacked pair mark and the second stacked pair mark.

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