Fpga instance code compiling method and device, terminal equipment and server

Abstract

The embodiment of the present application provides a FPGA instance code compiling method, device, terminal equipment and server, the method applied to the terminal equipment comprises: receiving a first input; in response to the first input, obtaining an instance code file of a field programmable logic gate array (FPGA) to be compiled; sending the instance code file to a server; receiving a compiling result sent by the server, wherein the compiling result is a result of compiling the instance code file. Therefore, in the embodiment of the present application, the compiling of the FPAG instance code can be automatically performed without frequent manual operations, thereby reducing the labor cost. Moreover, the compiling process is performed by the server, and after the compiling is completed, the compiling result can be viewed on the terminal equipment, thereby making the compiling process no longer affect the use of other functions of the terminal equipment.

Description

Technical Field

[0001] This invention relates to the field of mobile communication technology, and in particular to an FPGA example code compilation method, apparatus, terminal device and server. Background Technology

[0002] Currently, compiling versions of Field Programmable Gate Arrays (FPGAs) requires a significant amount of manual work. Specifically, the project manager first identifies requirements or vulnerabilities, then assigns the task to an FPGA engineer for code modification. Sometimes, modifications are required for multiple modules. However, since the module owners are different, after each module owner has completed their code modifications, the code needs to be managed uniformly, and the changes need to be compiled into a single project before being compiled together.

[0003] During compilation, the compiler needs to open the project, set the strategies for each implementation, and then execute the compilation. Vivado's compilation steps are synthesis, implementation, and then generating bitstream files, taking over 10 hours with no option to close the compilation terminal during the process. Furthermore, after the version compilation is complete, a CIV version bitstream file needs to be generated based on the board model. Manually generating the bitstream file from the ".dcp" file output by the version compilation takes approximately 30 minutes. Additionally, after generating the bitstream file, the compilation report needs to be manually reviewed to select the best implementation, and the corresponding bitstream file is downloaded to the test environment for functional verification.

[0004] As mentioned above, the compilation time for FPAG versions and the generation of bit files are both quite long, and the compilation terminal cannot be closed midway. Prolonged compilation in the terminal can easily affect the use of other functions. Furthermore, manually opening the project, viewing the report, and generating the bit file is cumbersome, leading to increased labor costs. Summary of the Invention

[0005] This invention provides an FPGA instance code compilation method, apparatus, terminal device, and server to solve the problems of FPGA version compilation process affecting the use of other functions of the compilation terminal and cumbersome manual operation in the prior art.

[0006] In a first aspect, embodiments of the present invention provide an FPGA instance code compilation method, applied to a terminal device, the method comprising:

[0007] Receive the first input;

[0008] In response to the first input, obtain the instance code file of the field-programmable gate array (FPGA) to be compiled;

[0009] Send the example code file to the server;

[0010] The compiler receives the compilation result sent by the server, wherein the compilation result is the result of compiling the instance code file.

[0011] Optionally, the terminal device is equipped with the open-source software project Jenkins client, and the first input is input in the operation interface of the Jenkins client;

[0012] The process of obtaining the instance code file includes:

[0013] Obtain the remote repository branch information associated with the first input;

[0014] Download the project source code file stored in the remote repository branch indicated by the remote repository branch information, and identify the downloaded project source code file as the example code file.

[0015] Optionally, the terminal device is equipped with a Jenkins client;

[0016] Sending the instance code file to the server includes:

[0017] The example code file is sent to the server corresponding to the account logged into the Jenkins client.

[0018] Optionally, the terminal device has a Jenkins client installed; the method further includes:

[0019] Receive the second input from the operation interface of the Jenkins client;

[0020] In response to the second input, obtain the virtual machine server node information associated with the second input;

[0021] Send the virtual machine server node information to the server, wherein the virtual machine server node information is used to instruct the server to compile the instance code file on the node indicated by the virtual machine server node information.

[0022] Optionally, after receiving the compilation result sent by the server, the method further includes:

[0023] A notification message is sent to a pre-determined account, wherein the notification message includes the linking information of the compilation result, the identification information of the instance code file, and an indication of whether the compilation was successful.

[0024] Secondly, embodiments of the present invention provide an FPGA instance code compilation method, applied to a server, the method comprising:

[0025] Receive the example code file of the field-programmable gate array sent by the terminal device;

[0026] The example code file is compiled to obtain the compilation result;

[0027] The compilation result is sent to the terminal device.

[0028] Optionally, the server is the server corresponding to the account logged in by the Jenkins client installed on the terminal device.

[0029] Optionally, before compiling the instance code file, the method further includes:

[0030] Receive virtual machine server node information sent by the terminal device;

[0031] The compilation of the instance code file includes:

[0032] On the node indicated by the virtual machine server node information, the instance code file is compiled.

[0033] Optionally, compiling the instance code file includes:

[0034] Invoke a pre-determined first script and execute the first script;

[0035] The first script is used to instruct the following:

[0036] A pre-determined second script is invoked and executed, wherein the second script instructs the restoration of the project file for the field-programmable gate array based on the example code file; and

[0037] When the project file is restored, a pre-determined third script is invoked and executed, wherein the third script is used to instruct the project file to be compiled.

[0038] Optionally, obtaining the compilation result includes:

[0039] Obtain a quality report and generate a preset version of the bitstream file;

[0040] The quality report and the bitstream file are identified as the compilation result;

[0041] The quality report includes the compilation time and target information of the instance code file;

[0042] The target information includes at least one of the following:

[0043] The number of predetermined warnings of each level generated by the target process, wherein the target process is the various interface implementation processes included in the compilation process of the instance code file;

[0044] The compilation time of each of the target processes;

[0045] The number and utilization rate of available resources in the example code file;

[0046] Timing information in the timing report of the target process;

[0047] The power information in the power report of the target process.

[0048] Optionally, obtaining the quality report and generating a preset version of the bitstream file includes:

[0049] When the example code file is compiled, a pre-determined fourth script is invoked and executed.

[0050] The fourth script is used to instruct the following:

[0051] A predetermined fifth script is invoked and executed, wherein the fifth script is used to instruct the acquisition of the compilation time of the instance code file and to write the compilation time into the quality report;

[0052] A predetermined sixth script is invoked and executed, wherein the sixth script is used to instruct the generation of the preset version of the bitstream file;

[0053] Obtain the target information and write it into the quality report.

[0054] Optionally, compiling the instance code file includes:

[0055] If an error is detected in one of the interface implementation processes included in the compilation process of the instance code file, skip at least one of the following processes:

[0056] Get the compilation time of the interface implementation process that caused the error;

[0057] Obtain the predetermined number of alarms at each level generated during the error-reporting interface implementation process;

[0058] Retrieve timing information from the timing report of the interface implementation that reported the error;

[0059] Retrieve power information from the power report of the interface implementation that reported the error.

[0060] Optionally, the method further includes:

[0061] The compilation results are uploaded to the Artifactory platform, a repository server software.

[0062] Thirdly, embodiments of the present invention provide a terminal device, including a memory, a transceiver, and a processor:

[0063] A memory for storing computer programs; a transceiver for sending and receiving data under the control of the processor; and a processor for reading the computer programs from the memory and performing the following operations:

[0064] Receive the first input;

[0065] In response to the first input, obtain the instance code file of the field-programmable gate array (FPGA) to be compiled;

[0066] Control the transceiver to send the instance code file to the server;

[0067] The transceiver is controlled to receive the compilation result sent by the server, wherein the compilation result is the result of compiling the instance code file.

[0068] Optionally, the terminal device has a Jenkins client installed, and the first input is input in the operation interface of the Jenkins client; the process by which the processor obtains the instance code file includes:

[0069] Obtain the remote repository branch information associated with the first input;

[0070] Download the project source code file stored in the remote repository branch indicated by the remote repository branch information, and identify the downloaded project source code file as the example code file.

[0071] Optionally, the terminal device is equipped with a Jenkins client; the transceiver sends the instance code file to the server, including:

[0072] The transceiver sends the instance code file to the server corresponding to the account logged into the Jenkins client.

[0073] Optionally, the terminal device is equipped with a Jenkins client; the processor is further configured to:

[0074] Receive the second input from the operation interface of the Jenkins client;

[0075] In response to the second input, obtain the virtual machine server node information associated with the second input;

[0076] The transceiver is controlled to send the virtual machine server node information to the server, wherein the virtual machine server node information is used to instruct the server to compile the instance code file on the node indicated by the virtual machine server node information.

[0077] Optionally, the transceiver is also used for:

[0078] A notification message is sent to a pre-determined account, wherein the notification message includes the linking information of the compilation result, the identification information of the instance code file, and an indication of whether the compilation was successful.

[0079] Fourthly, embodiments of the present invention provide a server, including a memory, a transceiver, and a processor:

[0080] A memory for storing computer programs; a transceiver for sending and receiving data under the control of the processor; and a processor for reading the computer programs from the memory and performing the following operations:

[0081] An example code file for controlling the transceiver to receive field-programmable gate arrays sent by the terminal device;

[0082] The example code file is compiled to obtain the compilation result;

[0083] The transceiver is controlled to send the compilation result to the terminal device.

[0084] Optionally, the server is the server corresponding to the account logged in by the Jenkins client installed on the terminal device.

[0085] Optionally, the transceiver is further configured to: receive virtual machine server node information sent by the terminal device;

[0086] When the processor compiles the instance code file, it is specifically used for:

[0087] On the node indicated by the virtual machine server node information, the instance code file is compiled.

[0088] Optionally, when the server compiles the instance code file, it specifically performs the following:

[0089] Invoke a pre-determined first script and execute the first script;

[0090] The first script is used to instruct the following:

[0091] A pre-determined second script is invoked and executed, wherein the second script instructs the restoration of the project file for the field-programmable gate array based on the example code file; and

[0092] When the project file is restored, a pre-determined third script is invoked and executed, wherein the third script is used to instruct the project file to be compiled.

[0093] Optionally, when the processor obtains the compilation result, it is specifically used for:

[0094] Obtain a quality report and generate a preset version of the bitstream file;

[0095] The quality report and the bitstream file are identified as the compilation result;

[0096] The quality report includes the compilation time and target information of the instance code file;

[0097] The target information includes at least one of the following:

[0098] The number of predetermined warnings of each level generated by the target process, wherein the target process is the various interface implementation processes included in the compilation process of the instance code file;

[0099] The compilation time of each of the target processes;

[0100] The number and utilization rate of available resources in the example code file;

[0101] Timing information in the timing report of the target process;

[0102] The power information in the power report of the target process.

[0103] Optionally, when the processor acquires the quality report and generates a preset version of the bitstream file, it is specifically used for:

[0104] When the example code file is compiled, a pre-determined fourth script is invoked and executed.

[0105] The fourth script is used to instruct the following:

[0106] A predetermined fifth script is invoked and executed, wherein the fifth script is used to instruct the acquisition of the compilation time of the instance code file and to write the compilation time into the quality report;

[0107] A predetermined sixth script is invoked and executed, wherein the sixth script is used to instruct the generation of the preset version of the bitstream file;

[0108] Obtain the target information and write it into the quality report.

[0109] Optionally, when the processor compiles the instance code file, it specifically performs the following:

[0110] If an error is detected in one of the interface implementation processes included in the compilation process of the instance code file, skip at least one of the following processes:

[0111] Get the compilation time of the interface implementation process that caused the error;

[0112] Obtain the predetermined number of alarms at each level generated during the error-reporting interface implementation process;

[0113] Retrieve timing information from the timing report of the interface implementation that reported the error;

[0114] Retrieve power information from the power report of the interface implementation that reported the error.

[0115] Optionally, the transceiver is also used for:

[0116] The compilation results are uploaded to the Artifactory platform, a repository server software.

[0117] Fifthly, embodiments of the present invention provide an FPGA instance code compilation apparatus, applied to a terminal device, the apparatus comprising:

[0118] The first receiving module is used to receive the first input;

[0119] The code file acquisition module is used to acquire the instance code file of the field-programmable gate array (FPGA) to be compiled in response to the first input;

[0120] The first sending module is used to send the instance code file to the server;

[0121] The second receiving module is used to receive the compilation result sent by the server, wherein the compilation result is the result of compiling the instance code file.

[0122] Sixthly, embodiments of the present invention provide an FPGA instance code compilation apparatus, applied to a server, the apparatus comprising:

[0123] The third receiving module is used to receive the example code file of the field-programmable gate array sent by the terminal device;

[0124] The compilation module is used to compile the example code file and obtain the compilation result;

[0125] The second sending module is used to send the compilation result to the terminal device.

[0126] In a seventh aspect, embodiments of the present invention also provide a processor-readable storage medium storing a computer program for causing the processor to perform the methods described in the first or second aspect.

[0127] In this embodiment of the invention, after receiving the first input, the terminal device can obtain the instance code file of the FPGA to be compiled, and then send the instance code file to the server for compilation, and the server returns the compilation result to the terminal device. Therefore, in this embodiment of the invention, after receiving the first input, the terminal device can automatically obtain the instance code file of the FPGA to be compiled and send it to the server for compilation. Thus, in this embodiment of the invention, the compilation of FPGA instance code can be performed automatically without frequent manual operation, thereby reducing labor costs. Furthermore, the compilation process is executed by the server, and after compilation is complete, the compilation result can be viewed on the terminal device, so that the compilation process does not affect the use of other functions of the terminal device. Attached Figure Description

[0128] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0129] Figure 1 A flowchart illustrating the steps of an FPGA example code compilation method provided in this embodiment of the invention;

[0130] Figure 2 A flowchart illustrating the steps of another FPGA example code compilation method provided in this embodiment of the invention;

[0131] Figure 3 A flowchart illustrating a specific implementation of the FPGA example code compilation method provided in this embodiment of the invention;

[0132] Figure 4 This is a schematic diagram of the Jenkins task display interface in an embodiment of the present invention;

[0133] Figure 5 This is a schematic diagram of the configuration interface for GIT repository branch information and virtual machine server node information in an embodiment of the present invention;

[0134] Figure 6This is a schematic diagram illustrating the calling of various scripts involved in the FPGA instance code compilation method in this embodiment of the invention;

[0135] Figure 7 This is a schematic diagram illustrating the result of executing the vivadoRuntime.sh script to calculate the compilation time of an IMPL in an embodiment of the present invention;

[0136] Figure 8 This is a schematic diagram showing the quality report in an embodiment of the present invention;

[0137] Figure 9 This is a schematic diagram illustrating the linking information of the compilation results displayed on the Artifactory platform in an embodiment of the present invention;

[0138] Figure 10 This is a schematic diagram showing the display of a notification email in an embodiment of the present invention;

[0139] Figure 11 A structural block diagram of an FPGA instance code compilation device provided in an embodiment of the present invention;

[0140] Figure 12 A structural block diagram of another FPGA example code compilation device provided in an embodiment of the present invention;

[0141] Figure 13 This is a structural block diagram of a terminal device provided in an embodiment of the present invention;

[0142] Figure 14 This is a structural block diagram of a server provided in an embodiment of the present invention. Detailed Implementation

[0143] In this embodiment of the invention, the term "and / or" describes the relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. The character " / " generally indicates that the preceding and following associated objects have an "or" relationship.

[0144] In this embodiment of the invention, the term "multiple" refers to two or more, and other quantifiers are similar.

[0145] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0146] This invention provides an FPGA instance code compilation method, apparatus, terminal device, and server to solve the problems in the prior art where the FPGA version compilation process affects the use of other functions of the compilation terminal, and where manual operation is cumbersome.

[0147] The method and apparatus are based on the same concept of the application. Since the methods and apparatus solve problems in similar ways, the implementation of the apparatus and methods can refer to each other, and the repeated parts will not be described again.

[0148] Furthermore, the technical solutions provided in this invention can be applied to various systems, especially 5th Generation Mobile Communication Technology (5G) systems. For example, applicable systems include Global System for Mobile Communication (GSM), Code Division Multiple Access (CDMA), Wideband Code Division Multiple Access (WCDMA) General Packet Radio Service (GPRS), Long Term Evolution (LTE), LTE Frequency Division Duplex (FDD), LTE Time Division Duplex (TDD), Long Term Evolution Advanced (LTE-A), Universal Mobile Telecommunication System (UMTS), Worldwide Interoperability for Microwave Access (WiMAX), and 5G New Radio (NR). All of these systems include terminal equipment and network equipment. The system may also include a core network component, such as the Evloved Packet System (EPS) or the 5G system (5GS).

[0149] The terminal devices involved in the embodiments of this invention can be devices that provide voice and / or data connectivity to users, handheld devices with wireless connectivity, or other processing devices connected to a wireless modem. The names of the terminal devices may differ in different systems; for example, in a 5G system, a terminal device can be called User Equipment (UE). Wireless terminal devices can communicate with one or more core networks (CNs) via a Radio Access Network (RAN). Wireless terminal devices can be mobile terminal devices, such as mobile phones (or "cellular" phones) and computers with mobile terminal devices, for example, portable, pocket-sized, handheld, computer-embedded, or vehicle-mounted mobile devices that exchange voice and / or data with the RAN. Examples include Personal Communication Service (PCS) phones, cordless phones, Session Initiated Protocol (SIP) phones, Wireless Local Loop (WLL) stations, and Personal Digital Assistants (PDAs). Wireless terminal equipment can also be referred to as a system, subscriber unit, subscriber station, mobile station, mobile station, remote station, access point, remote terminal, access terminal, user terminal, user agent, or user device, but is not limited to these terms in this embodiment of the invention.

[0150] The server involved in this embodiment of the invention can be a base station, which may include multiple cells providing services to terminals. Depending on the specific application, the base station may also be called an access point, or a device in the access network that communicates with the wireless terminal device through one or more sectors on the air interface, or other names. The server can be used to exchange received air frames with Internet Protocol (IP) packets, acting as a router between the wireless terminal device and the rest of the access network, where the rest of the access network may include an Internet Protocol (IP) communication network. The server can also coordinate the attribute management of the air interface. For example, the server involved in the embodiments of the present invention can be a server (Base Transceiver Station, BTS) in a Global System for Mobile communications (GSM) or Code Division Multiple Access (CDMA), a server (NodeB) in Wide-band Code Division Multiple Access (WCDMA), an evolved Node B (eNB or e-NodeB) in a long term evolution (LTE) system, a 5G base station (gNB) in a next generation system, a Home evolved Node B (HeNB), a relay node, a femto, a pico, etc., and is not limited in the embodiments of the present invention. In some network structures, the server may include a centralized unit (CU) node and a distributed unit (DU) node, and the centralized unit and distributed unit may also be geographically separated.

[0151] Servers and terminal devices can each use one or more antennas for Multiple-Input Multiple-Output (MIMO) transmission. MIMO transmission can be Single-User MIMO (SU-MIMO) or Multiple-User MIMO (MU-MIMO). Depending on the configuration and number of antenna combinations, MIMO transmission can be 2D-MIMO, 3D-MIMO, FD-MIMO, or massive-MIMO, and can also be diversity transmission, pre-coding transmission, or beamforming transmission, etc.

[0152] Figure 1 This diagram illustrates a flowchart of an FPGA example code compilation method provided by an embodiment of the present invention. This method is applied to terminal devices, such as... Figure 1 As shown, the method may include the following steps 301 to 304:

[0153] Step 101: Receive the first input.

[0154] The first input is used to trigger the execution of subsequent steps 102 to 104, namely, to trigger the acquisition of the instance code file of the FPGA to be compiled, thereby sending the acquired instance code file to the server for compilation, and then receiving the compilation result of the instance code file returned by the server.

[0155] In addition, the first input can be text input, voice input, or selection input of content displayed on the relevant operation interface.

[0156] Step 102: In response to the first input, obtain the example code file of the FPGA to be compiled.

[0157] The FPGA example code file to be compiled is a pre-edited FPGA example code file. Alternatively, the FPGA example code file to be compiled can be an FPGA example code file stored locally on the terminal device, or an FPGA example code file stored on other devices.

[0158] Step 103: Send the example code file to the server.

[0159] After receiving the instance code file, the server compiles the instance code file, obtains the compilation result, and then sends the compilation result to the terminal device.

[0160] Step 104: Receive the compilation result sent by the server, wherein the compilation result is the result of compiling the instance code file.

[0161] As can be seen from steps 101 to 104 above, in the embodiments of the present invention, after receiving the first input, the terminal device can automatically obtain the FPGA instance code file to be compiled, and then send the instance code file to the server for compilation. Therefore, in the embodiments of the present invention, the compilation of FPGA instance code can be performed automatically without frequent manual operation, thereby reducing labor costs. Furthermore, the compilation process is executed by the server, and after compilation is completed, the compilation result can be viewed on the terminal device, so that the compilation process does not affect the use of other functions of the terminal device.

[0162] Optionally, the terminal device is equipped with an open-source software project (Jenkins) client, and the first input is input in the operation interface of the Jenkins client;

[0163] The process of obtaining the instance code file includes:

[0164] Retrieve the remote (GIT) repository branch information associated with the first input;

[0165] Download the project source code file stored in the remote repository branch indicated by the remote repository branch information, and identify the downloaded project source code file as the example code file.

[0166] Among them, Jenkins is an open-source software project, an integration tool developed based on Java, mainly used for continuously and automatically building / testing software projects, monitoring the operation of external tasks, etc.; Git repository is an open-source distributed version control system that can effectively and quickly handle version management of projects ranging from small to very large, and can also be applied to Linux systems.

[0167] In addition, the first input in the Jenkins client's interface can be text or voice input of remote (GIT) repository branch information, or it can be the selection of one of the GIT repository branches displayed in the interface.

[0168] Therefore, in the embodiments of the present invention, the FPGA instance code file to be compiled can be stored in a GIT repository. When compilation is required, the project source code file stored in the set GIT repository branch can be determined as the FPGA instance code file to be compiled by setting the GIT repository branch information in the Jenkins client.

[0169] In addition, when compiling FPGA instance code files through the Jenkins client, operators can first create a Jenkins task in the Jenkins client and set the GIT repository branch information during the creation of the Jenkins task. This will enable the terminal device to automatically download the project source code to be compiled from the GIT repository branch to the WORKSPACE folder in the default working path of Jenkins after the Jenkins task initialization is completed.

[0170] As can be seen from the above, in the embodiments of the present invention, the Git repository branch can be flexibly selected.

[0171] Furthermore, it should be noted that when there are too many versions of FPGA instance code files required, and different people are responsible for modifying the code, inconsistencies in code, baseline versions, and timing constraints can occur during compilation. This can lead to unusable compilation results after a long period of time, wasting a significant amount of development time and manpower. In the embodiments of this invention, using a Git repository for source code management can generate version numbers and baseline versions in a uniform format, reducing inconsistencies in code versions and thus improving development efficiency.

[0172] Optionally, the terminal device is equipped with a Jenkins client;

[0173] Sending the instance code file to the server includes:

[0174] The example code file is sent to the server corresponding to the account logged into the Jenkins client.

[0175] Therefore, when participating in the compilation of FPGA instance code through the Jenkins client, the terminal device can send the FPGA instance code file to be compiled to the server corresponding to the account logged into the Jenkins client, so that the server can compile the received instance code.

[0176] Optionally, the terminal device has a Jenkins client installed; the method further includes:

[0177] Receive the second input from the operation interface of the Jenkins client;

[0178] In response to the second input, obtain the virtual machine server node information associated with the second input;

[0179] Send the virtual machine server node information to the server, wherein the virtual machine server node information is used to instruct the server to compile the instance code file on the node indicated by the virtual machine server node information.

[0180] The second input in the Jenkins client's interface can be text or voice input of virtual machine server node information, or it can be the selection input of one of the candidate virtual machine server node information displayed in the interface.

[0181] In addition, when compiling FPGA instance code files through the Jenkins client, the operator can first create a Jenkins task in the Jenkins client and set the virtual machine server node information during the creation of the Jenkins task. This allows the terminal device to obtain the FPGA instance code to be compiled, send the instance code to the server, and compile the instance code in the node indicated by the virtual machine server node information on the server.

[0182] As can be seen from the above, in the embodiments of the present invention, the virtual machine server node for compiling FPGA instance code in the server can also be flexibly selected.

[0183] Optionally, after receiving the compilation result sent by the server, the method further includes:

[0184] A notification message is sent to a pre-determined account, wherein the notification message includes the linking information of the compilation result, the identification information of the instance code file, and an indication of whether the compilation was successful.

[0185] The identification information may include at least one of the following: the name of the project to which the instance code file belongs, the project number, and the identifier of the user who initiated the compilation (e.g., name, employee number); the pre-determined account may include a pre-determined email address.

[0186] Therefore, after compilation is complete, the terminal device can automatically send a notification message to a pre-determined account so that relevant personnel can view the compilation results in a timely manner.

[0187] Optionally, the compilation result includes a quality report and a preset version of the bitstream file, wherein the quality report includes the compilation time and target information of the example code file;

[0188] The target information includes at least one of the following:

[0189] The number of predetermined warnings of each level generated by the target process, wherein the target process is the various interface implementation (IMPL) processes included in the compilation process of the instance code file;

[0190] The compilation time of each of the target processes;

[0191] The number and utilization rate of available resources in the example code file;

[0192] Timing information in the timing report of the target process;

[0193] The power information in the power report of the target process.

[0194] The aforementioned bitstream file is the final file of the FPGA design, downloaded to the application environment to implement FPGA functionality. The IMPL process refers to "implementation," i.e., placement and routing, connecting the gate-level netlist generated after "synthesis." There are many ways to connect these netlists, so different strategies need to be used in parallel processing. Here, "synthesis," or the SYNTH process, converts the circuit logic described in the FPGA code into basic logic units such as AND gates, NOT gates, OR gates, and flip-flops.

[0195] Additionally, the runme.log files generated during each IMPL process included in the compilation can be read to obtain the number of alarms of each predetermined level (i.e., normal alarms and critical alarms) mentioned above. The runme.log file records the process of all system printouts during the IMPL process, including detailed information such as compilation time, alarms, and errors for each part of the compilation process.

[0196] According to the resource report of IMPL, the number and usage rate of resources available in the instance code file can be statistically analyzed. The resources available in the instance code file are mainly resources on the baseband board, including look-up tables (LUTs), first input first output (FIFOs), block random access memory (BRAM), ultra-volatile memory (URAM), and multiply-accumulators (DSPs).

[0197] The timing and power information can be extracted from the timing and power reports of each IMPL process included in the compilation process. The timing information can include the worst negative timing margin (WNS), total negative timing margin (TNS), worst hold timing margin (WHS), and total hold timing margin (THS), which can reflect the compilation quality. The power information includes the FPGA static power consumption calculated based on the compilation process.

[0198] Furthermore, when an FPGA instance code includes multiple IMPL procedures, these IMPL procedures are executed in parallel during compilation. Therefore, the compilation time of an FPGA instance code is the longest compilation time among these IMPL procedures. When an IMPL procedure includes multiple flows (i.e., design), these flows are executed serially. Therefore, the compilation time of an IMPL is the sum of the compilation times of its individual flows.

[0199] Therefore, in the embodiments of the present invention, the compilation quality of FPGA instance code can be visualized. That is, after compilation, the above quality report can be read directly, thereby comparing the differences in implementation strategies of different versions of FPGA instance code and comparing the compilation quality differences between this compilation and previous versions. Therefore, in the embodiments of the present invention, the FPGA version quality can be more conveniently and intuitively reflected.

[0200] Figure 2 This diagram illustrates a flowchart of another FPGA example code compilation method provided by an embodiment of the present invention. This method is applied to servers, such as... Figure 2 As shown, the method may include the following steps 201 to 203:

[0201] Step 201: Receive the example code file of the field-programmable gate array sent by the terminal device.

[0202] Upon receiving a first input, the terminal device can, in response to that first input, obtain the instance code file of the FPGA to be compiled, and then send the instance code file to the server. The first input can be text input, voice input, or selection input of content displayed on a relevant operation interface.

[0203] In addition, the example code file is a pre-edited FPGA example code file.

[0204] Step 202: Compile the example code file to obtain the compilation result.

[0205] Step 203: Send the compilation result to the terminal device.

[0206] As can be seen from steps 201 to 203 above, after receiving the first input, the terminal device can obtain the instance code file of the FPGA to be compiled, and then send the instance code file to the server for compilation, and then return the compilation result to the terminal device. Therefore, in this embodiment of the invention, after receiving the first input, the terminal device can automatically obtain the instance code file of the FPGA to be compiled, and then send the instance code file to the server for compilation.

[0207] Therefore, in the embodiments of the present invention, after receiving the first input, the terminal device can automatically obtain the FPGA instance code file to be compiled, and then send the instance code file to the server for compilation. Thus, in the embodiments of the present invention, the compilation of the FPGA instance code can be performed automatically without frequent manual operation, thereby reducing labor costs. Furthermore, the compilation process is executed by the server, and after compilation is complete, the compilation results can be viewed on the terminal device, ensuring that the compilation process does not affect the use of other functions of the terminal device.

[0208] Optionally, the server is the server corresponding to the account logged in by the Jenkins client installed on the terminal device.

[0209] Therefore, when the Jenkins client installed on the terminal device participates in the compilation of FPGA instance code, the terminal device can send the FPGA instance code file to be compiled to the server corresponding to the account logged into the Jenkins client, so that the server can compile the received instance code.

[0210] Optionally, before compiling the instance code file, the method further includes:

[0211] Receive virtual machine server node information sent by the terminal device;

[0212] The compilation of the instance code file includes:

[0213] On the node indicated by the virtual machine server node information, the instance code file is compiled.

[0214] The terminal device can be equipped with a Jenkins client. When the terminal device receives a second input from the Jenkins client's operation interface (such as text or voice input of virtual machine server node information, or selection input of one of the virtual machine server node information among the candidate virtual machine server node information displayed in the Jenkins client's operation interface), it can obtain the virtual machine server node information associated with the second input and then send the obtained virtual machine server node information to the server.

[0215] As can be seen from the above, in the embodiments of the present invention, the virtual machine server node for compiling FPGA instance code in the server can also be flexibly selected.

[0216] Optionally, compiling the instance code file includes:

[0217] Invoke a pre-determined first script and execute the first script;

[0218] The first script is used to instruct the following:

[0219] A pre-determined second script is invoked and executed, wherein the second script instructs the restoration of the project file for the field-programmable gate array based on the example code file; and

[0220] When the project file is restored, a pre-determined third script is invoked and executed, wherein the third script is used to instruct the project file to be compiled.

[0221] It should be noted that the first, second, and third scripts mentioned above are pre-written. Specifically, when the server compiles the example code file by calling the first, second, and third scripts, these scripts need to be pre-configured in the server so that they can be successfully called when the server needs to compile the FPGA example code.

[0222] As can be seen from the above, executing the first script is used to achieve the following functions:

[0223] First, the second script is called and executed to restore the FPGA project file based on the example code file mentioned above. Then, when the FPGA project file is restored, the third script is called and executed to compile the project file.

[0224] Furthermore, the specific process of compiling the above-mentioned project files can be as follows: open the restored FPGA project file, then start the SYNTH process of FPGA compilation, and wait for the SYNTH process to end; start the parallel execution of multiple IMPLs, and wait for all IMPL processes to end; generate bitstream files of all available IMPLs and various data reports (such as IMPL resource reports, IMPL process timing reports and power reports) in parallel.

[0225] The SYNTH process refers to "synthesis," which converts the circuit logic described in the FPGA code into basic logic units such as AND gates, NOT gates, OR gates, and flip-flops. The IMPL process refers to "implementation," which is placement and routing, connecting the gate-level netlist generated after synthesis. There are many ways to connect the netlists, so different strategies need to be used in parallel.

[0226] Alternatively, the restored FPGA project files can be opened using the Vivado software installed on the server. Vivado is an integrated design environment that provides scalable data models and a universal debugging environment for FPGA development and simulation.

[0227] Optionally, obtaining the compilation result includes:

[0228] Obtain a quality report and generate a preset version of the bitstream file;

[0229] The quality report and the bitstream file are identified as the compilation result;

[0230] The quality report includes the compilation time and target information of the instance code file;

[0231] The target information includes at least one of the following:

[0232] The number of predetermined warnings of each level generated by the target process, wherein the target process is the various interface implementation processes included in the compilation process of the instance code file;

[0233] The compilation time of each of the target processes;

[0234] The number and utilization rate of available resources in the example code file;

[0235] Timing information in the timing report of the target process;

[0236] The power information in the power report of the target process.

[0237] In the embodiments of the present invention, the above compilation results include the above quality report and the above preset version of the bitstream file.

[0238] Specifically, it can read the runme.log files generated during each IMPL process included in the compilation process, thereby obtaining the number of alarms of each predetermined level (i.e., ordinary alarms and critical alarms) mentioned above; the runme.log file records the process of all system printouts during the IMPL process, including detailed information such as compilation time, alarms, and errors for each part of the compilation process.

[0239] According to the resource report of IMPL, the number and usage rate of the resources available in the instance code file can be counted. The resources available in the instance code file are mainly resources on the baseband board, including LUT, FIFO, BRAM, URAM, and DSP.

[0240] The timing and power information can be extracted from the timing and power reports of each IMPL process included in the compilation process. The timing information may include WNS, TNS, WHS, and THS, which can reflect the compilation quality. The power information includes the FPGA static power consumption calculated based on the compilation process.

[0241] Therefore, in the embodiments of the present invention, the compilation quality of FPGA instance code can be visualized. That is, after compilation, the above quality report can be read directly, thereby comparing the differences in implementation strategies of different versions of FPGA instance code and comparing the compilation quality differences between this compilation and previous versions. Therefore, in the embodiments of the present invention, the FPGA version quality can be more conveniently and intuitively reflected.

[0242] Optionally, obtaining the quality report and generating a preset version of the bitstream file includes:

[0243] When the example code file is compiled, a pre-determined fourth script is invoked and executed.

[0244] The fourth script is used to instruct the following:

[0245] A predetermined fifth script is invoked and executed, wherein the fifth script is used to instruct the acquisition of the compilation time of the instance code file and to write the compilation time into the quality report;

[0246] A predetermined sixth script is invoked and executed, wherein the sixth script is used to instruct the generation of the preset version of the bitstream file;

[0247] Obtain the target information and write it into the quality report.

[0248] It should be noted that the fourth, fifth, and sixth scripts mentioned above are pre-written. Specifically, when the server uses these scripts to obtain the compilation results, the pre-written scripts need to be configured in the server so that after the server has completed compiling the FPGA example code, it can call these scripts to obtain the compilation results.

[0249] As can be seen from the above, executing the fourth script is used to achieve the following functions:

[0250] The fifth script is invoked and executed to obtain the compilation time of the instance code file, and the compilation time is written into the quality report; the sixth script is invoked and executed to generate the preset version of the bitstream file; the above target information is obtained and written into the quality report.

[0251] The aforementioned preset version can be a CIV version, thus, in embodiments of the present invention, a CIV version bitstream file can be generated. In the prior art, Vivado software can only generate ordinary version bitstream files during automatic compilation, and cannot process files specific to certain boards. Therefore, to make the compilation process more complete, embodiments of the present invention can generate CIV version bitstream files. Here, CIV represents the chip type.

[0252] Optionally, compiling the instance code file includes:

[0253] If an error is detected in one of the interface implementation processes included in the compilation process of the instance code file, skip at least one of the following processes:

[0254] Get the compilation time of the interface implementation process that caused the error;

[0255] Obtain the predetermined number of alarms at each level generated during the error-reporting interface implementation process;

[0256] Retrieve timing information from the timing report of the interface implementation that reported the error;

[0257] Retrieve power information from the power report of the interface implementation that reported the error.

[0258] In the compilation process of FPGA example code, errors are frequently encountered, so IMPLs are generally compiled in parallel. If one IMPL reports an error, it may cause errors in the scripts for writing bitstream files or calculating compilation time, leading to the entire compilation process stopping. To avoid this, in this embodiment of the invention, the rumme.log file of the IMPL process can be read to check for errors. If errors are found, the process of calculating the compilation time, number of alarms, timing information, and power information of the IMPL process in this report is skipped, preventing the automated compilation platform from stopping due to IMPL errors.

[0259] Optionally, the method further includes:

[0260] The compilation results are uploaded to the Artifactory platform, a repository server software.

[0261] Artifactory is a Maven repository server software that can be used to build a Maven repository on an intranet, facilitating the uploading and publishing of internal company libraries to improve the ease of use of shared code. Therefore, uploading the compilation results to the Artifactory platform allows users to easily retrieve them.

[0262] In summary, the specific implementation method of the FPGA example code compilation method of this invention is as follows:

[0263] The FPGA example code compilation method of this invention is applied to a terminal device and a server. The terminal device has a Jenkins client installed, and the server has a Jenkins server and Vivado software installed.

[0264] like Figure 3 As shown, in this embodiment of the invention, Jenkins automatic deployment tasks are used to achieve overall control of a series of automated processes, including calling the GIT repository to download the project source code, starting automatic compilation, providing result feedback, and extracting compilation results. The specific implementation process of this automated process is described in detail below through steps H1 to H8:

[0265] To facilitate understanding of the following process, the correspondence between the various scripts involved in the process and the aforementioned first and sixth scripts is explained as follows:

[0266] The first script corresponds to the Makefile script below, the second script corresponds to the setup.tcl script below, the third script corresponds to the Compile.tcl script below, the fourth script corresponds to the Ctrl.sh script below, the fifth script corresponds to the vivadoRuntime.sh script below, and the sixth script corresponds to the Gen_civbit_plp1 / 2.tcl script below.

[0267] Step H1: After receiving the startup command for the Jenkins client, the terminal device opens the Jenkins client.

[0268] Step H2: After the terminal device receives the operation to create a Jenkins task, or the terminal device receives an interface to the Jenkins task (such as...), Figure 4 After clicking on one of the Jenkins tasks shown in the image, the Jenkins task configuration interface (as shown) is displayed. Figure 5 As shown in the image, this allows users to configure Jenkins tasks through the configuration interface, such as configuring Git repository branch information and virtual machine server node information. Figure 5 In this context, "branch" means a branch, that is, in Figure 5 The options following "branch" allow you to configure Git repository branch information; Figure 5 In this context, "node" represents a node, that is, in Figure 5 The options following "node" allow you to configure virtual machine server node information.

[0269] Among them, Figure 4 The display shows four columns of information, from left to right: "Jenkins task name, current time since the last successful compilation, current time since the last failed compilation, duration of the last compilation, and currently configured virtual machine server node information." Figure 4 In this context, “HBPOF_PLP1_MC, HBPOF_PLP1_MC_TAG, HBPOF_PLP1_SC, HBPOF_PLP1_SC_TAG, HBPOF_PLP2, HBPOF_PLP2_TAG” represent different Jenkins task names; “FPGA-NODE05, FPGA-NODE01, FPGA-NODE06, FPGA-NODE08” represent different virtual machine server node information.

[0270] Step H3: After the Jenkins task configuration is complete, the Jenkins task is initialized. After the Jenkins task initialization is complete, the source code of the project to be compiled (i.e. the FPGA instance code file to be compiled) is automatically downloaded from the configured GIT repository branch to the WORKSPACE file in the default working path of Jenkins. Then, the source code of the project in the WORKSPACE file is transferred to the server corresponding to the Jenkins login account.

[0271] Step H4: After receiving the aforementioned project source code file, the server calls and executes the pre-stored Makefile script to compile the aforementioned project source code.

[0272] Specifically, such as Figure 6 As shown, the Makefile script is used to control the restoration of the project and the script that starts the compilation process, and provides relevant instructions that are called by the Jenkins built-in script. That is, the Jenkins built-in script starts the setup.tcl script with the command "make setup" to restore the project, and after the project is restored, it starts the Compile.tcl script (i.e., the automatic compilation script) with the command "make all" to compile.

[0273] In order to facilitate transmission and storage, the automated compilation platform was designed to use the setup.tcl script generated by the Vivado software itself, and the FPGA project files were restored by transferring the project source code from the aforementioned WORKSPACE file.

[0274] In addition, Compile.tcl is an FPGA compilation script. The process of compiling the restored FPGA project file by the Compile.tcl script includes: first, calling the Vivado software installed on the server to open the restored FPGA project file, then starting the SYNTH process of FPGA compilation and waiting for the SYNTH process to end; starting multiple IMPLs to execute in parallel and waiting for all IMPL processes to end; generating bitstream files of all available IMPLs and various data reports (such as IMPL resource reports, IMPL process timing reports and power reports) in parallel.

[0275] Step H5: After compilation is complete, call and execute the Ctrl.sh script to obtain the compilation results.

[0276] The Ctrl.sh script, written in shell scripting, controls the execution after compilation. Shell scripts are similar to batch files in Windows and are used on Linux systems running FPGA cluster servers. They pre-load various commands into a single file for convenient one-time execution, offering higher efficiency compared to Windows.

[0277] Specifically, such as Figure 6 As shown, the Jenkins built-in script waits for the compilation to complete before launching the Ctrl.sh script. First, it determines the version of the currently compiled project source code based on the aforementioned project source code, so that different versions of the CIV bitstream files can be processed differently. For example, different versions of the project source code files will generate CIV bitstream files with different names.

[0278] After determining the version of the source code of the project being compiled, perform the following process:

[0279] The vivadoRuntime.sh script is started to collect the compilation time and write it into the quality report. The compilation time is the maximum compilation time of each IMPL process included in the compilation process.

[0280] Read the runme.log file generated in each IMPL process, record the number of normal alarms and critical alarms, and according to the resource report of IMPL, count the number and utilization rate of available resources in the project source file of this FPGA version. Calculate the compilation time of each IMPL process included in the compilation process, and extract the timing information and power information from the timing report and power report of each IMPL. Then write all the above-statistical information into the quality report.

[0281] Place the routed.dcp file in the specified location and call the Gen_civbit_plp1 / 2.tcl script to open the routed.dcp file with the Vivado software and generate a CIV version bit stream file; the routed.dcp file includes checkpoints recorded during the compilation process;

[0282] Call the seventh script (i.e. Error.sh script) to check if there is an erroneous IMPL process. If so, skip the statistics of the above-mentioned related information of the erroneous IMPL (i.e., compilation time, number of alarms, timing information and power information).

[0283] It should be noted that the vivadoRuntime.sh script is a script for calculating compilation time, written in shell scripting and invoked by Ctrl.sh. Specifically, for each IMPL process, it calculates the compilation time of that IMPL by summing the processing times of each step in the runme.log file generated by the IMPL process. For example... Figure 7 As shown, an IMPL process includes five flows: link_design, opt_design, place_design, phys_opt_design, and rout_design. The compilation times for these five flows are 12 minutes 30 seconds, 22 minutes 58 seconds, 1 hour 23 minutes 21 seconds, 15 minutes 11 seconds, and 2 hours 10 minutes 48 seconds, respectively. Therefore, the total compilation time of the IMPL is the sum of these five flows (i.e., the total runtime), which is 4 hours 24 minutes 57 seconds. This compilation time is extracted by Ctrl.sh and entered into the quality report.

[0284] Among them, link_design refers to merging the netlist generated by synth into a netlist file; opt_design refers to the logic optimization process; place_desgin refers to improving the layout and reducing latency; phys_opt_design refers to the physical optimization process, which performs timing optimization by copying and moving registers; and route_design refers to the process of connecting the optimized circuit.

[0285] in addition, Figure 7In this context, FINAL indicates completion, Elapsed time refers to the time it takes for the Vivado tool to connect the gate-level netlist instantiated by the SYNTH procedure during the IMPL process; Central Processing Unit (CPU) time refers to the time it takes for the CPU to execute tasks. The connection information needs to be obtained from the project file and requires CPU execution. In multi-processor systems or when using multiple threads, the CPU execution time will exceed the connection's Elapsed time.

[0286] Gen_civbit_plp1 / 2.tcl is a script that generates CIV version bitstream files. The Vivado software's automatic compilation process can only generate standard version bitstream files and cannot handle special boards. Therefore, to make the compilation process more complete, the Gen_civbit_1 / 2.tcl script can be called in Ctrl.sh to generate CIV version bitstream files.

[0287] Error.sh is an error detection script written in shell script. Errors are frequently encountered during FPGA version compilation, so multiple implementations (impls) are typically compiled in parallel. If one of the implements encounters an error, it may cause scripts written by civbit to report errors or track compilation time, leading to the entire compilation process halting. To avoid this, Error.sh reads the rumme.log of the implement to check for errors. If any are found, it skips the information tracking process for that implement, preventing the automated compilation platform from stopping due to implement errors.

[0288] As can be seen from the above, after executing the Ctrl.sh script, the vivadoRuntime.sh script, and the Gen_civbit_plp1 / 2.tcl script, the compilation results include "the aforementioned quality report, all IMPL bit stream files, and civ version bit stream files".

[0289] The quality report can be as follows: Figure 8 As shown. In Figure 8The quality report shown includes information for seven IMPL processes (imp_1, imp_2, imp_3, imp_4, imp_5, imp_6, and imp_7), such as Worst Negative Slack (WNS), Total Negative Slack (TNS), Worst Negative Slack (WHS), Worst Pulse Width Margin (WPWS), Total Pulse Width Margin (TPWS), Elapsed Time, Number of Lookup Tables (LUTs) Used, Number of First Input First Output (FIFOs) Used, Number of Memory Units (BRAM, URAM) Used, Number of Multiply-Accumulators (DSPs) Used, Total Power Rating, Number of Critical Warnings, Number of Design Rule Check Warnings (DRCWarnings), Number of General Warnings, and the number of General Warnings and Critical Warnings for the Synth process. The Elapsed time refers to the time it takes for the Vivado tool to connect the gate-level netlist instantiated by the SYNTH procedure during the IMPL process.

[0290] Step H6: Move the aforementioned compilation results, namely the quality report, all IMPL bitstream files, and civ version bitstream files, to the work directory of the current project for easy extraction by the Jenkins built-in script.

[0291] Step H7: After the Jenkins built-in script completes the automatic compilation, it uploads all files in the work directory of the current compilation project to the Artifactory platform for easy retrieval by users.

[0292] The Artifactory platform allows for the display of compilation results via linked information, for example... Figure 9 As shown, clicking on one of the links will bring up a window to download the compilation results associated with that link, thus downloading the compilation results to the location set in that window.

[0293] Step H9: The server returns the compilation results to the Jenkins client on the terminal device. The Jenkins client then sends an email to the user to notify them whether the compilation was successful and provides a link to the compilation results for the user to view.

[0294] Notification emails can be like... Figure 10As shown, the email may include the project name, project number, build status, person who triggered the compilation, build log address, and build address of the source code of the compiled project. The build log address is the link to the Artifactory platform, and the build address is the address used to navigate to the task interface in the Jenkins client, i.e., clicking... Figure 10 The "specific build address (i.e., http: / / 172.27.14.5:5080 / job / chenkin_fpga_bit / 25 / )" will redirect you to... Figure 4 The interface shown.

[0295] Furthermore, it should be noted that the aforementioned Setup.tcl, Compile.tcl, and Gen_civbit_plp1 / 2.tcl scripts are all written in the TCL language. TCL is a tool control language primarily used to issue commands to interactive programs. It has a simple syntax, strong extensibility, and is supported by most Electronic Design Automation (EDA) tools, including Vivado. TCL programs can be run in two ways: one is by writing the program into a script, usually named with a .tcl extension, and the other is by executing it directly from the TCL command line.

[0296] In summary, the FPGA example code compilation method of this invention has the following advantages:

[0297] 1. Reduce labor costs: The process from compilation to generating a preset version of the bitstream file is changed from manual to automatic, saving the time spent manually opening the project, opening the implementation, and generating the bitstream file;

[0298] 2. Git repository management of project source code makes code more consistent and avoids version inconsistencies, improving development efficiency. Furthermore, project source code, IP files (i.e., IP cores, such as mathematical operations (multipliers, adders, floating-point units, etc.) and signal processing (FFT, DFT, DDS) models) can be directly called when writing code, greatly accelerating development speed) are stored in the Git repository, reducing the storage pressure on each individual cluster or computer.

[0299] 3. Visualization of compilation quality: After compilation, the quality report can be read directly, allowing for comparison of the implementation strategies of different versions of the project source code, and the compilation quality differences between this compilation and previous versions. This makes it easier and more intuitive to reflect the quality of the FPGA version.

[0300] 4. It removes computer limitations, and automatic compilation is performed on a server cluster, which will not cause compilation interruption due to abnormal computer shutdown, thus increasing the stability of version compilation.

[0301] 5. Once compilation is complete, an email notification will be sent, allowing users to promptly process the compilation results.

[0302] Compared to existing technologies, Vivado is the primary tool for compiling FPGA versions. Its use requires storing the project's code and IP files in a designated location, manually opening the project to trigger compilation, and manually generating a bit file (the FPGA version) after compilation. Furthermore, compilers must expend time monitoring for compilation errors. Due to the large amount of data in FPGA projects and the long compilation time, there are significant requirements for computer performance and storage space. When there are too many version requirements, and different personnel are responsible for modifying the code, inconsistencies in code, baseline versions, and timing constraints can arise during compilation, leading to unusable results after long compilation periods and wasting considerable development time and manpower.

[0303] In this embodiment of the invention, a TCL script is generated to restore the FPGA project based on existing code, IP, and timing constraints, and then automatically compile it. This saves time compared to manually opening the project and triggering compilation, and reduces the error rate of manual compilation. A Git repository is used for source code management to resolve inconsistencies in code and baseline versions. The Jenkins platform is used to trigger compilation, extract compilation results, and generate compilation quality reports, providing more intuitive feedback on the FPGA version's compilation quality.

[0304] The above describes the FPGA example code compilation method provided by the embodiments of the present invention. The FPGA example code compilation device provided by the embodiments of the present invention will be described below with reference to the accompanying drawings.

[0305] See Figure 11 This invention also provides an FPGA instance code compilation device for use in terminal devices, the device comprising:

[0306] The first receiving module 1301 is used to receive the first input;

[0307] The code file acquisition module 1302 is used to acquire the instance code file of the field-programmable gate array FPGA to be compiled in response to the first input;

[0308] The first sending module 1303 is used to send the instance code file to the server;

[0309] The second receiving module 1304 is used to receive the compilation result sent by the server, wherein the compilation result is the result of compiling the instance code file.

[0310] Optionally, the terminal device is equipped with the open-source software project Jenkins client, and the first input is input in the operation interface of the Jenkins client;

[0311] The code file retrieval module 1302 is specifically used for:

[0312] Obtain the remote repository branch information associated with the first input;

[0313] Download the project source code file stored in the remote repository branch indicated by the remote repository branch information, and identify the downloaded project source code file as the example code file.

[0314] Optionally, the terminal device is equipped with a Jenkins client;

[0315] The first sending module 1303 is specifically used for:

[0316] The example code file is sent to the server corresponding to the account logged into the Jenkins client.

[0317] Optionally, the terminal device is equipped with a Jenkins client; the device further includes:

[0318] The fourth receiving module is used to receive the second input from the operation interface of the Jenkins client;

[0319] The node information acquisition module is used to acquire virtual machine server node information associated with the second input in response to the second input;

[0320] The third sending module is used to send the virtual machine server node information to the server, wherein the virtual machine server node information is used to instruct the server to compile the instance code file on the node indicated by the virtual machine server node information.

[0321] Optionally, the device further includes:

[0322] The fourth sending module is used to send notification information to a predetermined account, wherein the notification information includes the link information of the compilation result, the identification information of the instance code file, and the indication information of whether the compilation was successful.

[0323] See Figure 12 This invention also provides an FPGA instance code compilation device for use in a server, the device comprising:

[0324] The third receiving module 1401 is used to receive the example code file of the field-programmable gate array sent by the terminal device;

[0325] Compilation module 1402 is used to compile the instance code file and obtain the compilation result;

[0326] The second sending module 1403 is used to send the compilation result to the terminal device.

[0327] Optionally, the server is the server corresponding to the account logged in by the Jenkins client installed on the terminal device.

[0328] Optionally, the device further includes:

[0329] The fifth receiving module is used to receive virtual machine server node information sent by the terminal device;

[0330] When the compilation module 1402 compiles the example code file, it is specifically used for:

[0331] On the node indicated by the virtual machine server node information, the instance code file is compiled.

[0332] Optionally, when the compilation module 1402 compiles the example code file, it is specifically used for:

[0333] Invoke a pre-determined first script and execute the first script;

[0334] The first script is used to instruct the following:

[0335] A pre-determined second script is invoked and executed, wherein the second script instructs the restoration of the project file for the field-programmable gate array based on the example code file; and

[0336] When the project file is restored, a pre-determined third script is invoked and executed, wherein the third script is used to instruct the project file to be compiled.

[0337] Optionally, when the compilation module 1402 obtains the compilation result, it is specifically used for:

[0338] Obtain a quality report and generate a preset version of the bitstream file;

[0339] The quality report and the bitstream file are identified as the compilation result;

[0340] The quality report includes the compilation time and target information of the instance code file;

[0341] The target information includes at least one of the following:

[0342] The number of predetermined warnings of each level generated by the target process, wherein the target process is the various interface implementation processes included in the compilation process of the instance code file;

[0343] The compilation time of each of the target processes;

[0344] The number and utilization rate of available resources in the example code file;

[0345] Timing information in the timing report of the target process;

[0346] The power information in the power report of the target process.

[0347] Optionally, when the compilation module 1402 obtains the quality report and generates a preset version of the bitstream file, it is specifically used for:

[0348] When the example code file is compiled, a pre-determined fourth script is invoked and executed.

[0349] The fourth script is used to instruct the following:

[0350] A predetermined fifth script is invoked and executed, wherein the fifth script is used to instruct the acquisition of the compilation time of the instance code file and to write the compilation time into the quality report;

[0351] A predetermined sixth script is invoked and executed, wherein the sixth script is used to instruct the generation of the preset version of the bitstream file;

[0352] Obtain the target information and write it into the quality report.

[0353] Optionally, when the compilation module 1402 compiles the instance code file, it is specifically used for:

[0354] If an error is detected in one of the interface implementation processes included in the compilation process of the instance code file, skip at least one of the following processes:

[0355] Get the compilation time of the interface implementation process that caused the error;

[0356] Obtain the predetermined number of alarms at each level generated during the error-reporting interface implementation process;

[0357] Retrieve timing information from the timing report of the interface implementation that reported the error;

[0358] Retrieve power information from the power report of the interface implementation that reported the error.

[0359] Optionally, the method further includes:

[0360] The result upload module is used to upload the compilation results to the Artifactory repository server software platform.

[0361] It should be noted that the division of units in the embodiments of this invention is illustrative and only represents one logical functional division. In actual implementation, other division methods may be used. Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated units described above can be implemented in hardware or as software functional units.

[0362] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a processor-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0363] It should be noted that the apparatus provided in this embodiment of the invention can implement all the method steps implemented in the above method embodiment and can achieve the same technical effect. Therefore, the parts and beneficial effects that are the same as those in the method embodiment will not be described in detail here.

[0364] Embodiments of the present invention also provide a terminal device, such as Figure 13 As shown, the terminal device includes a memory 1520, a transceiver 1510, a processor 1500, and a user interface 1530.

[0365] The memory 1520 is used to store computer programs; the transceiver 1510 is used to send and receive data under the control of the processor 1500; the processor 1500 is used to read the computer program in the memory 1520 and perform the following operations:

[0366] Control user interface 1530 to receive the first input;

[0367] In response to the first input, obtain the instance code file of the field-programmable gate array (FPGA) to be compiled;

[0368] The transceiver 1510 is controlled to send the instance code file to the server.

[0369] The transceiver 1510 is controlled to receive the compilation result sent by the server, wherein the compilation result is the result of compiling the instance code file.

[0370] Optionally, the terminal device has a Jenkins client installed, and the first input is input in the operation interface of the Jenkins client; the process by which the processor 1500 obtains the instance code file includes:

[0371] Obtain the remote repository branch information associated with the first input;

[0372] Download the project source code file stored in the remote repository branch indicated by the remote repository branch information, and identify the downloaded project source code file as the example code file.

[0373] Optionally, the terminal device is equipped with a Jenkins client; the transceiver 1510 sends the instance code file to the server, including:

[0374] The transceiver 1510 sends the instance code file to the server corresponding to the account logged into the Jenkins client.

[0375] Optionally, the terminal device is equipped with a Jenkins client; the processor 1500 is further configured to:

[0376] The control user interface 1530 receives a second input from the operation interface of the Jenkins client.

[0377] In response to the second input, obtain the virtual machine server node information associated with the second input;

[0378] The transceiver 1510 is controlled to send the virtual machine server node information to the server, wherein the virtual machine server node information is used to instruct the server to compile the instance code file on the node indicated by the virtual machine server node information.

[0379] Optionally, the transceiver 1510 is further used for:

[0380] A notification message is sent to a pre-determined account, wherein the notification message includes the linking information of the compilation result, the identification information of the instance code file, and an indication of whether the compilation was successful.

[0381] Among them, Figure 13 In this context, the bus architecture can include any number of interconnected buses and bridges, specifically linking various circuits of one or more processors represented by processor 1500 and memory represented by memory 1520 together. The bus architecture can also link various other circuits such as peripheral devices, voltage regulators, and power management circuits, which are well known in the art and therefore will not be described further herein. The bus interface provides an interface. The transceiver 1510 can be multiple elements, including transmitters and receivers, providing a unit for communicating with various other devices over a transmission medium, including wireless channels, wired channels, optical fibers, etc. For different user equipment, the user interface 1530 can also be an interface capable of connecting external or internal devices, including but not limited to keypads, displays, speakers, microphones, joysticks, etc.

[0382] The processor 1500 is responsible for managing the bus architecture and general processing, while the memory 1520 can store the data used by the processor 1500 when performing operations.

[0383] Optionally, the processor 1500 can be a CPU, an ASIC (Application Specific Integrated Circuit), an FPGA (Field-Programmable Gate Array), or a CPLD (Complex Programmable Logic Device). The processor 1500 can also adopt a multi-core architecture.

[0384] The processor executes any of the methods provided in the embodiments of the present invention according to the obtained executable instructions by calling a computer program stored in memory. The processor and memory may also be physically separated.

[0385] Embodiments of the present invention also provide a server, such as Figure 14 As shown, the server includes a memory 1620, a transceiver 1610, and a processor 1600.

[0386] The memory 1620 is used to store computer programs; the transceiver 1610 is used to send and receive data under the control of the processor 1600; the processor 1600 is used to read the computer program in the memory 1620 and perform the following operations:

[0387] Example code file for controlling the transceiver 1610 to receive field-programmable gate arrays sent by the terminal device;

[0388] The example code file is compiled to obtain the compilation result;

[0389] The transceiver 1610 is controlled to send the compilation result to the terminal device.

[0390] Optionally, the server is the server corresponding to the account logged in by the Jenkins client installed on the terminal device.

[0391] Optionally, the transceiver 1610 is further configured to: receive virtual machine server node information sent by the terminal device;

[0392] When the processor 1600 compiles the instance code file, it is specifically used for:

[0393] On the node indicated by the virtual machine server node information, the instance code file is compiled.

[0394] Optionally, when the server compiles the instance code file, it specifically performs the following:

[0395] Invoke a pre-determined first script and execute the first script;

[0396] The first script is used to instruct the following:

[0397] A pre-determined second script is invoked and executed, wherein the second script instructs the restoration of the project file for the field-programmable gate array based on the example code file; and

[0398] When the project file is restored, a pre-determined third script is invoked and executed, wherein the third script is used to instruct the project file to be compiled.

[0399] Optionally, when the processor 1600 obtains the compilation results, it is specifically used for:

[0400] Obtain a quality report and generate a preset version of the bitstream file;

[0401] The quality report and the bitstream file are identified as the compilation result;

[0402] The quality report includes the compilation time and target information of the instance code file;

[0403] The target information includes at least one of the following:

[0404] The number of predetermined warnings of each level generated by the target process, wherein the target process is the various interface implementation processes included in the compilation process of the instance code file;

[0405] The compilation time of each of the target processes;

[0406] The number and utilization rate of available resources in the example code file;

[0407] Timing information in the timing report of the target process;

[0408] The power information in the power report of the target process.

[0409] Optionally, when the processor 1600 acquires the quality report and generates a preset version of the bitstream file, it is specifically used for:

[0410] When the example code file is compiled, a pre-determined fourth script is invoked and executed.

[0411] The fourth script is used to instruct the following:

[0412] A predetermined fifth script is invoked and executed, wherein the fifth script is used to instruct the acquisition of the compilation time of the instance code file and to write the compilation time into the quality report;

[0413] A predetermined sixth script is invoked and executed, wherein the sixth script is used to instruct the generation of the preset version of the bitstream file;

[0414] Obtain the target information and write it into the quality report.

[0415] Optionally, when the processor 1600 compiles the instance code file, it specifically performs the following:

[0416] If an error is detected in one of the interface implementation processes included in the compilation process of the instance code file, skip at least one of the following processes:

[0417] Get the compilation time of the interface implementation process that caused the error;

[0418] Obtain the predetermined number of alarms at each level generated during the error-reporting interface implementation process;

[0419] Retrieve timing information from the timing report of the interface implementation that reported the error;

[0420] Retrieve power information from the power report of the interface implementation that reported the error.

[0421] Optionally, the transceiver 1610 is further used for:

[0422] The compilation results are uploaded to the Artifactory platform, a repository server software.

[0423] Among them, Figure 14 In this context, the bus architecture can include any number of interconnected buses and bridges, specifically linking various circuits together, represented by one or more processors (processor 1600) and memory (memory 1620). The bus architecture can also link together various other circuits such as peripheral devices, voltage regulators, and power management circuits, which are well known in the art and therefore will not be described further herein. The bus interface provides an interface. The transceiver 1610 can be multiple elements, including transmitters and receivers, providing a unit for communicating with various other devices over transmission media, including wireless channels, wired channels, optical fibers, etc. The processor 1600 is responsible for managing the bus architecture and general processing, and the memory 1620 can store data used by the processor 1600 during operation.

[0424] The processor 1600 can be a CPU, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or a complex programmable logic device (CPLD). The processor 1600 can also adopt a multi-core architecture.

[0425] It should be noted that the apparatus provided in this embodiment of the invention can implement all the method steps implemented in the above method embodiment and can achieve the same technical effect. Therefore, the parts and beneficial effects that are the same as those in the method embodiment will not be described in detail here.

[0426] Embodiments of the present invention also provide a processor-readable storage medium storing a computer program for causing the processor to execute a method for compiling FPGA instance code.

[0427] The processor-readable storage medium can be any available medium or data storage device that the processor can access, including but not limited to magnetic memory (e.g., floppy disk, hard disk, magnetic tape, magneto-optical disk (MO)), optical memory (e.g., CD, DVD, BD, HVD), and semiconductor memory (e.g., ROM, EPROM, EEPROM, non-volatile memory (NAND FLASH), solid-state drive (SSD)).

[0428] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product implemented on one or more computer-usable storage media (including, but not limited to, disk storage and optical storage) containing computer-usable program code.

[0429] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-executable instructions. These computer-executable instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0430] These processor-executable instructions may also be stored in a processor-readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the processor-readable memory produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0431] These processors can execute instructions that can also be loaded onto a computer or other programmable data processing device, causing a series of operational steps to be performed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable device for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0432] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A method for compiling FPGA example code, applied to a terminal device, characterized in that, The method includes: Receive the first input; In response to the first input, obtain the instance code file of the field-programmable gate array (FPGA) to be compiled; Send the example code file to the server; The method further includes receiving a compilation result sent by the server, wherein the compilation result is the result of compiling the instance code file; the terminal device has a Jenkins client installed; and the method also includes: Receive the second input from the operation interface of the Jenkins client; In response to the second input, obtain the virtual machine server node information associated with the second input; Send the virtual machine server node information to the server, wherein the virtual machine server node information is used to instruct the server to compile the instance code file on the node indicated by the virtual machine server node information.

2. The FPGA example code compilation method according to claim 1, characterized in that, The terminal device is equipped with the open-source software project Jenkins client, and the first input is the input in the operation interface of the Jenkins client. The process of obtaining the instance code file includes: Obtain the remote repository branch information associated with the first input; Download the project source code file stored in the remote repository branch indicated by the remote repository branch information, and identify the downloaded project source code file as the example code file.

3. The FPGA example code compilation method according to claim 1, characterized in that, The terminal device is equipped with a Jenkins client. Sending the instance code file to the server includes: The example code file is sent to the server corresponding to the account logged into the Jenkins client.

4. The FPGA example code compilation method according to claim 1, characterized in that, After receiving the compilation result sent by the server, the method further includes: A notification message is sent to a pre-determined account, wherein the notification message includes the linking information of the compilation result, the identification information of the instance code file, and an indication of whether the compilation was successful.

5. A method for compiling FPGA example code, characterized in that, Applied to a server, the method includes: Receive the example code file of the field-programmable gate array sent by the terminal device; The example code file is compiled to obtain the compilation result; Sending the compilation result to the terminal device; before compiling the instance code file, the method further includes: Receive virtual machine server node information sent by the terminal device; The compilation of the instance code file includes: On the node indicated by the virtual machine server node information, the instance code file is compiled.

6. The FPGA example code compilation method according to claim 5, characterized in that, The server is the server corresponding to the account logged into by the Jenkins client installed on the terminal device.

7. The FPGA example code compilation method according to claim 5, characterized in that, The compilation of the instance code file includes: Invoke a pre-determined first script and execute the first script; The first script is used to instruct the following: A pre-determined second script is invoked and executed, wherein the second script instructs the restoration of the project file for the field-programmable gate array based on the example code file; and When the project file is restored, a pre-determined third script is invoked and executed, wherein the third script is used to instruct the project file to be compiled.

8. The FPGA example code compilation method according to claim 5, characterized in that, The obtained compilation results include: Obtain a quality report and generate a preset version of the bitstream file; The quality report and the bitstream file are identified as the compilation result; The quality report includes the compilation time and target information of the instance code file; The target information includes at least one of the following: The number of predetermined warnings of each level generated by the target process, wherein the target process is the various interface implementation processes included in the compilation process of the instance code file; The compilation time of each of the target processes; The number and utilization rate of available resources in the example code file; Timing information in the timing report of the target process; The power information in the power report of the target process.

9. The FPGA example code compilation method according to claim 8, characterized in that, The process of obtaining a quality report and generating a preset version of the bitstream file includes: When the example code file is compiled, a pre-determined fourth script is invoked and executed. The fourth script is used to instruct the following: A predetermined fifth script is invoked and executed, wherein the fifth script is used to instruct the acquisition of the compilation time of the instance code file and to write the compilation time into the quality report; A predetermined sixth script is invoked and executed, wherein the sixth script is used to instruct the generation of the preset version of the bitstream file; Obtain the target information and write it into the quality report.

10. The FPGA example code compilation method according to claim 8, characterized in that, The process of obtaining the compilation result also includes: If an error is detected in one of the interface implementation processes included in the compilation process of the instance code file, skip at least one of the following processes: Get the compilation time of the interface implementation process that caused the error; Obtain the predetermined number of warnings at each level generated during the error-reporting interface implementation process; Retrieve timing information from the timing report of the interface implementation that reported the error; Retrieve power information from the power report of the interface implementation that reported the error.

11. The FPGA example code compilation method according to claim 5, characterized in that, The method further includes: The compilation results are uploaded to the Artifactory platform, a repository server software.

12. A terminal device, characterized in that, Includes memory, transceiver, and processor: A memory for storing computer programs; a transceiver for sending and receiving data under the control of the processor; and a processor for reading the computer programs from the memory and performing the following operations: Receive the first input; In response to the first input, obtain the instance code file of the field-programmable gate array (FPGA) to be compiled; Control the transceiver to send the instance code file to the server; The transceiver is controlled to receive the compilation result sent by the server, wherein the compilation result is the result of compiling the instance code file; the terminal device has a Jenkins client installed; the processor is further configured to: Receive the second input from the operation interface of the Jenkins client; In response to the second input, obtain the virtual machine server node information associated with the second input; The transceiver is controlled to send the virtual machine server node information to the server, wherein the virtual machine server node information is used to instruct the server to compile the instance code file on the node indicated by the virtual machine server node information.

13. The terminal device according to claim 12, characterized in that, The terminal device has the Jenkins client, an open-source software project, installed. The first input is the input in the operation interface of the Jenkins client. The process by which the processor acquires the instance code file includes: Obtain the remote repository branch information associated with the first input; Download the project source code file stored in the remote repository branch indicated by the remote repository branch information, and identify the downloaded project source code file as the example code file.

14. The terminal device according to claim 12, characterized in that, The terminal device is equipped with a Jenkins client. The transceiver sends the instance code file to the server, including: The transceiver sends the instance code file to the server corresponding to the account logged into the Jenkins client.

15. The terminal device according to claim 12, characterized in that, The transceiver is also used for: A notification message is sent to a pre-determined account, wherein the notification message includes the linking information of the compilation result, the identification information of the instance code file, and an indication of whether the compilation was successful.

16. A server, characterized in that, Includes memory, transceiver, and processor: A memory for storing computer programs; a transceiver for sending and receiving data under the control of the processor; and a processor for reading the computer programs from the memory and performing the following operations: An example code file for controlling the transceiver to receive field-programmable gate arrays sent by the terminal device; The example code file is compiled to obtain the compilation result; The transceiver is controlled to send the compilation result to the terminal device; the transceiver is also used to: receive virtual machine server node information sent by the terminal device; When the processor compiles the instance code file, it is specifically used for: On the node indicated by the virtual machine server node information, the instance code file is compiled.

17. The server according to claim 16, characterized in that, The server is the server corresponding to the account logged into by the Jenkins client installed on the terminal device.

18. The server according to claim 16, characterized in that, When the server compiles the instance code file, it is specifically used for: Invoke a pre-determined first script and execute the first script; The first script is used to instruct the following: A pre-determined second script is invoked and executed, wherein the second script instructs the restoration of the project file for the field-programmable gate array based on the example code file; and When the project file is restored, a pre-determined third script is invoked and executed, wherein the third script is used to instruct the project file to be compiled.

19. The server according to claim 16, characterized in that, When the processor obtains the compilation results, it is specifically used for: Obtain a quality report and generate a preset version of the bitstream file; The quality report and the bitstream file are identified as the compilation result; The quality report includes the compilation time and target information of the instance code file; The target information includes at least one of the following: The number of predetermined warnings of each level generated by the target process, wherein the target process is the various interface implementation processes included in the compilation process of the instance code file; The compilation time of each of the target processes; The number and utilization rate of available resources in the example code file; Timing information in the timing report of the target process; The power information in the power report of the target process.

20. The server according to claim 19, characterized in that, When the processor acquires the quality report and generates a preset version of the bitstream file, it is specifically used for: When the example code file is compiled, a pre-determined fourth script is invoked and executed. The fourth script is used to instruct the following: A predetermined fifth script is invoked and executed, wherein the fifth script is used to instruct the acquisition of the compilation time of the instance code file and to write the compilation time into the quality report; A predetermined sixth script is invoked and executed, wherein the sixth script is used to instruct the generation of the preset version of the bitstream file; Obtain the target information and write it into the quality report.

21. The server according to claim 19, characterized in that, When the processor compiles the instance code file, it is specifically used for: If an error is detected in one of the interface implementation processes included in the compilation process of the instance code file, skip at least one of the following processes: Get the compilation time of the interface implementation process that caused the error; Obtain the predetermined number of warnings at each level generated during the error-reporting interface implementation process; Retrieve timing information from the timing report of the interface implementation that reported the error; Retrieve power information from the power report of the interface implementation that reported the error.

22. The server according to claim 16, characterized in that, The transceiver is also used for: The compilation results are uploaded to the Artifactory platform, a repository server software.

23. An FPGA example code compilation device, applied to a terminal device, characterized in that, The device includes: The first receiving module is used to receive the first input; The code file acquisition module is used to acquire the instance code file of the field-programmable gate array (FPGA) to be compiled in response to the first input; The first sending module is used to send the instance code file to the server; The second receiving module is used to receive the compilation result sent by the server, wherein the compilation result is the result of compiling the instance code file; the terminal device has a Jenkins client installed; and further includes: The fourth receiving module is used to receive the second input from the operation interface of the Jenkins client; The node information acquisition module is used to acquire virtual machine server node information associated with the second input in response to the second input; The third sending module is used to send the virtual machine server node information to the server, wherein the virtual machine server node information is used to instruct the server to compile the instance code file on the node indicated by the virtual machine server node information.

24. An FPGA instance code compilation device, applied to a server, characterized in that, The device includes: The third receiving module is used to receive the example code file of the field-programmable gate array sent by the terminal device; The compilation module is used to compile the example code file and obtain the compilation result; The second sending module is used to send the compilation result to the terminal device; the apparatus further includes: The fifth receiving module is used to receive virtual machine server node information sent by the terminal device; The compilation module is used for: On the node indicated by the virtual machine server node information, the instance code file is compiled.

25. A processor-readable storage medium, characterized in that, The processor-readable storage medium stores a computer program that causes the processor to perform the method according to any one of claims 1 to 4, or to perform the method according to any one of claims 5 to 11.

Images