Floating point operator and configuration method and device thereof, artificial intelligence chip and accelerator

Abstract

The present disclosure provides a floating point operation device, a configuration method and apparatus thereof, an artificial intelligence chip and an accelerator, and relates to the technical field of artificial intelligence. The floating point operation device is based on a data flow and comprises a data input end, N multiplexers, N floating point operation circuits, and a data output end. Each multiplexer comprises a first input end, a second input end and a first output end. The first input end of the first multiplexer is connected with the data input end. The first input end of the i-th multiplexer is connected with the first output end of the (i-1)-th multiplexer. N is greater than or equal to 2, and 2 is less than or equal to i and less than or equal to N. The first floating point operation circuit is connected between the data input end and the second input end of the first multiplexer. The i-th floating point operation circuit is connected between the first output end of the (i-1)-th multiplexer and the second input end of the i-th multiplexer. The data output end is connected with the first output end of the N-th multiplexer.

Description

Technical Field

[0001] This disclosure relates to the field of artificial intelligence technology, and in particular to a floating-point arithmetic unit and its configuration method and apparatus, an artificial intelligence chip and an accelerator. Background Technology

[0002] In recent years, artificial intelligence (AI) technology has been widely applied across various industries. However, the implementation of AI involves a large amount of computation. AI chips can be used to perform these calculations, thereby improving computational efficiency. Summary of the Invention

[0003] However, the inventors noticed that the computational efficiency was still low in this way.

[0004] The inventors discovered that when performing floating-point operations on complex floating-point data, such as whitening, color gamut conversion, and activation function processing on videos and images, the floating-point arithmetic unit in the artificial intelligence chip completes the operation based on the instruction set. That is, the next operation can only be performed after the previous one is completed, resulting in low computational efficiency.

[0005] To address the aforementioned problems, the present disclosure proposes the following solutions.

[0006] According to one aspect of the present disclosure, a floating-point arithmetic unit is provided, the floating-point arithmetic unit being based on a data stream and comprising: a data input terminal; N multiplexers, each multiplexer including a first input terminal, a second input terminal, and a first output terminal, wherein the first input terminal of the first multiplexer is connected to the data input terminal, the first input terminal of the i-th multiplexer is connected to the first output terminal of the (i-1)-th multiplexer, N≥2, 2≤i≤N; N floating-point arithmetic circuits, the first floating-point arithmetic circuit being connected between the data input terminal and the second input terminal of the first multiplexer, the i-th floating-point arithmetic circuit being connected between the first output terminal of the (i-1)-th multiplexer and the second input terminal of the i-th multiplexer; and a data output terminal connected to the first output terminal of the N-th multiplexer.

[0007] In some embodiments, the floating-point arithmetic unit further includes at least one set of multiplexers, each set of multiplexers corresponding to the j-th floating-point arithmetic circuit and the k-th multiplexer, where j is a positive integer from 1 to N-1, and k is a positive integer from j+1 to N. Each set of multiplexers includes: a first multiplexer, comprising: a second output terminal connected to the end of the j-th floating-point arithmetic circuit away from the j-th multiplexer; and a third input terminal connected to the data input terminal when j=1, and connected when 2≤j≤N-1. The first multiplexer is connected to the first output of the (j-1)th multiplexer and to the first output of the kth multiplexer; and the second multiplexer includes: a fifth input connected to the first output of the kth multiplexer, a sixth input connected to the end of the jth floating-point circuit near the jth multiplexer, and a third output connected to the first input of the (k+1)th multiplexer when j+1≤k≤N-1, and connected to the data output when k=N.

[0008] In some embodiments, the at least one set of multiplexers includes multiple sets of multiplexers, the j-th floating-point operation circuits corresponding to different sets of multiplexers are different, and the k-th multiplexer corresponding to different sets of multiplexers is different.

[0009] In some embodiments, the j-th floating-point circuit corresponding to one of the at least one set of multiplexers is configured to perform a multiplication operation.

[0010] In some embodiments, the k-th multiplexer corresponding to the set of multiplexers is the N-th multiplexer.

[0011] In some embodiments, the N floating-point arithmetic circuits include an r-th floating-point arithmetic circuit configured to perform binar arithmetic, where r ≥ 2; the floating-point arithmetic unit further includes: a data synchronization circuit connected between the r-th floating-point arithmetic circuit and the first output of the (r-1)-th multiplexer, configured to synchronize data from the first output of the (r-1)-th multiplexer and data from the first output of the t-th multiplexer to the r-th floating-point arithmetic circuit in synchronous mode, where 1 ≤ t ≤ r-1; and to allow data from the first output of the (r-1)-th multiplexer to flow to the r-th floating-point arithmetic circuit via the data synchronization circuit in asynchronous mode.

[0012] In some embodiments, different floating-point circuits are configured to perform different types of floating-point operations.

[0013] In some embodiments, the floating-point operations performed by the N floating-point circuits include inversion, comparison, logarithmic, multiplication, exponentiation, addition, and reciprocal operations.

[0014] In some embodiments, the logarithmic operation and the exponential operation are based on e.

[0015] In some embodiments, the N floating-point circuits are configured in an initial order from 1 to N to perform inversion, comparison, logarithmic, multiplication, exponentiation, addition, and reciprocal operations.

[0016] According to another aspect of the embodiments of this disclosure, a method for configuring a floating-point arithmetic unit according to any of the above embodiments is provided, comprising: determining a first set of floating-point operations to be executed, wherein the type of each floating-point operation in the first set of floating-point operations is the type of floating-point operation configured to be executed by one of the N floating-point arithmetic circuits; configuring a register at least once according to a reference order and a first execution order of the first set of floating-point operations, such that the register controls the floating-point arithmetic unit to execute the first set of floating-point operations in response to data from the data input terminal; wherein the reference order includes the execution order of the N floating-point operations executed sequentially by the N floating-point arithmetic circuits in an initial order from 1 to N, and each configuration includes configuring the N multiplexers.

[0017] In some embodiments, each floating-point arithmetic circuit is configured to output the data after floating-point arithmetic on the flowing data in arithmetic mode, and to directly output the flowing data in non-arithmetic mode; wherein, each configuration also includes configuring each floating-point arithmetic circuit to be in arithmetic mode or non-arithmetic mode.

[0018] In some embodiments, configuring the registers at least once according to a reference order and a first execution order of the first group of floating-point operations includes: splitting the first group of floating-point operations into a plurality of second groups of floating-point operations according to the first execution order when the order of the plurality of floating-point operations in the first group of floating-point operations in the first execution order is different from the order of the plurality of floating-point operations in the reference order, wherein any two floating-point operations in each second group of floating-point operations have the same order in the second execution order of the second group of floating-point operations as in the reference order; configuring the registers once for each second group of floating-point operations so that the registers control the floating-point unit to execute the plurality of second group of floating-point operations in response to data from the data input terminal.

[0019] In some embodiments, the order of at least two floating-point operations in the execution order of the third group of floating-point operations is different from the order of the at least two floating-point operations in the reference order; wherein, the third group of floating-point operations is obtained by merging any two adjacent second group of floating-point operations in the plurality of second group of floating-point operations.

[0020] In some embodiments, performing at least one configuration on the register according to the reference order and the first execution order of the first group of floating-point operations further includes performing a configuration on the register if any two floating-point operations in the first group of floating-point operations are in the same order in the first execution order as they are in the reference order.

[0021] In some embodiments, the floating-point unit further includes at least one set of multiplexers, each set of multiplexers corresponding to the j-th floating-point circuit, the k-th multiplexer, and the k-th floating-point circuit, where j is a positive integer from 1 to N-1, and k is a positive integer from j+1 to N. Each set of multiplexers includes: a first multiplexer, comprising: a second output terminal connected to the end of the j-th floating-point circuit away from the j-th multiplexer; a third input terminal connected to a data input terminal when j=1, and connected to the first output terminal of the (j-1)-th multiplexer when 2≤j≤N-1; and a fourth input terminal connected to the first output terminal of the k-th multiplexer; and a second multiplexer, comprising: a fifth input terminal connected to the first output terminal of the k-th multiplexer; a sixth input terminal connected to the first output terminal of the (j-1)-th multiplexer; and a sixth input terminal connected to the first output terminal of the k-th multiplexer. The input terminal is connected to the end of the j-th floating-point arithmetic circuit closest to the j-th multiplexer, and the third output terminal is connected to the first input terminal of the (k+1)-th multiplexer when j+1≤k≤N-1, and to the data output terminal when k=N; wherein, each configuration also includes configuring the first multiplexer and the second multiplexer in each group of multiplexers; the reference order also includes the execution order of the N floating-point arithmetic circuits performing N floating-point operations in an adjusted order different from the initial order, wherein the adjusted order is based on the initial order, adjusting the j-th floating-point arithmetic circuit corresponding to each group of multiplexers in one or more groups of multiplexers to perform the operation after the corresponding k-th floating-point arithmetic circuit.

[0022] In some embodiments, the N floating-point arithmetic circuits include an r-th floating-point arithmetic circuit configured to perform binar arithmetic, where r ≥ 2; the floating-point arithmetic unit further includes a data synchronization circuit connected between the r-th floating-point arithmetic circuit and the first output of the (r-1)-th multiplexer, configured to synchronize data from the first output of the (r-1)-th multiplexer and data from the first output of the t-th multiplexer to the r-th floating-point arithmetic circuit in synchronous mode, where 1 ≤ t ≤ r-1; and to allow data from the first output of the (r-1)-th multiplexer to flow to the r-th floating-point arithmetic circuit via the data synchronization circuit in asynchronous mode; wherein each configuration further includes configuring the data synchronization circuit to be in synchronous mode or asynchronous mode.

[0023] In some embodiments, determining the first set of floating-point operations to be performed includes: decomposing the formula to be operated on to obtain the first set of floating-point operations.

[0024] According to another aspect of the embodiments of this disclosure, a configuration apparatus for a floating-point arithmetic unit of any of the above embodiments is provided, comprising: a determining module configured to determine a first set of floating-point operations to be executed, wherein the type of each floating-point operation in the first set of floating-point operations is the type of floating-point operation configured to be executed by one of the N floating-point arithmetic circuits; and a configuration module configured to perform at least one configuration on a register according to a reference order and a first execution order of the first set of floating-point operations, such that the register controls the floating-point arithmetic unit to execute the first set of floating-point operations in response to data from the data input terminal, wherein the reference order includes the execution order of the N floating-point operations executed sequentially by the N floating-point arithmetic circuits in an initial order from 1 to N, and each configuration includes configuring the N multiplexers.

[0025] According to another aspect of the present disclosure, a configuration apparatus for a floating-point arithmetic unit of any of the above embodiments is provided, comprising: a memory; and a processor coupled to the memory, the processor being configured to execute the configuration method of the floating-point arithmetic unit of any of the above embodiments based on instructions stored in the memory.

[0026] According to another aspect of the present disclosure, an artificial intelligence chip is provided, including: a floating-point arithmetic unit of any of the above embodiments.

[0027] According to another aspect of the present disclosure, an accelerator is provided, comprising: a configuration device for a floating-point arithmetic unit of any of the above embodiments; and an artificial intelligence chip of any of the above embodiments, including the register, the register being configured to control the floating-point arithmetic unit to perform the first set of floating-point operations in response to data from the data input terminal according to the at least one configuration.

[0028] According to another aspect of the present disclosure, a computer-readable storage medium is provided, including computer program instructions, wherein the computer program instructions, when executed by a processor, implement the configuration method of the floating-point arithmetic unit of any of the above embodiments.

[0029] According to another aspect of the present disclosure, a computer program product is provided, including a computer program, wherein when the computer program is executed by a processor, it implements the configuration method of the floating-point arithmetic unit of any of the above embodiments.

[0030] In this embodiment of the disclosure, the first input terminal of each multiplexer in the floating-point arithmetic unit is connected to the data input terminal of the floating-point arithmetic unit or the output terminal of the previous multiplexer to receive data from the data input terminal or the previous multiplexer. Furthermore, a corresponding floating-point arithmetic circuit is connected between the second input terminal of each multiplexer and the data input terminal or the output terminal of the previous multiplexer to receive data processed by the corresponding floating-point arithmetic circuit. After configuring each multiplexer to output data from the first or second input terminal, the data input from the data input terminal can sequentially flow through the floating-point arithmetic circuits required for the operation, so that these floating-point arithmetic circuits perform floating-point operations on the flowing data in a data-stream manner. In the data-stream mode, these floating-point arithmetic circuits can each perform floating-point operations simultaneously. Thus, using this simple floating-point arithmetic unit, the required floating-point operations can be completed in a data-stream manner, thereby improving computational efficiency.

[0031] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a schematic diagram of the structure of a floating-point arithmetic unit according to some embodiments of the present disclosure;

[0034] Figure 2 This is a flowchart illustrating a method for configuring a floating-point arithmetic unit according to some embodiments of the present disclosure;

[0035] Figure 3 This is a schematic diagram of the structure of a floating-point arithmetic unit according to other embodiments of this disclosure;

[0036] Figure 4 This is a schematic diagram of the structure of a floating-point arithmetic unit according to some embodiments of the present disclosure;

[0037] Figure 5 This is a schematic diagram of the configuration device of a floating-point arithmetic unit according to some embodiments of the present disclosure;

[0038] Figure 6 This is a schematic diagram of the configuration apparatus of a floating-point arithmetic unit according to other embodiments of the present disclosure;

[0039] Figure 7This is a schematic diagram of the structure of an accelerator according to some embodiments of the present disclosure. Detailed Implementation

[0040] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. The descriptions of the exemplary embodiments are merely illustrative and are in no way intended to limit the present disclosure or its application or use. The present disclosure may be implemented in many different forms and is not limited to the embodiments described herein. These embodiments are provided so that the present disclosure will be thorough and complete, and will fully express the scope of the disclosure to those skilled in the art. It should be noted that, unless specifically stated otherwise, the relative arrangement of components and steps, the composition of materials, numerical expressions, and values ​​set forth in these embodiments should be interpreted as exemplary only and not as limiting.

[0041] The terms "first," "second," and similar words used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different parts. Words such as "including" or "containing" mean that the element preceding the word encompasses the element listed after the word, and do not exclude the possibility of encompassing other elements as well. Terms such as "above" and "below" are used only to indicate relative positional relationships, and these relative positional relationships may also change accordingly when the absolute position of the described object changes.

[0042] In this disclosure, when a specific component is described as being located between a first component and a second component, an intermediary component may or may not be present between the specific component and the first or second component. When a specific component is described as connecting to other components, the specific component may be directly connected to the other components without having an intermediary component, or it may not be directly connected to the other components but may have an intermediary component.

[0043] All terms used in this disclosure (including technical or scientific terms) have the same meaning as understood by one of ordinary skill in the art to which this disclosure pertains, unless otherwise specifically defined. It should also be understood that terms defined in a general dictionary, such as a dictionary, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or highly formalized meaning, unless expressly defined herein.

[0044] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0045] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0046] Figure 1This is a schematic diagram of a floating-point arithmetic unit according to some embodiments of the present disclosure. The floating-point arithmetic units provided in the embodiments of the present disclosure are all based on data streams.

[0047] like Figure 1 As shown, the floating-point arithmetic unit includes a data input terminal 100, N multiplexers 200, N floating-point arithmetic circuits 300, and a data output terminal 400. N≥2, that is, the floating-point arithmetic unit includes multiple multiplexers 200 and multiple floating-point arithmetic circuits 300.

[0048] Figure 1 An example with N=7 is shown. That is, the N multiplexers 200, connected sequentially from data input 100 to data output 400, include the first multiplexer 2001, the second multiplexer 2002, the third multiplexer 2003, the fourth multiplexer 2004, the fifth multiplexer 2005, the sixth multiplexer 2006, and the seventh multiplexer 2007.

[0049] Each multiplexer includes a first input 201, a second input 202, and a first output 203. Each multiplexer can be configured to output data from either the first input 201 or the second output 202 via the first output 203.

[0050] Specifically, the first input terminal 201 of the first multiplexer 2001 is connected to the data input terminal 100, and the first input terminal 201 of the i-th multiplexer (e.g., the second multiplexer 2002 to the seventh multiplexer 2007) is connected to the first output terminal 203 of the (i-1)-th multiplexer (e.g., the first multiplexer 2001 to the sixth multiplexer 2006), where 2≤i≤N. The first output terminal 203 of the N-th multiplexer (e.g., the seventh multiplexer 2007) is connected to the data output terminal 400.

[0051] In other words, when configured to output data from the first input terminal 201, the first multiplexer 2001 outputs data input from the data input terminal 100 to the floating-point unit, and the i-th multiplexer outputs data from the first output terminal 203 of the (i-1)-th multiplexer.

[0052] Similarly, in Figure 1 In the above, following the sequential connection order from data input terminal 100 to data output terminal 400, the N floating-point operation circuits 300 include the first floating-point operation circuit 3001, the second floating-point operation circuit 3002, the third floating-point operation circuit 3003, the fourth floating-point operation circuit 3004, the fifth floating-point operation circuit 3005, the sixth floating-point operation circuit 3006, and the seventh floating-point operation circuit 3007.

[0053] Specifically, the first floating-point operation circuit 3001 is connected between the data input terminal 100 and the second input terminal 202 of the first multiplexer 2001, and the i-th floating-point operation circuit (e.g., the second floating-point operation circuit 3002 to the seventh floating-point operation circuit 3007) is connected between the first output terminal 203 of the (i-1)-th multiplexer (e.g., the first multiplexer 2001 to the sixth multiplexer 2006) and the second input terminal 202 of the i-th multiplexer (e.g., the second multiplexer 2002 to the seventh multiplexer 2007).

[0054] Each floating-point circuit can perform floating-point operations on the data flowing through it. In some embodiments, each floating-point circuit automatically performs floating-point operations on all the data flowing through it. In other embodiments, each floating-point circuit can be configured to be in either an operation mode or a non-operation mode. In operation mode, the floating-point circuit can output the data after performing floating-point operations on the data flowing through it; in non-operation mode, the floating-point circuit can directly output the data flowing through it. That is, in non-operation mode, the floating-point circuit acts as a data path and does not perform floating-point operations on the data flowing through it.

[0055] In some embodiments, each floating-point circuit can be configured to perform a corresponding type of floating-point operation, such as multiplication, addition, etc. It should be understood that different floating-point circuits can be configured to perform the same or different types of floating-point operations.

[0056] In the above embodiment, the first input terminal 201 of each multiplexer in the floating-point arithmetic unit is connected to the data input terminal 100 of the floating-point arithmetic unit or the output terminal 203 of the previous multiplexer to receive data from the data input terminal 100 or the previous multiplexer. Furthermore, a corresponding floating-point arithmetic circuit is connected between the second input terminal 202 of each multiplexer and the data input terminal 100 or the output terminal 203 of the previous multiplexer to receive data processed by the corresponding floating-point arithmetic circuit. After configuring each multiplexer to output data from the first input terminal 201 or the second input terminal 202, the data input from the data input terminal 100 can sequentially flow through the floating-point arithmetic circuits required for the operation, allowing these circuits to perform floating-point operations on the flowing data in a data-stream manner. In this data-stream mode, these floating-point arithmetic circuits can perform floating-point operations simultaneously. Thus, this simple floating-point arithmetic unit can complete the required floating-point operations in a data-stream manner, thereby improving computational efficiency.

[0057] The following description, in conjunction with some embodiments, further illustrates the point. Figure 1The floating-point arithmetic unit shown is based on data streams.

[0058] In some embodiments, different floating-point circuits are configured to perform different types of floating-point operations. That is, with the number of N floating-point circuits 300 remaining constant, the floating-point unit can perform more types of floating-point operations. In this way, the floating-point unit can be adapted to more diverse computational needs, thereby improving its versatility.

[0059] In some embodiments, the N floating-point circuits 300 are configured to perform floating-point operations including inversion, comparison, logarithmic, multiplication, exponentiation, addition, and reciprocal operations. This improves the versatility of the floating-point unit.

[0060] In some embodiments, logarithmic and exponential operations are performed with base e. Since the demand for logarithmic and exponential operations with base e is the highest in practice, this further improves the versatility of the floating-point unit.

[0061] In some embodiments, N floating-point circuits are configured sequentially from 1 to N to perform inversion, comparison, logarithmic, multiplication, exponentiation, addition, and reciprocal operations. This further enhances the versatility of the floating-point unit.

[0062] The following is combined Figure 2 illustrate Figure 1 The configuration method for the floating-point arithmetic unit is shown. Figure 2 This is a flowchart illustrating a method for configuring a floating-point arithmetic unit according to some embodiments of the present disclosure.

[0063] like Figure 2 As shown, the configuration method of the floating-point arithmetic unit includes steps 1002 to 1004.

[0064] In step 1002, the first set of floating-point operations to be performed is determined.

[0065] Here, the type of each floating-point operation in the first group of floating-point operations is the type of floating-point operation that one of the N floating-point operation circuits 300 in the floating-point arithmetic unit is configured to perform.

[0066] As one implementation method, the formula that needs to be operated on can be broken down to obtain the first set of floating-point operations.

[0067] For example, the formula that needs to perform the calculation is: The formula can be broken down into the following four operations: y1 = Ax, y2 = e y1 y3=y2+B That is, the first group of floating-point operations includes four floating-point operations, which are arranged in the following order of execution (i.e., the first execution order): multiplication, exponentiation with base e, addition, and reciprocal.

[0068] In step 1004, the registers are configured at least once according to the reference order and the first execution order of the first set of floating-point operations, so that the registers control the floating-point unit to perform the first set of floating-point operations in response to data from the data input terminal.

[0069] Here, the reference order refers to the execution order of the N floating-point operation circuits 300 performing the N floating-point operations sequentially from an initial order of 1 to N. Taking N=3 as an example, assuming the first floating-point operation circuit 3001 is configured to perform multiplication, the second floating-point operation circuit 3002 is configured to perform addition, and the third floating-point operation circuit 3003 is configured to perform multiplication, then the initial order from 1 to N is: multiplication, addition, multiplication.

[0070] Each configuration performed on the register at least once involves configuring N multiplexers 200. The register is, for example, a control register of a floating-point arithmetic unit. After performing at least one configuration on the register, the register can send control signals to each multiplexer individually to configure each multiplexer to output data from either a first input 201 or a second input 202.

[0071] In the above embodiment, a set of floating-point operations to be performed is determined based on the types of floating-point operations that the N floating-point arithmetic circuits 300 can execute. Then, the registers are configured according to the execution order of this set of floating-point operations and the execution order of the N floating-point operations executed sequentially by the N floating-point arithmetic circuits 300 from 1 to N, so that the registers control the floating-point arithmetic unit to execute this set of floating-point operations in response to data from the data input terminal 100. In this way, the floating-point arithmetic unit can be controlled to complete the set of floating-point operations to be performed according to the actual computational requirements in a data stream manner.

[0072] Step 1004 is further illustrated below with reference to some embodiments.

[0073] In some embodiments, each floating-point arithmetic circuit can be configured to output the data after floating-point operations on the flowing data in arithmetic mode, and to directly output the flowing data in non-arithmetic mode. In these embodiments, each configuration also includes configuring each floating-point arithmetic circuit to be in arithmetic mode or non-arithmetic mode. For example, floating-point arithmetic circuits that need to perform floating-point operations can be configured to be in arithmetic mode, while floating-point arithmetic circuits that do not need to perform floating-point operations can be configured to be in non-arithmetic mode. In this way, the floating-point arithmetic circuits required for operations in the floating-point arithmetic unit can be controlled to perform floating-point operations, thereby improving the accuracy of the operations.

[0074] In some embodiments, the order of any two floating-point operations in the first group of floating-point operations determined in step 1002 in the first execution order is the same as the order of these two floating-point operations in the reference order. In these embodiments, the registers may be configured once.

[0075] Taking the first group of floating-point operations obtained from the above formula as an example, the four floating-point operations in this group, arranged in the first execution order, are: multiplication, exponentiation to base e, addition, and reciprocal. Assuming N = 5, and the N floating-point circuits 300 execute multiplication, inversion, exponentiation to base e, addition, and reciprocal in the initial order from 1 to N, then the order of any two floating-point operations in the first execution order is the same as their order in the reference order.

[0076] In this configuration, the registers can be configured to control the five multiplexers 200 and the five floating-point circuits 300 as follows: The first multiplexer 2001 and the third through fifth multiplexers 2005 output data from the second input terminal 202; the second multiplexer 2002 outputs data from the first input terminal 201; the first and fifth floating-point circuits 3001 and 3003 through 3005 are in operation mode; and the second floating-point circuit 3002 is in non-operation mode. After configuration, the floating-point unit can perform the first set of floating-point operations in response to data from the data input terminal 100.

[0077] In the above embodiments, if the order of any two floating-point operations in the first group of floating-point operations in the first execution order is the same as the order of these two floating-point operations in the reference order, a configuration is performed on the register once. Thus, after one configuration, data can complete the first group of floating-point operations in a single flow through the floating-point unit, thereby further improving computational efficiency.

[0078] In other embodiments, the order of the multiple floating-point operations in the first group of floating-point operations determined in step 1002 in the first execution order is different from the order of these multiple floating-point operations in the reference order. That is, there are at least two floating-point operations in the first group of floating-point operations whose order in the first execution order is different from their order in the reference order.

[0079] In these embodiments, the first group of floating-point operations can first be split into multiple second groups of floating-point operations according to a first execution order. Here, the order of any two floating-point operations in each second group of floating-point operations is the same as the order of these two floating-point operations in the reference order. Then, for each second group of floating-point operations, the registers are configured once, so that the registers control the floating-point unit to perform multiple second group floating-point operations in response to data from the data input terminal 100.

[0080] Let's continue with the first group of floating-point operations from the example above. The first group of floating-point operations, arranged in the first execution order, consists of: multiplication, exponentiation to base e, addition, and reciprocal. Assuming N = 4, and the N floating-point circuits 300 execute addition, reciprocal, multiplication, and exponentiation to base e in the initial order from 1 to N, then the order of these floating-point operations in the first execution order is different from their order in the reference order. In this case, the first group of floating-point operations can be split into two second groups of floating-point operations according to the first execution order: multiplication and exponentiation to base e; addition and reciprocal.

[0081] For the second set of floating-point operations, including multiplication and exponentiation to base e, a register can be configured to control the four multiplexers 200 and the four floating-point arithmetic circuits 300 as follows: The first multiplexer 2001 and the second multiplexer 2002 output data from the first input terminal 201; the third multiplexer 2003 and the fourth multiplexer 2004 output data from the second input terminal 202; the first floating-point arithmetic circuit 3001 and the second floating-point arithmetic circuit 3002 are in non-operation mode; and the third floating-point arithmetic circuit 3003 and the fourth floating-point arithmetic circuit 3004 are in operation mode. Then, the data input terminal 100 receives data, causing the floating-point arithmetic unit to complete y1 = Ax and y2 = e in response to the data from the data input terminal 100. y1 These two floating-point operations output intermediate results.

[0082] For the second set of floating-point operations, including addition and reciprocal operations, the registers can be configured again to control the four multiplexers 200 and the four floating-point arithmetic circuits 300 as follows: The first multiplexer 2001 and the second multiplexer 2002 output data from the second input terminal 202; the third multiplexer 2003 and the fourth multiplexer 2004 output data from the first input terminal 201; the first floating-point arithmetic circuit 3001 and the second floating-point arithmetic circuit 3002 are in arithmetic mode; and the third floating-point arithmetic circuit 3003 and the fourth floating-point arithmetic circuit 3004 are in non-arithmic mode. Afterwards, the data input terminal 100 receives the intermediate results, allowing the floating-point arithmetic unit to complete y3 = y2 + B in response to the data from the data input terminal 100. These two floating-point operations complete the first set of floating-point operations.

[0083] In the above embodiments, if the order of multiple floating-point operations in the first group of floating-point operations in the first execution order is different from the order of these multiple floating-point operations in the reference order, the first group of floating-point operations is split into multiple second groups of floating-point operations, and the registers are configured once for each second group of floating-point operations. Thus, even if the execution order of each floating-point operation in the first group of floating-point operations is different from the execution order of the N floating-point operation circuits 300, the required first group of floating-point operations can still be completed after the data flows through the floating-point arithmetic unit multiple times by configuring the registers multiple times.

[0084] In some embodiments, the execution order of at least two floating-point operations in the third set of floating-point operations is different from their order in the reference order. The third set of floating-point operations is obtained by merging any two adjacent second-set floating-point operations from multiple second-set floating-point operations. Thus, after multiple configurations, data can complete the required first set of floating-point operations with the fewest possible passes through the floating-point unit, thereby further improving computational efficiency.

[0085] Figure 3 This is a schematic diagram of the structure of a floating-point arithmetic unit according to other embodiments of the present disclosure.

[0086] like Figure 3 As shown, in addition to the data input terminal 100, N multiplexers 200, N floating-point arithmetic circuits 300, and data output terminal 400, the floating-point arithmetic unit also includes at least one set of multiplexers 500. Figure 3 (A set is shown schematically in the image).

[0087] Each group of multiplexers 500 corresponds to the j-th floating-point arithmetic circuit, the k-th multiplexer, and the k-th floating-point arithmetic circuit. Here, j is a positive integer from 1 to N-1, and k is a positive integer from j+1 to N. Each group of multiplexers 500 includes a first multiplexer 510 and a second multiplexer 520. The first multiplexer 510 includes a third input terminal 511, a fourth input terminal 512, and a second output terminal 513, and the second multiplexer 520 includes a fifth input terminal 521, a sixth input terminal 522, and a third output terminal 523.

[0088] The second output terminal 513 of the first multiplexer 510 is connected to the end of the corresponding j-th floating-point arithmetic circuit that is furthest from the j-th multiplexer. The j-th floating-point arithmetic circuit can be one of the first floating-point arithmetic circuit 3001 to the sixth floating-point arithmetic circuit 3006, for example... Figure 3 The fourth floating-point arithmetic circuit 3004 is shown; the j-th multiplexer can be one of the first multiplexer 2001 to the sixth multiplexer 2006, for example... Figure 3 The fourth multiplexer, 2004, is shown.

[0089] The third input terminal 511 of the first multiplexer 510 is connected to the data input terminal 100 when j=1, and is connected to the first output terminal 203 of the (j-1)th multiplexer when 2≤j≤N-1. Figure 3 The case where j=4 is shown, that is, the third input terminal 511 is connected to the first output terminal 203 of the third multiplexer 2003.

[0090] The fourth input terminal 512 of the first multiplexer 510 is connected to the first output terminal 203 of the corresponding k-th multiplexer. Figure 3 Taking the j-th floating-point circuit shown as the 4th floating-point circuit 3004 as an example, the k-th multiplexer can be one of the 5th multiplexer 2005 to the 7th multiplexer 2007, for example... Figure 3 The 7th multiplexer 2007 is shown.

[0091] The fifth input terminal 521 of the second multiplexer 520 is connected to the first output terminal 203 of the corresponding k-th multiplexer. The sixth input terminal 522 of the second multiplexer 520 is connected to the end of the corresponding j-th floating-point circuit closest to the j-th multiplexer. The third output terminal 523 of the second multiplexer 520 is connected to the first input terminal 201 of the (k+1)-th multiplexer when j+1≤k≤N-1, and connected to the data output terminal 400 when k=N. That is, when k=N, the first output terminal 203 of the N-th multiplexer 2007 is connected to the data output terminal 400 via the second multiplexer 520.

[0092] and Figure 1 Similarly, for each multiplexer shown, the first multiplexer 510 can be configured to output data from the third input 511 or the fourth input 512, and the second multiplexer 520 can be configured to output data from the fifth input 521 or the sixth input 522. By configuring the first multiplexer 510 and the second multiplexer 520, the j-th floating-point operation circuit can be adjusted to perform operations after the k-th floating-point operation circuit.

[0093] For example, the first multiplexer 510 is configured to output data from the third input terminal 511, and the second multiplexer 520 is configured to output data from the fifth input terminal 521. In this case, the N floating-point arithmetic circuits 300 can perform N floating-point operations in an initial order from 1 to N.

[0094] For example, the first multiplexer 510 is configured to output data from the fourth input terminal 512, and the second multiplexer 520 is configured to output data from the sixth input terminal 522. In this case, the N floating-point operation circuits 300 can perform N floating-point operations in an execution order that adjusts the j-th floating-point operation circuit to perform operations after the k-th floating-point operation circuit, based on the initial order.

[0095] In the above embodiments, the floating-point arithmetic unit further includes at least one set of multiplexers 500, thereby enabling the N floating-point arithmetic circuits 300 to perform N floating-point operations in at least two execution orders. In this way, without adding additional floating-point arithmetic circuits, the probability of completing the first set of floating-point operations with data flowing through the floating-point arithmetic unit in a single pass is increased, thereby further improving computational efficiency.

[0096] The following description, in conjunction with some embodiments, further illustrates the point. Figure 3 The floating-point arithmetic unit shown.

[0097] In some embodiments, the floating-point arithmetic unit includes multiple sets of multiplexers 500. Here, the j-th floating-point arithmetic circuits corresponding to different sets of multiplexers 500 are different, and the k-th multiplexer corresponding to different sets of multiplexers 500 is also different. Thus, the N floating-point arithmetic circuits 300 in the floating-point arithmetic unit can perform N floating-point operations in more execution orders, thereby further increasing the probability that the first set of floating-point operations can be completed in a single pass through the floating-point arithmetic unit without adding additional floating-point arithmetic circuits, and further improving computational efficiency.

[0098] In some embodiments, the j-th floating-point circuit corresponding to at least one set of multiplexers 500 is configured to perform a multiplication operation. In these embodiments, the execution order of the multiplication operation differs among the different execution orders of the N floating-point operations that can be performed by the N floating-point circuits 300. Since multiplication is a high-frequency operation used in the implementation of artificial intelligence technology, by adjusting the execution order of the multiplication operation, the probability that the first set of floating-point operations can be completed in a single pass through the floating-point unit without adding additional floating-point circuits can be further increased. This further improves computational efficiency.

[0099] In some embodiments, the j-th floating-point circuit is configured to perform multiplication operations, and the k-th multiplexer of a set of multiplexers 500 is the N-th multiplexer. In these embodiments, the multiplication operation in the N floating-point operations performed by the N floating-point circuits 300 can be performed either at the last bit or at other positions. Since multiplication operations are usually required to be performed at the last bit or other positions in the entire operation during the implementation of artificial intelligence technology, this further increases the possibility that the first set of floating-point operations can be completed in one pass through the floating-point arithmetic unit without adding additional floating-point circuits, thereby further improving the computational efficiency.

[0100] Below Figure 2 Based on the configuration method of the floating-point arithmetic unit shown, further explanation is provided. Figure 3 The configuration method for the floating-point arithmetic unit is shown.

[0101] for Figure 3 The floating-point arithmetic unit shown, in step 1004 of its configuration method, each configuration of the registers also includes configuring the first multiplexer 510 and the second multiplexer 520 in each group of multiplexers 500.

[0102] In addition, the reference order includes not only the execution order of N floating-point operations executed sequentially according to the initial order from 1 to N, but also the execution order of N floating-point operations executed sequentially by N floating-point circuits according to an adjustment order different from the initial order.

[0103] Here, the adjustment order is based on the initial order, adjusting the j-th floating-point operation circuit corresponding to one or more groups of multiplexers 500 in the group to perform the operation after the k-th floating-point operation circuit corresponding to that group of multiplexers 500.

[0104] For example, N=7, the seven floating-point arithmetic circuits 300 are configured sequentially from 1 to N to perform inversion, comparison, logarithmic, multiplication, exponentiation, addition, and reciprocal operations. The floating-point unit includes two sets of multiplexers 500. The first set of multiplexers 500 corresponds to j=1, k=3; the second set of multiplexers 500 (see...) Figure 3 The corresponding values ​​are j=4 and k=7.

[0105] In this case, the reference sequence includes the execution order of N floating-point operations performed by the 7 floating-point circuits 300 in an initial order from 1 to 7, namely, inverse operation, comparison operation, logarithmic operation, multiplication operation, exponentiation operation, addition operation, and reciprocal operation.

[0106] In addition, the reference order includes three adjustment orders. The first adjustment order is to adjust the execution order of the first floating-point operation circuit 3001 in the first group of multiplexers 500 so that it performs operations after the third floating-point operation circuit 3003, that is, comparison operation, logarithmic operation, inverse operation, multiplication operation, exponentiation operation, addition operation, and reciprocal operation. The second adjustment order is to adjust the execution order of the fourth floating-point operation circuit 3004 in the second group of multiplexers 500 so that it performs operations after the seventh floating-point operation circuit 3007, that is, inverse operation, comparison operation, logarithmic operation, exponentiation operation, addition operation, reciprocal operation, and multiplication operation. The third adjustment order is to adjust the execution order of the first floating-point operation circuit 3001 in the first group of multiplexers 500 to perform operations after the third floating-point operation circuit 3003, and to adjust the fourth floating-point operation circuit 3004 in the second group of multiplexers 500 to perform operations after the seventh floating-point operation circuit 3007. That is, the comparison operation, logarithmic operation, inverse operation, exponentiation operation, addition operation, reciprocal operation, and multiplication operation.

[0107] In the above embodiments, the execution order of the N floating-point operations performed by the N floating-point arithmetic circuits 300 can be adjusted by configuring the first multiplexer 510 and the second multiplexer 520 in each group of multiplexers 500. Thus, after at least one configuration, data can complete the first group of floating-point operations determined in step 1002 with fewer passes through the floating-point arithmetic unit, thereby further improving computational efficiency.

[0108] Figure 4 This is a schematic diagram of the structure of a floating-point arithmetic unit according to some embodiments of the present disclosure.

[0109] In some embodiments, the N floating-point arithmetic circuits 300 include an r-th floating-point arithmetic circuit configured to perform binary arithmetic, where r ≥ 2. Binary arithmetic includes, but is not limited to, comparison operations, addition operations, multiplication operations, etc.

[0110] In these embodiments, such as Figure 4 As shown, in addition to the data input terminal 100, N multiplexers 200, N floating-point arithmetic circuits 300, and data output terminal 400, the floating-point arithmetic unit also includes a data synchronization circuit 600. The data synchronization circuit 600 is connected between the r-th floating-point arithmetic circuit and the first output terminal 203 of the (r-1)-th multiplexer. Figure 4 The diagram schematically shows that the second floating-point arithmetic circuit 3002, the fourth floating-point arithmetic circuit 3004, and the sixth floating-point arithmetic circuit 3006 are floating-point arithmetic circuits configured to perform binary arithmetic, i.e., r = 2, 4, and 6.

[0111] It should be understood that, although Figure 4 A first multiplexer 510 and a second multiplexer 520 are also shown, but this is not necessary. It should also be understood that if the r-th floating-point circuit is the j-th floating-point circuit corresponding to a certain group of multiplexers 500, then, see [reference needed]. Figure 4 The data synchronization circuit 600 is connected between the second output terminal 513 of the first multiplexer 510 in the group of multiplexers 500 and the corresponding j-th floating-point operation circuit (i.e., the r-th floating-point operation circuit).

[0112] The data synchronization circuit 600 is configured to synchronize data from the first output terminal 203 of the (r-1)th multiplexer and data from the first output terminal 203 of the t-th multiplexer to the r-th floating-point circuit in synchronous mode, where 1 ≤ t ≤ r-1. In asynchronous mode, it allows data from the first output terminal 203 of the (r-1)th multiplexer to flow to the r-th floating-point circuit via the data synchronization circuit 600. That is, in synchronous mode, the data synchronization circuit 600 performs a synchronization operation; in asynchronous mode, the data synchronization circuit 600 acts as a data path.

[0113] In the above embodiments, the floating-point arithmetic unit further includes a data synchronization circuit 600 connected between the r-th floating-point arithmetic circuit configured to perform binarization and the first output terminal 203 of the (r-1)-th multiplexer, to synchronize data from the first output terminal 203 of the (r-1)-th multiplexer and data from the first output terminal 203 of the t-th multiplexer to the r-th floating-point arithmetic circuit. Thus, the r-th floating-point arithmetic circuit can accurately perform binarization on these two sets of data.

[0114] In some embodiments, see Figure 4 The r-th floating-point operation circuit is also connected to the data input terminal 700 of the floating-point unit, which is configured to receive constant data. The r-th floating-point operation circuit can also be configured to perform binarization on data from the data synchronization circuit 600 in asynchronous mode and constant data from the data input terminal 700.

[0115] In some embodiments, a floating-point arithmetic circuit configured to perform addition (e.g., Figure 4 The sixth floating-point arithmetic circuit 3006 shown also relates to a floating-point arithmetic circuit configured to perform reciprocal operations (e.g., Figure 4 The seventh floating-point arithmetic circuit (3007) shown is connected. The floating-point arithmetic circuit configured to perform addition operations can also be configured to send the number of additions to the floating-point arithmetic circuit configured to perform reciprocal operations, so that the floating-point arithmetic circuit configured to perform reciprocal operations can calculate the average based on the number of additions performed.

[0116] Below Figure 2 Based on the configuration method of the floating-point arithmetic unit shown, further explanation is provided. Figure 4 The configuration method for the floating-point arithmetic unit is shown.

[0117] for Figure 4 The floating-point arithmetic unit shown includes a configuration step 1004 in which each configuration of the registers is performed, which further includes configuring the data synchronization circuit 600 to be in synchronous or asynchronous mode. In this way, the r-th floating-point arithmetic circuit can accurately perform binary operations.

[0118] Figure 5 This is a schematic diagram of the configuration device of a floating-point arithmetic unit according to some embodiments of the present disclosure.

[0119] like Figure 5 As shown, the configuration device 500 for the floating-point arithmetic unit includes a determination module 501 and a configuration module 502.

[0120] The determination module 501 is configured to determine the first set of floating-point operations to be performed. Here, the type of each floating-point operation in the first set of floating-point operations is the type of floating-point operation that one of the N floating-point operation circuits 300 is configured to perform.

[0121] The configuration module 502 is configured to perform at least one configuration on the registers according to a reference order and a first execution order of the first set of floating-point operations, such that the registers control the floating-point unit to perform the first set of floating-point operations in response to data from the data input terminal 100. Here, the reference order includes the execution order of the N floating-point operations performed sequentially by the N floating-point circuits in an initial order from 1 to N, and each configuration includes configuring the N multiplexers 200.

[0122] It should be understood that the configuration device 500 for the floating-point arithmetic unit may also include various other modules to execute the configuration method of the floating-point arithmetic unit of any of the above embodiments.

[0123] Figure 6 This is a schematic diagram of the configuration apparatus of a floating-point arithmetic unit according to other embodiments of the present disclosure.

[0124] like Figure 6 As shown, the configuration device 600 for the floating-point arithmetic unit includes a memory 601 and a processor 602 coupled to the memory 601. The processor 602 is configured to execute the configuration method of the floating-point arithmetic unit of any of the above embodiments based on the instructions stored in the memory 601.

[0125] The memory 601 may include, for example, system memory, fixed non-volatile storage media, etc. The system memory may store, for example, an operating system, application programs, a boot loader, and other programs.

[0126] The configuration device 600 may also include an input / output interface 603, a network interface 604, and a storage interface 605. These interfaces 603, 604, and 605, as well as the memory 601 and processor 602, can be connected, for example, via a bus 606. The input / output interface 603 provides a connection interface for input / output devices such as a monitor, mouse, keyboard, and touchscreen. The network interface 604 provides a connection interface for various networked devices. The storage interface 605 provides a connection interface for external storage devices such as SD cards and USB flash drives.

[0127] This disclosure also provides an artificial intelligence chip, including the floating-point arithmetic unit of any of the above embodiments.

[0128] Figure 7 This is a schematic diagram of the structure of an accelerator according to some embodiments of the present disclosure.

[0129] like Figure 7 As shown, the accelerator includes a configuration device for the floating-point arithmetic unit of any of the above embodiments (e.g., configuration device 500 / 600) and an artificial intelligence chip of any of the above embodiments (e.g., Figure 7 The AI ​​chip shown is 700.

[0130] The artificial intelligence chip 700 includes a floating-point unit 701 and a register 702, as described in any of the above embodiments. The register 702 is configured to control the floating-point unit 701 to perform a first set of floating-point operations in response to data from the data input terminal 100, according to at least one configuration.

[0131] This disclosure also provides a computer-readable storage medium including computer program instructions that, when executed by a processor, implement the configuration method of the floating-point arithmetic unit of any of the above embodiments.

[0132] This disclosure also provides a computer program product, including a computer program that, when executed by a processor, implements the configuration method of the floating-point arithmetic unit of any of the above embodiments.

[0133] The embodiments of this disclosure have now been described in detail. To avoid obscuring the concept of this disclosure, some details known in the art have not been described. Those skilled in the art can fully understand how to implement the technical solutions disclosed herein based on the above description.

[0134] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the embodiments of configuration methods, apparatus, artificial intelligence chips, and accelerators, since they basically correspond to the embodiments of floating-point arithmetic units, the descriptions are relatively simple; relevant parts can be referred to the descriptions of the floating-point arithmetic unit embodiments.

[0135] Those skilled in the art will understand that embodiments of this disclosure can be provided as methods, systems, or computer program products. Therefore, this disclosure can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this disclosure can take the form of a computer program product embodied on one or more computer-usable non-transitory storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0136] This disclosure is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that the functions specified in one or more flowchart illustrations and / or one or more blocks in a block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate functions for implementing the functions in the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0137] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0138] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0139] While specific embodiments of this disclosure have been described in detail by way of examples, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of this disclosure. Those skilled in the art should understand that modifications can be made to the above embodiments or equivalent substitutions can be made to some technical features without departing from the scope and spirit of this disclosure. The scope of this disclosure is defined by the appended claims.

Claims

1. A floating-point arithmetic unit, said floating-point arithmetic unit being based on a data stream, and comprising: Data input terminal; There are N multiplexers, each multiplexer including a first input terminal, a second input terminal and a first output terminal. The first input terminal of the first multiplexer is connected to the data input terminal, the first input terminal of the i-th multiplexer is connected to the first output terminal of the (i-1)-th multiplexer, N≥2, 2≤i≤N; There are N floating-point operation circuits. The first floating-point operation circuit is connected between the data input terminal and the second input terminal of the first multiplexer. The i-th floating-point operation circuit is connected between the first output terminal of the (i-1)-th multiplexer and the second input terminal of the i-th multiplexer. The data output terminal is connected to the first output terminal of the Nth multiplexer; and At least one set of multiplexers, each set of multiplexers corresponds to the j-th floating-point circuit and the k-th multiplexer, where j is a positive integer from 1 to N-1, and k is a positive integer from j+1 to N. Each set of multiplexers includes: The first multiplexer includes: The second output terminal is connected to the end of the j-th floating-point arithmetic circuit that is furthest from the j-th multiplexer. The third input terminal is connected to the data input terminal when j=1, and to the first output terminal of the (j-1)th multiplexer when 2≤j≤N-1. The fourth input terminal is connected to the first output terminal of the k-th multiplexer; and The second multiplexer includes: The fifth input terminal is connected to the first output terminal of the kth multiplexer. The sixth input terminal is connected to the end of the j-th floating-point arithmetic circuit closest to the j-th multiplexer, and... The third output terminal is connected to the first input terminal of the (k+1)th multiplexer when j+1≤k≤N-1, and connected to the data output terminal when k=N.

2. The floating-point arithmetic unit according to claim 1, wherein, The at least one set of multiplexers includes multiple sets of multiplexers, the j-th floating-point operation circuits corresponding to different sets of multiplexers are different, and the k-th multiplexer corresponding to different sets of multiplexers is different.

3. The floating-point arithmetic unit according to claim 1, wherein, The j-th floating-point circuit corresponding to one of the at least one set of multiplexers is configured to perform multiplication.

4. The floating-point arithmetic unit according to claim 3, wherein, The k-th multiplexer in the set of multiplexers is the N-th multiplexer.

5. The floating-point arithmetic unit according to claim 1, wherein, The N floating-point arithmetic circuits include the r-th floating-point arithmetic circuit configured to perform binary arithmetic, where r ≥ 2; The floating-point arithmetic unit also includes: A data synchronization circuit, connected between the r-th floating-point arithmetic circuit and the first output of the (r-1)-th multiplexer, is configured to synchronize data from the first output of the (r-1)-th multiplexer and data from the first output of the t-th multiplexer to the r-th floating-point arithmetic circuit in synchronous mode, where 1 ≤ t ≤ r-1; and to allow data from the first output of the (r-1)-th multiplexer to flow to the r-th floating-point arithmetic circuit via the data synchronization circuit in asynchronous mode.

6. The floating-point arithmetic unit according to any one of claims 1-5, wherein, Different floating-point circuits are configured to perform different types of floating-point operations.

7. The floating-point arithmetic unit according to any one of claims 1-5, wherein, The floating-point operations that the N floating-point circuits are configured to perform include inversion, comparison, logarithmic, multiplication, exponentiation, addition, and reciprocal operations.

8. The floating-point arithmetic unit according to claim 7, wherein, The logarithmic and exponential operations are based on e.

9. The floating-point arithmetic unit according to claim 7, wherein, The N floating-point arithmetic circuits are configured in an initial order from 1 to N to perform inversion, comparison, logarithmic, multiplication, exponentiation, addition, and reciprocal operations.

10. A method for configuring a floating-point arithmetic unit according to any one of claims 1-9, comprising: The first set of floating-point operations to be performed is determined, wherein the type of each floating-point operation in the first set of floating-point operations is the type of floating-point operation that one of the N floating-point operation circuits is configured to perform; According to the reference order and the first execution order of the first group of floating-point operations, the register is configured at least once such that the register controls the floating-point unit to perform the first group of floating-point operations in response to data from the data input terminal; The reference order includes the execution order of the N floating-point operations performed by the N floating-point circuits in an initial order from 1 to N, and each configuration includes configuring the N multiplexers.

11. The method according to claim 10, wherein, Each floating-point arithmetic circuit is configured to output the data after floating-point arithmetic on the flowing data in arithmetic mode, and to directly output the flowing data in non-arithmetic mode. Each configuration also includes configuring each floating-point arithmetic circuit to be in arithmetic mode or non-arithmetic mode.

12. The method according to claim 10, wherein, According to the reference order and the first execution order of the first group of floating-point operations, performing at least one configuration of the registers includes: If the order of multiple floating-point operations in the first group of floating-point operations in the first execution order is different from the order of the multiple floating-point operations in the reference order, the first group of floating-point operations is split into multiple second groups of floating-point operations according to the first execution order. In each second group of floating-point operations, the order of any two floating-point operations in the second execution order of the second group of floating-point operations is the same as the order in the reference order. For each second set of floating-point operations, the registers are configured once, such that the registers control the floating-point unit to perform the plurality of second set of floating-point operations in response to data from the data input terminal.

13. The method according to claim 12, wherein, In the third group of floating-point operations, the order of at least two floating-point operations in the execution order of the third group of floating-point operations is different from the order of the at least two floating-point operations in the reference order; The third set of floating-point operations is obtained by merging any two adjacent second set of floating-point operations from the plurality of second set of floating-point operations.

14. The method according to claim 12, wherein, Performing at least one configuration of the registers according to the reference order and the first execution order of the first group of floating-point operations further includes: If any two floating-point operations in the first group of floating-point operations are in the same order in the first execution order as in the reference order, the register is configured once.

15. The method according to any one of claims 10-14, wherein, Each configuration also includes configuring the first and second multiplexers in each group of multiplexers; The reference order also includes the execution order of the N floating-point operations performed by the N floating-point circuits in an adjusted order different from the initial order. The adjusted order is based on the initial order, whereby the j-th floating-point circuit corresponding to each of the at least one set of multiplexers is adjusted to perform the operation after the corresponding k-th floating-point circuit.

16. The method of claim 10, wherein, The N floating-point arithmetic circuits include the r-th floating-point arithmetic circuit configured to perform binary arithmetic, where r ≥ 2; The floating-point arithmetic unit further includes a data synchronization circuit connected between the r-th floating-point arithmetic circuit and the first output terminal of the (r-1)-th multiplexer, configured to synchronize data from the first output terminal of the (r-1)-th multiplexer and data from the first output terminal of the t-th multiplexer to the r-th floating-point arithmetic circuit in synchronous mode, 1≤t≤r-1; and to allow data from the first output terminal of the (r-1)-th multiplexer to flow to the r-th floating-point arithmetic circuit via the data synchronization circuit in asynchronous mode. Each configuration also includes configuring the data synchronization circuit to be in synchronous or asynchronous mode.

17. The method according to claim 10, wherein, The first set of floating-point operations to be performed includes: The formulas that need to be operated on are broken down to obtain the first set of floating-point operations.

18. A configuration device for a floating-point arithmetic unit according to any one of claims 1-9, comprising: The determination module is configured to determine the first set of floating-point operations to be performed, wherein the type of each floating-point operation in the first set of floating-point operations is the type of floating-point operation that one of the N floating-point operation circuits is configured to perform; The configuration module is configured to perform at least one configuration on the registers according to a reference order and a first execution order of the first group of floating-point operations, such that the registers control the floating-point unit to perform the first group of floating-point operations in response to data from the data input terminal, wherein the reference order includes the execution order of the N floating-point operations performed sequentially by the N floating-point circuits in an initial order from 1 to N, and each configuration includes configuring the N multiplexers.

19. A configuration device for a floating-point arithmetic unit according to any one of claims 1-9, comprising: Memory; as well as A processor coupled to the memory is configured to execute the configuration method of the floating-point arithmetic unit according to any one of claims 10-17 based on instructions stored in the memory.

20. An artificial intelligence chip, comprising: The floating-point arithmetic unit according to any one of claims 1-9.

21. An accelerator, comprising: Configuration apparatus for the floating-point arithmetic unit as described in claim 18 or 19; as well as The artificial intelligence chip of claim 20 includes the register, the register being configured to control the floating-point unit to perform the first set of floating-point operations in response to data from the data input terminal, according to the at least one configuration.

22. A computer-readable storage medium comprising computer program instructions, wherein, When the computer program instructions are executed by the processor, they implement the configuration method of the floating-point arithmetic unit according to any one of claims 10-17.

23. A computer program product comprising a computer program, wherein, When the computer program is executed by the processor, it implements the configuration method of the floating-point arithmetic unit according to any one of claims 10-17.

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