A charge balance based silicon carbide floating junction JBS design method
By adopting the JBS design method for silicon carbide floating junctions based on charge balance theory, the problem of reliance on human factors in traditional design is solved, and efficient device parameter determination and simulation result optimization are achieved, thereby improving design efficiency and cycle time.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- XIDIAN UNIV
- Filing Date
- 2023-04-27
- Publication Date
- 2026-07-31
AI Technical Summary
The design of existing silicon carbide floating junction JBS devices relies on the designer's theoretical level and knowledge accumulation. The TCAD software has the problem of non-convergence in modeling and simulation, resulting in low design efficiency.
Based on charge balance theory, six electric field distribution types of silicon carbide floating junction JBS are established, and a reverse blocking analysis model is built. The blocking voltage performance of the device is quickly predicted by the model, and the optimal simulation result is selected in one go by TCAD software.
It greatly reduces the reliance on the designer's theoretical level and knowledge accumulation, improves design efficiency, shortens the design cycle, bypasses the modeling and simulation non-convergence problem in TCAD simulation verification, and realizes the rapid determination of device design parameters.
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Figure CN116611384B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor power device technology, specifically relating to a silicon carbide floating junction JBS design method based on charge balance. Background Technology
[0002] In recent years, energy conservation, emission reduction, and low-carbon development have become the mainstream development model. Power semiconductor devices are a crucial link in the energy generation-storage-distribution cycle. Improving the performance of semiconductor power devices has become a feasible method to enhance energy conversion efficiency. Among them, silicon carbide power semiconductor devices, due to their high-voltage blocking capability, high-frequency switching characteristics, and high-temperature operation, are expected to become the next generation of mainstream high-power devices and have gained widespread favor from semiconductor manufacturers and researchers.
[0003] Commercial silicon carbide (SiC) devices are already available, making them an ideal alternative to silicon power devices. However, due to the properties of SiC, some mature silicon power devices cannot be commercially manufactured using SiC. Among these, the SiC floating junction JBS (Junction Barrier Controlled Schottky Diode), as a power device that can break the one-dimensional limitations of SiC, has attracted widespread interest from researchers in the industry.
[0004] In the traditional design of silicon carbide floating junction diode devices, designers typically rely on years of accumulated experience to define parameter ranges that meet design specifications. These parameters are then adjusted using simulation results from TCAD software, and the final design parameters that meet the specifications are obtained through multiple rounds of simulation and modification. This method heavily depends on the designer's theoretical knowledge and experience. Furthermore, TCAD software suffers from problems such as modeling, mesh setup, and simulation non-convergence, making it very time-consuming and impacting design efficiency. Summary of the Invention
[0005] To address the aforementioned problems in the prior art, this invention provides a charge-balance-based silicon carbide floating junction (JBS) design method. The technical problem to be solved by this invention is achieved through the following technical solution:
[0006] This invention provides a charge balance-based silicon carbide floating junction (JBS) design method, comprising:
[0007] S1: Based on the charge balance theory, six electric field distribution types of the silicon carbide floating junction JBS to be designed are obtained. The six electric field distribution types are non-depletion non-punch-through electric field distribution, non-depletion punch-through electric field distribution, surface breakdown non-punch-through electric field distribution, surface breakdown punch-through electric field distribution, internal breakdown non-punch-through electric field distribution, and internal breakdown punch-through electric field distribution.
[0008] S2: Establish reverse blocking analysis models corresponding to different electric field distribution types using the six types of electric field distribution;
[0009] S3: Use the reverse blocking analysis model to obtain the optimal device parameters of the silicon carbide floating junction JBS that meet the design requirements.
[0010] In one embodiment of the present invention, the silicon carbide floating junction JBS comprises, from bottom to top, a bottom electrode, an N+ substrate layer, an N- drift layer, and a top electrode. The bottom electrode forms an ohmic contact with the N+ substrate layer. A P-type floating junction is disposed inside the N-drift layer. A P+ region is disposed inside the upper surface of the N-drift layer. The top electrode forms an ohmic contact with the P+ region and a Schottky contact with the N-drift layer. The P-type floating junction is located directly below the P+ region and is not in contact with the P+ region.
[0011] In one embodiment of the present invention, the expression for the non-depletion, non-penetration electric field distribution is:
[0012]
[0013] The boundary conditions are:
[0014]
[0015] Where E1(x) is the electric field distribution along the x-axis of the upper half of the silicon carbide floating junction JBS, and E2(x) is the electric field distribution along the x-axis of the lower half of the silicon carbide floating junction JBS. C E is the critical breakdown electric field strength. e N represents the peak value of the electric field distribution in the upper half of the silicon carbide floating junction JBS. D ε is the doping concentration of the N-drift layer, q is the charge constant, and ε is the doping concentration of the N-drift layer. s t is the dielectric constant of silicon carbide, t1 is the thickness of the P-type floating junction, and t epi2 The distance from the P-type floating junction to the upper surface of the N-drift layer is defined as follows: the upper half of the silicon carbide floating junction JBS refers to the portion above the center position in the thickness direction of the P-type floating junction; the lower half of the silicon carbide floating junction JBS refers to the portion below the center position in the thickness direction of the P-type floating junction; and the x-axis extends vertically downward from the center position of the upper surface of the P+ region.
[0016] In one embodiment of the present invention, the expression for the non-depletion punch-through electric field distribution is:
[0017]
[0018] The boundary conditions are:
[0019]
[0020] Among them, t epi The thickness of the N-drift layer.
[0021] In one embodiment of the present invention, the expression for the surface breakdown non-penetration electric field distribution is:
[0022]
[0023] The boundary conditions are:
[0024]
[0025] Among them, E f The electric field value at the floating junction when the holes in the P-type floating junction are completely depleted.
[0026] In one embodiment of the present invention, the expression for the surface breakdown-through electric field distribution is:
[0027]
[0028] The boundary conditions are:
[0029]
[0030] In one embodiment of the present invention, the expression for the internal breakdown non-penetration electric field distribution is:
[0031]
[0032] The boundary conditions are:
[0033]
[0034] In one embodiment of the present invention, the expression for the internal breakdown-through electric field distribution is:
[0035]
[0036] The boundary conditions are:
[0037]
[0038] In one embodiment of the present invention, S2 includes:
[0039] S2.1: Establish the breakdown voltage model of the silicon carbide floating junction JBS based on charge balance theory:
[0040] BV=∫E1(x)+E2(x)dx,
[0041] Wherein, BV represents the blocking voltage of the silicon carbide floating junction JBS;
[0042] S2.2: Substitute the expressions for the six electric field distribution types into the expression for the breakdown voltage model to obtain the reverse blocking analysis model for each electric field distribution type. The reverse blocking analysis model is the corresponding blocking voltage calculation formula.
[0043] In one embodiment of the present invention, S3 includes:
[0044] S3.1: Set the device parameter range for the silicon carbide floating junction JBS to be designed;
[0045] S3.2: Based on the device parameter range, determine which of the six electric field distribution types the silicon carbide floating junction JBS to be designed belongs to;
[0046] S3.3: Based on the reverse blocking analysis model corresponding to the silicon carbide floating junction JBS, calculate the blocking voltage and determine whether the blocking voltage meets the performance design specifications. If yes, execute S3.4; otherwise, set a new device parameter range and return to S3.2 to execute again.
[0047] S3.4: Input the device parameters that meet the design specifications into the TCAD software for simulation and obtain the simulation results;
[0048] S3.5: Based on the TCAD simulation results, select the optimal device design parameters to obtain the designed silicon carbide floating junction JBS device.
[0049] Compared with the prior art, the beneficial effects of the present invention are as follows:
[0050] 1. This invention provides a charge balance-based design method for silicon carbide floating junction diodes (JBS). Based on charge balance theory, a reverse blocking analysis model for silicon carbide floating junction diodes is established. This model allows for rapid prediction of the device's blocking voltage performance, further reducing the range of optimal parameter values. The optimal simulation results are then selected in one step using TCAD software, thus determining the device design parameters. This invention significantly reduces the reliance on the designer's theoretical level and knowledge accumulation in traditional device design, bypassing numerous problems associated with TCAD simulation verification, such as modeling, mesh setting, and simulation non-convergence, thereby improving design efficiency and reducing the design cycle time.
[0051] 2. This silicon carbide floating junction structure design method can design a variety of silicon carbide semiconductor power devices containing floating junction structures according to design requirements. The designed semiconductor power devices include: diodes, Schottky diodes, barrier-controlled Schottky diodes, metal-oxide-semiconductor field-effect transistors, etc., which can be widely used in the field of electronic power and help promote the design of silicon carbide floating junction devices and the development of power devices.
[0052] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description
[0053] Figure 1 This is a flowchart of a charge balance-based silicon carbide floating junction JBS design method provided in an embodiment of the present invention;
[0054] Figure 2 This is a partial structural schematic diagram of a silicon carbide floating junction JBS provided in an embodiment of the present invention;
[0055] Figure 3 This is an electric field distribution diagram of a silicon carbide floating junction JBS provided in an embodiment of the present invention;
[0056] Figure 4 These are six electric field distribution diagrams of the silicon carbide floating junction JBS provided in the embodiments of the present invention;
[0057] Figure 5 This is a flowchart of an embodiment of the present invention for obtaining the optimal parameters of a device that meet design requirements using a reverse blocking analysis model. Detailed Implementation
[0058] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following detailed description of the charge balance-based silicon carbide floating junction JBS design method proposed according to the present invention is provided in conjunction with the accompanying drawings and specific embodiments.
[0059] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a more in-depth and concrete understanding can be gained of the technical means and effects adopted by the present invention to achieve its intended purpose. However, the accompanying drawings are for reference and illustration only and are not intended to limit the technical solutions of the present invention.
[0060] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, such that an article or apparatus comprising a list of elements includes not only those elements but also other elements not expressly listed. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes said element.
[0061] This invention establishes a reverse blocking analysis model for silicon carbide floating junction diodes based on charge balance theory. This reverse blocking analysis model can quickly predict the blocking voltage performance of the device, further reducing the range of optimal parameter values. Then, the optimal simulation results are selected in one go using TCAD software to determine the device design parameters.
[0062] Please see Figure 1 , Figure 1 This is a flowchart illustrating a charge-balance-based silicon carbide floating junction (JBS) design method according to an embodiment of the present invention. The design method includes:
[0063] S1: Based on the charge balance theory, six electric field distribution types of the silicon carbide floating junction JBS to be designed are obtained. The six electric field distribution types are non-depletion non-punch-through electric field distribution, non-depletion punch-through electric field distribution, surface breakdown non-punch-through electric field distribution, surface breakdown punch-through electric field distribution, internal breakdown non-punch-through electric field distribution, and internal breakdown punch-through electric field distribution.
[0064] Please see Figure 2 and Figure 3 , Figure 2 This is a partial structural schematic diagram of a silicon carbide floating junction JBS provided in an embodiment of the present invention; Figure 3 This is an electric field distribution diagram of a silicon carbide floating junction JBS provided in an embodiment of the present invention. The silicon carbide floating junction JBS includes, from bottom to top, a bottom electrode, an N+ substrate layer, an N- drift layer, and a top electrode. An ohmic contact is formed between the bottom electrode and the N+ substrate layer. A P-type floating junction is disposed inside the N- drift layer. A P+ region is disposed inside the upper surface of the N- drift layer, and the top electrode forms an ohmic contact with the P+ region and a Schottky contact with the N- drift layer. The P-type floating junction is located directly below the P+ region and does not contact the P+ region, and the P-type floating junction and the P+ region have the same width.
[0065] To establish a reverse blocking analysis model for the floating junction JBS, this embodiment of the invention employs a one-dimensional approximate electric field model to study its breakdown characteristics. First, the electric field distribution of the silicon carbide floating junction JBS is extracted along the dashed line (i.e., the central axis of the device) in the electric field distribution diagram, as shown below. Figure 3 As shown, where E c E represents the critical breakdown electric field. e E represents the electric field value at the JBS surface when the electric field extends to the floating junction. f This represents the electric field value at the floating junction when all holes in the floating junction are completely depleted. First, the theoretical basis for determining device breakdown is given. In this embodiment, breakdown is considered to occur when the device's electric field strength reaches the critical breakdown electric field strength:
[0066]
[0067] Where, N D The doping concentration of the N-drift layer.
[0068] In practical devices, two-dimensional effects need to be considered. That is, electrons in the N-drift region of the device will deplete some of the holes in the P-type floating junction. When the spacing S between adjacent P-type floating junctions in the device is large, more floating junction holes will be depleted laterally in the device drift region, leading to an increase in E. f This reduces the voltage. Therefore, parameter Z is introduced to correct the device's breakdown voltage model. Therefore, E e and E f We can obtain:
[0069]
[0070]
[0071]
[0072] Where, N A ε is the doping concentration of the P-type floating junction, q is the charge constant, and ε is the doping concentration of the P-type floating junction. s t is the dielectric constant of silicon carbide, t1 is the thickness of the P-type floating junction, and t epi2 W represents the distance from the P-type floating junction to the upper surface of the N-drift layer, and W represents the width of the P+ region.
[0073] The working principle of a single-layer silicon carbide floating junction (JBS) was then analyzed: As the reverse voltage gradually increases, the electric field of the JBS extends from the device surface to the device interior. Due to the presence of a p-type floating junction in the N-drift region, when the upper half of the electric field boundary extends to the p-type floating junction, the electric field value at the p-type floating junction will be clamped to 0 (at this time, the peak electric field value at the JBS surface is Ee). According to the charge balance theory, the electric field distribution in the upper half does not change with the increase of the reverse voltage until the holes in the p-type floating junction are completely depleted. When the holes in the floating junction are completely depleted (at this time, the peak electric field value at the floating junction is Ee), the electric field distributions in both the upper and lower halves will increase simultaneously with the increase of the reverse voltage until one of the electric field peak values reaches Ec, at which point the device breaks down. Therefore, it can be inferred that the electric field at the p-type floating junction is not always 0 when breakdown occurs; this is determined by whether the p-type floating junction is completely depleted. It should be noted that the boundary between the upper and lower electric fields is the floating junction. The upper part of the silicon carbide floating junction JBS refers to the part above the center position in the thickness direction of the P-type floating junction, and the lower part of the silicon carbide floating junction JBS refers to the part below the center position in the thickness direction of the P-type floating junction.
[0074] Under these conditions, the doping concentration N of the p-type floating junction is indicated. A This is a crucial factor affecting the electric field distribution within a device. Based on the above analysis, the electric field distribution during breakdown can be classified into six types: non-depletion non-punch-through electric field distribution, non-depletion punch-through electric field distribution, surface breakdown non-punch-through electric field distribution, surface breakdown punch-through electric field distribution, internal breakdown non-punch-through electric field distribution, and internal breakdown punch-through electric field distribution. Figure 4 As shown. If the doping concentration N of the p-type floating junction... A If the voltage is too high, the lower half of the electric field in the p-type floating junction will reach the critical breakdown electric field (Ec) before depletion. This type of device is defined as an IDFJ JBS (Incomplete Depletion Floating Junction Barrier-Controlled Schottky Diode), and the breakdown voltage calculation is divided into two cases: non-depletion non-punch-through type and non-depletion punch-through type. For example... Figure 4 As shown in (b) and 4(c), the p-type floating junction in the JBS drift region is moderately doped. When the p-type floating junction is fully depleted, if Ee > Ef, the electric field in the upper half of the JBS device reaches Ec first. On the other hand, the electric field in the lower half of the JBS device reaches Ec first. This device is defined as FDFJ JBS (fully depleted floating junction barrier controlled Schottky diode). Considering whether the bottom electric field punches through, the breakdown voltage of FDFJ JBS will be calculated in four cases: surface breakdown non-punch-through type, surface breakdown punch-through type, internal breakdown non-punch-through type, and internal breakdown punch-through type, as shown in... Figure 4 As shown in (b) and 4(c).
[0075] Specifically, (1) the expression for the non-depletion, non-penetration electric field distribution is:
[0076]
[0077] The boundary conditions are:
[0078]
[0079] Wherein, E1(x) is the electric field distribution along the x-axis of the upper half of the silicon carbide floating junction JBS, and E2(x) is the electric field distribution along the x-axis of the lower half of the silicon carbide floating junction JBS, wherein the x-axis extends vertically downward from the center of the upper surface of the P+ region.
[0080] (2) The expression for the non-depletion punch-through electric field distribution is:
[0081]
[0082] The boundary conditions are:
[0083]
[0084] (3) The expression for the surface breakdown non-penetration electric field distribution is:
[0085]
[0086] The boundary conditions are:
[0087]
[0088] (4) The expression for the surface breakdown-through electric field distribution is:
[0089]
[0090] The boundary conditions are:
[0091]
[0092] (5) The expression for the internal breakdown non-penetration electric field distribution is:
[0093]
[0094] The boundary conditions are:
[0095]
[0096] (6) The expression for the internal breakdown-through electric field distribution is:
[0097]
[0098] The boundary conditions are:
[0099]
[0100] S2: Establish reverse blocking analysis models corresponding to different electric field distribution types using the six types of electric field distribution.
[0101] Based on the six types of electric field distribution under breakdown conditions, the one-dimensional electric field distribution in the drift region is integrated, consisting of the upper electric field (E1) and the lower electric field (E2), and a breakdown voltage model of silicon carbide floating junction devices can be established.
[0102] Specifically, step S2 in this embodiment includes:
[0103] S2.1: Establish the breakdown voltage model of the silicon carbide floating junction JBS based on charge balance theory:
[0104] BV=∫E1(x)+E2(x)dx,
[0105] Wherein, BV represents the blocking voltage of the silicon carbide floating junction JBS;
[0106] S2.2: Substitute the expressions for the six electric field distribution types into the expression for the breakdown voltage model to obtain the reverse blocking analysis model for each electric field distribution type. The reverse blocking analysis model is the corresponding blocking voltage calculation formula.
[0107] S3: Use the reverse blocking analysis model to obtain the optimal device parameters of the silicon carbide floating junction JBS that meet the design requirements.
[0108] Please see Figure 5 , Figure 5 This is a flowchart illustrating how a reverse blocking analysis model can be used to obtain optimal device parameters that meet design requirements, according to an embodiment of the present invention. Step S3 of this embodiment further includes the following steps:
[0109] S3.1: Set the device parameter range for the silicon carbide floating junction JBS to be designed, wherein the device parameters include t epi t epi2 , t1, N D N A 、W、S.
[0110] S3.2: Determine which of the six electric field distribution types the silicon carbide floating junction JBS to be designed belongs to based on the device parameter range;
[0111] S3.3: Based on the reverse blocking analysis model corresponding to the silicon carbide floating junction JBS, calculate the blocking voltage and determine whether the blocking voltage meets the performance design specifications. If yes, execute S3.4; otherwise, set a new device parameter range and return to S3.2 to execute again.
[0112] S3.4: Input the device parameters that meet the design specifications into the TCAD software for simulation and obtain the simulation results;
[0113] S3.5: Based on the TCAD simulation results, select the optimal device design parameters to obtain the designed silicon carbide floating junction JBS device.
[0114] This invention provides a charge balance-based design method for silicon carbide floating junction diodes (SCBs). Based on charge balance theory, a reverse blocking analysis model for SCBs is established. This model allows for rapid prediction of the device's blocking voltage performance, further narrowing the range of optimal parameter values. The optimal simulation results are then selected in a single step using TCAD software, determining the device design parameters. This invention significantly reduces the reliance on the designer's theoretical knowledge and experience in traditional device design, bypassing numerous problems associated with TCAD simulation verification, such as modeling, mesh setup, and simulation non-convergence. This improves design efficiency, reduces the design cycle time, and the design method can also be applied to other power device fields.
[0115] Furthermore, this silicon carbide floating junction structure design method can be used to design a variety of silicon carbide semiconductor power devices that include floating junction structures according to design requirements. The designed semiconductor power devices include diodes, Schottky diodes, barrier-controlled Schottky diodes, metal-oxide-semiconductor field-effect transistors, etc., which can be widely used in the field of electronic power and help promote the design of silicon carbide floating junction devices and the development of power devices.
[0116] Another embodiment of the present invention provides a storage medium storing a computer program for executing the steps of the charge balance-based silicon carbide floating junction JBS design method described in the above embodiments. A further aspect of the present invention provides an electronic device including a memory and a processor. The memory stores a computer program, and the processor, when calling the computer program in the memory, implements the steps of the charge balance-based silicon carbide floating junction JBS design method described in the above embodiments. Specifically, the integrated modules implemented as software functional modules can be stored in a computer-readable storage medium. These software functional modules, stored in a storage medium, include several instructions to cause an electronic device (which may be a personal computer, server, or network device, etc.) or processor to execute some steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.
[0117] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.
Claims
1. A charge balance-based design method for silicon carbide floating junction JBS, characterized in that, include: S1: Based on the charge balance theory, six electric field distribution types of the silicon carbide floating junction JBS to be designed are obtained. The six electric field distribution types are non-depletion non-punch-through electric field distribution, non-depletion punch-through electric field distribution, surface breakdown non-punch-through electric field distribution, surface breakdown punch-through electric field distribution, internal breakdown non-punch-through electric field distribution, and internal breakdown punch-through electric field distribution. S2: Establish reverse blocking analysis models corresponding to different electric field distribution types using the six types of electric field distribution; S3: Use the reverse blocking analysis model to obtain the optimal device parameters of the silicon carbide floating junction JBS that meet the design requirements; The expression for the non-depletion, non-penetration electric field distribution is: ， The boundary conditions are: ， in, The upper half of the silicon carbide floating junction JBS is along x Electric field distribution on the axis, The lower half of the silicon carbide floating junction JBS is along x Electric field distribution on the axis, E C The critical breakdown electric field strength, E e The peak value of the electric field distribution in the upper half of the silicon carbide floating junction JBS is given. N D The doping concentration of the N-drift layer. q It is a constant charge. The dielectric constant of silicon carbide is... The thickness of the P-type floating junction. The distance from the P-type floating junction to the upper surface of the N-drift layer is defined as follows: the upper half of the silicon carbide floating junction JBS refers to the portion above the center position in the thickness direction of the P-type floating junction, and the lower half of the silicon carbide floating junction JBS refers to the portion below the center position in the thickness direction of the P-type floating junction. x The axis extends vertically downwards from the center of the upper surface of the P+ region; The expression for the non-depletion punch-through electric field distribution is: ， The boundary conditions are: ， in, The thickness of the N-drift layer; The expression for the surface breakdown non-penetration electric field distribution is: ， The boundary conditions are: ， in, This represents the electric field value at the floating junction when all holes in the P-type floating junction are completely depleted. N A The doping concentration of the P-type floating junction; The expression for the surface breakdown-through electric field distribution is: ， The boundary conditions are: ； The expression for the internal breakdown non-penetration electric field distribution is: ， The boundary conditions are: ； The expression for the internal breakdown-through electric field distribution is: The boundary conditions are: 。 2. The charge balance-based silicon carbide floating junction JBS design method according to claim 1, characterized in that, The silicon carbide floating junction JBS comprises, from bottom to top, a bottom electrode, an N+ substrate layer, an N- drift layer, and a top electrode. The bottom electrode forms an ohmic contact with the N+ substrate layer. A P-type floating junction is disposed within the N- drift layer. A P+ region is disposed within the upper surface of the N- drift layer, and the top electrode forms an ohmic contact with the P+ region. The top electrode also forms a Schottky contact with the N- drift layer. The P-type floating junction is located directly below the P+ region and is not in contact with it.
3. The charge balance-based silicon carbide floating junction JBS design method according to claim 2, characterized in that, S2 includes: S2.1: Establish the breakdown voltage model of the silicon carbide floating junction JBS based on charge balance theory: ， in, This represents the blocking voltage of the silicon carbide floating junction JBS; S2.2: Substitute the expressions for the six electric field distribution types into the expression for the breakdown voltage model to obtain the reverse blocking analysis model for each electric field distribution type. The reverse blocking analysis model is the corresponding blocking voltage calculation formula.
4. The charge balance-based silicon carbide floating junction JBS design method according to any one of claims 1 to 3, characterized in that, S3 includes: S3.1: Set the device parameter range for the silicon carbide floating junction JBS to be designed; S3.2: Based on the device parameter range, determine which of the six electric field distribution types the silicon carbide floating junction JBS to be designed belongs to; S3.3: Based on the reverse blocking analysis model corresponding to the silicon carbide floating junction JBS, calculate the blocking voltage and determine whether the blocking voltage meets the performance design specifications. If yes, execute S3.4; otherwise, set a new device parameter range and return to S3.2 to execute again. S3.4: Input the device parameters that meet the design specifications into the TCAD software for simulation and obtain the simulation results; S3.5: Based on the TCAD simulation results, select the optimal device design parameters to obtain the designed silicon carbide floating junction JBS device.