Resistive memory device

Abstract

A resistive memory device includes a plurality of bit lines, a plurality of word lines, a memory array, a plurality of bypass paths, a plurality of selection circuits, and a switch circuit. The plurality of word lines cross the plurality of bit lines. The memory array includes a plurality of memory elements. One end of each memory element is coupled to a corresponding word line, and another end of each memory element is coupled between a first end point and a second end point on a corresponding bit line. Each bypass path is parallel to the corresponding bit line between the first end point and the second end point. Each selection circuit is coupled to the corresponding bit line and bypass path and is configured to select the coupled bit line or bypass path. The switch circuit is coupled to the plurality of word lines and is configured to select one of the plurality of word lines.

Description

Technical Field

[0001] This invention relates to a storage device, and more particularly to a resistive storage device. Background Technology

[0002] Resistive random access memory (RRAM) is a type of non-volatile memory that is being actively developed in the industry. In a 1-transistor-1-resistor (1T1R) architecture, the transistor controls the current flowing through the resistive memory cell. In this type of architecture, the transistor used to control the current has a relatively large area. Attempting to shrink the transistor leads to increased manufacturing complexity and a decrease in the current supplied. Therefore, the 1-selector-1-resistor (1S1R) architecture, which replaces the transistor with a selector, is gradually being adopted by the industry.

[0003] However, in the current 1-selector-1-resistor architecture, even unselected memory components generate sneak current, which can easily cause read operation errors and sometimes cause neighboring memory components to switch states improperly. For example, Figure 1A and Figure 1B This diagram illustrates the creeping current in a conventional resistive storage device. Please refer to... Figure 1A and Figure 1B ,exist Figure 1A In this process, because the storage component MT is selected to operate, the switching component SW is turned on to write data to or read data from the storage component MT. However, as... Figure 1A As shown, the unselected storage component MN1 may also generate a creeping current SC1 along path P1, thus affecting operation. Similarly, as Figure 1B As shown, the unselected storage components MN2 and MN3 may also generate a creeping current SC2 along path P2, which may affect the operation.

[0004] by Figure 1A and Figure 1B The more cells connected in a certain way, the greater the impact of creeping current. Therefore, how to manage creeping current is a major issue for designers in this field. Summary of the Invention

[0005] This invention provides a resistive storage device that can manage creeping current and reduce the impact of creeping current.

[0006] The resistive memory device of the present invention includes a plurality of bit lines, a plurality of word lines, a memory array, a plurality of bypass paths, a plurality of selection circuits, and a switching circuit. The plurality of word lines intersect the plurality of bit lines. The memory array includes a plurality of memory components. One end of each memory component is coupled to a corresponding word line, and the other end of each memory component is coupled between a first endpoint and a second endpoint of a corresponding bit line. Each bypass path is connected in parallel with a corresponding bit line between the first endpoint and the second endpoint. Each selection circuit is coupled to a corresponding bit line and a bypass path, and is configured to select either the coupled bit line or the bypass path. The switching circuit is coupled to the plurality of word lines and is configured to select one of the plurality of word lines.

[0007] In one embodiment of the present invention, when one of the plurality of memory components is selected as the selected memory component, the selected bit line is selected by a selection circuit coupled to the selected memory component via a bit line, and the other selection circuits select the coupled bypass path.

[0008] Based on the above, in the resistive memory device of the present invention, when one of a plurality of memory components is selected, the conduction paths of the bit lines other than those required to operate the selected memory component can be replaced by bypass paths. Therefore, the resistive memory device of the present invention can reduce the paths that generate creeping current, and even in architectures with larger areas, it can reliably reduce the impact of creeping current. Attached Figure Description

[0009] Figure 1A and Figure 1B A schematic diagram illustrating the creeping current in an existing resistive storage device;

[0010] Figure 2 This is a block diagram of a resistive storage device according to an embodiment of the present invention;

[0011] Figure 3 This is a circuit diagram of a resistive storage device according to an embodiment of the present invention;

[0012] Figure 4 This is a block diagram of a storage component according to an embodiment of the present invention;

[0013] Figure 5A and Figure 5B This is an example of the operation method of the selection circuit according to an embodiment of the present invention.

[0014] Explanation of reference numerals in the attached figures

[0015] 100: Resistive storage device

[0016] 110: Storage Array

[0017] 120_0~120_3: Selection circuit

[0018] 130: Switching circuit

[0019] 200: Resistive memory cell

[0020] 210: Selector Detailed Implementation

[0021] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same component reference numerals are used in the drawings and description to denote the same or similar parts.

[0022] Figure 2 This is a block diagram of a resistive storage device according to an embodiment of the present invention. Figure 3 This is a circuit diagram of a resistive storage device according to an embodiment of the present invention. Please also refer to... Figure 2 and Figure 3 The resistive memory device 100 includes bit lines BL0-BL3, word lines WL0-WL3, bypass paths BP0-BP3, a memory array 110, selection circuits 120_0-120_3, and a switching circuit 130. For example... Figure 3 As shown, word lines WL0 to WL3 are respectively intersected with bit lines BL0 to BL3, with an intersection angle of approximately 90 degrees, but the invention is not limited thereto. The resistive memory device 100 is, for example, a subset of a larger memory array.

[0023] The storage array 110 includes storage components M00 to M33. One end of storage components M00 to M03 is coupled to word line WL0, one end of storage components M10 to M13 is coupled to word line WL1, one end of storage components M20 to M23 is coupled to word line WL2, and one end of storage components M30 to M33 is coupled to word line WL3. The other end of storage components M00, M10, M20, and M30 is coupled between the first endpoint ND1_0 and the second endpoint ND2_0 on bit line BL0. The other end of storage components M01, M11, M21, and M31 is coupled between the first endpoint ND1_1 and the second endpoint ND2_1 on bit line BL1. The other end of storage components M02, M12, M22, and M32 is coupled between the first endpoint ND1_2 and the second endpoint ND2_2 on bit line BL2. The other end of storage components M03, M13, M23, and M33 is coupled between the first endpoint ND1_3 and the second endpoint ND2_3 on bit line BL3.

[0024] The internal structure of the storage component in this embodiment is described below using storage component M00 as an example. The internal structures of other storage components M01 to M33 are the same as those of storage component M00. Figure 4This is a block diagram of a storage component according to an embodiment of the present invention. Please refer to... Figure 4 The storage component M00 includes a resistive storage cell 200 and a selector 210. The resistive storage cell 200 can provide storage for a single bit of data. The selector 210 can be a bidirectional threshold switch (OTS), which is a two-terminal symmetrical voltage-sensitive switching component. For example, when an applied voltage less than a threshold voltage is applied to the selector 210, the selector 210 remains in the off state (e.g., non-conductive state). On the other hand, when an applied voltage greater than a threshold voltage is applied to the selector 210 in either direction, the selector 210 becomes the on state (e.g., conductive state). That is, the selector 210 allows bidirectional switching and has the advantage of small area because it does not require a terminal to control whether it is on (e.g., the gate of a metal-oxide-semiconductor field-effect transistor (MOSFET) or the base of a bipolar junction transistor (BJT)). Furthermore, selector 210 can be based on field-enhanced emission or tunneling.

[0025] It should be noted that the arrangement order of the resistive memory cell 200 and the selector 210 in the storage component M00 is not limited in this invention, as long as the configuration of one resistive memory cell 200 and one selector 210 in one storage component M00 is acceptable. In one embodiment, the selector 210 may also be integrated into the resistive memory cell 200.

[0026] Back Figure 2 and Figure 3 The bypass paths BP0 to BP3 are connected in parallel with bit lines BL0 to BL3, respectively. For example... Figure 3 As shown, bypass path BP0 is connected in parallel with bit line BL0 between the first endpoint ND1_0 and the second endpoint ND2_0. Bypass path BP1 is connected in parallel with bit line BL1 between the first endpoint ND1_1 and the second endpoint ND2_1. Bypass path BP2 is connected in parallel with bit line BL2 between the first endpoint ND1_2 and the second endpoint ND2_2. Bypass path BP3 is connected in parallel with bit line BL3 between the first endpoint ND1_3 and the second endpoint ND2_3.

[0027] Selection circuits 120_0 to 120_3 are respectively coupled to bit lines BL0 to BL3 and bypass paths BP0 to BP3. Selection circuit 120_0 is coupled to bit line BL0 and bypass path BP0, and is configured to select either bit line BL0 or bypass path BP0 for voltage or current conduction. Selection circuit 120_1 is coupled to bit line BL1 and bypass path BP1, and is configured to select either bit line BL1 or bypass path BP1 for voltage or current conduction. Selection circuit 120_2 is coupled to bit line BL2 and bypass path BP2, and is configured to select either bit line BL2 or bypass path BP2 for voltage or current conduction. Selection circuit 120_3 is coupled to bit line BL3 and bypass path BP3, and is configured to select either bit line BL3 or bypass path BP3 for voltage or current conduction.

[0028] Switching circuit 130 is coupled to word lines WL0 to WL3. Switching circuit 130 is configured to select one of word lines WL0 to WL3 for voltage or current conduction.

[0029] In this embodiment, both the selection circuits 120_0 to 120_3 and the switching circuit 130 can achieve the selection operation by operating the switching component. The switching component can, for example, be composed of a transistor. Figure 3 As shown, selection circuit 120_0 includes a first switch component SW1_0 and a second switch component SW2_0; selection circuit 120_1 includes a first switch component SW1_1 and a second switch component SW2_1; selection circuit 120_2 includes a first switch component SW1_2 and a second switch component SW2_2; and selection circuit 120_3 includes a first switch component SW1_3 and a second switch component SW2_3. Switching circuit 130 includes third switch components SW3_0 to SW3_3.

[0030] The first switching components SW1_0 to SW1_3 can be turned on or off by control signals SBL0 to SBL3, respectively. The second switching components SW2_0 to SW2_3 can be turned on or off by control signals SBP0 to SBP3, respectively. The third switching components SW3_0 to SW3_3 can be turned on or off by control signals SWL0 to SWL3, respectively. The control signals SBL0 to SBL3, SBP0 to SBP3, and SWL0 to SWL3 can, for example, come from a memory controller external to the resistive memory device 100.

[0031] The internal circuits of selection circuits 120_0 to 120_3 are configured similarly. Taking selection circuit 120_0 as an example, the first switch component SW1_0 is configured on bit line BL0, and the second switch component SW2_0 is configured on bypass path BP0. One end of the first switch component SW1_0 and one end of the second switch component SW2_0 are coupled to ND2_0 on bit line BL0. In switch circuit 130, one end of the third switch components SW3_0 to SW3_3 is coupled to word lines WL0 to WL3, respectively, and the other end of the third switch components SW3_0 to SW3_3 is coupled to source line SL.

[0032] In this embodiment, when one of the storage components M00 to M33 is selected as the selection storage component MS, the selection circuit coupled to the selection storage component MS via a bit line selects the coupled bit line for voltage or current conduction. Other selection circuits select the coupled bypass path for voltage or current conduction. The selection storage component MS is chosen, for example, for write or read operations. The following description uses storage component M10 as an example to illustrate the operation when storage component M10 is selected as the selection storage component MS.

[0033] Specifically Figure 5A and Figure 5B This is an example of the operation method of a selection circuit according to an embodiment of the present invention. When the selection memory component MS (memory component M10) is selected, the selection circuit 120_0 selects the bit line BL0 for voltage or current conduction. For example... Figure 5A As shown, the first switch component SW1_0, located on the bit line BL0 corresponding to the selected storage component MS, is turned on based on the control signal SBL0 at the on level VP to generate a current I1. The second switch component SW2_0, located on the bypass path BP0 in parallel with the bit line BL0, is turned off based on the control signal SBP0 at the off level V0.

[0034] On the other hand, when the selected memory component MS (memory component M10) is selected, the selection circuits 120_1 to 120_3 will respectively select bypass paths BP1 to BP3 for voltage or current conduction. The first switching components SW1_1 to SW1_3, located on the bit lines BL1 to BL3 corresponding to other memory components, will be disconnected, and the second switching components SW2_1 to SW2_3, located on the bypass paths BP1 to BP3 connected in parallel with the bit lines BL1 to BL3 corresponding to other memory components, will be turned on. Taking selection circuit 120_1 as an example, if... Figure 5BAs shown, the first switch component SW1_1, which is set on the bit line BL1, will be turned off based on the control signal SBL1 with the off level V0, and the second switch component SW2_1, which is set on the bypass path BP1 in parallel with the bit line BL1, will be turned on based on the control signal SBP1 with the on level VP, so as to generate current I2.

[0035] Furthermore, when the selected storage component MS (storage component M10) is selected, the third switch component SW3_1 coupled to the word line WL1 corresponding to the selected storage component MS will also be turned on based on the control signal SWL1 of the on-level VP.

[0036] In this way, when the selected memory module (MS) is chosen for a write or read operation, only the bit lines coupled to the selected MS remain on, while the conduction paths of other bit lines are replaced by bypass paths. This limits the flow to a sufficiently small subset of the memory array, reducing the amount of creeping current and thus mitigating its impact.

[0037] It should be noted that, in this embodiment of the invention, a 4x4 memory array 110 comprising 16 memory components M00 to M33 is used for illustration. However, the invention is not limited thereto. As long as the circuit structure conforms to the bypass path taught in this invention, those skilled in the art can extrapolate the number of memory components used to a greater extent according to their actual needs, based on the teachings of this invention. Furthermore, those skilled in the art can also appropriately arrange multiple resistive memory devices taught in this invention, for example, in the direction of bit line extension, to expand them into a larger memory array.

[0038] In summary, the resistive memory device of the present invention is configured with multiple bypass paths. When one of the multiple memory components is selected, the conduction paths of other bit lines, except for the bit lines required to operate on the selected memory component, can be replaced by bypass paths. Therefore, the resistive memory device of the present invention can reduce the paths that generate creeping current, and even in large-area architectures, the effects of creeping current can be reliably reduced.

[0039] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A resistive storage device, characterized in that, include: Multiple bit lines; Multiple word lines are configured to intersect with the multiple bit lines, respectively; A storage array includes multiple storage components, one end of each of the multiple storage components being coupled to a corresponding word line, and the other end of each of the multiple storage components being coupled between a first endpoint and a second endpoint of a corresponding bit line; Multiple bypass paths, each of which is connected in parallel with the corresponding bit line between the first endpoint and the second endpoint; Multiple selection circuits, each of which is coupled to a corresponding bit line and a bypass path, configured to select the coupled bit line or the bypass path; as well as A switching circuit, coupled to the plurality of word lines, configured to select one of the plurality of word lines. When one of the plurality of memory components is selected as the selected memory component, the selected circuitry coupled to the selected memory component selects the coupled bit line, and the other selected circuitry selects the coupled bypass path.

2. The resistive memory device according to claim 1, characterized in that, Each of the plurality of selection circuits includes a first switch component and a second switch component, the first switch component being configured on a corresponding bit line, the second switch component being configured on a corresponding bypass path, and one end of the first switch component and one end of the second switch component being coupled to the second endpoint of the corresponding bit line.

3. The resistive memory device according to claim 2, characterized in that, When the selected storage component is selected, the first switch component on the bit line corresponding to the selected storage component is turned on, and the second switch component on the bypass path connected in parallel with the bit line corresponding to the selected storage component is turned off.

4. The resistive memory device according to claim 2, characterized in that, When the selected storage component is selected, the first switch component located on the bit line corresponding to the other storage components is turned off, and the second switch component located on the bypass path connected in parallel with the bit line corresponding to the other storage components is turned on.

5. The resistive memory device according to claim 1, characterized in that, The switching circuit includes a plurality of third switching components, one end of which is coupled to the plurality of word lines, and the other end of which is coupled to the source line. When the selected storage component is selected, the third switch component coupled to the word line corresponding to the selected storage component is turned on.

6. The resistive memory device according to claim 1, characterized in that, Each of the plurality of storage components includes a resistive storage cell and a selector.

7. The resistive memory device according to claim 6, characterized in that, The selector is a bidirectional threshold switch, which is a two-terminal symmetrical voltage-sensitive switch assembly.

8. The resistive memory device according to claim 6, characterized in that, The selector is based on field-enhanced emission or tunneling.

9. The resistive memory device according to claim 6, characterized in that, The selector is integrated into the resistive memory cell.

10. The resistive memory device according to claim 6, characterized in that, When an applied voltage less than a threshold voltage is applied to the selector, the selector remains in the off state; when an applied voltage greater than the threshold voltage is applied to the selector in either direction, the selector becomes in the on state.

11. The resistive memory device according to claim 6, characterized in that, The selector allows for bidirectional switching.

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