Semiconductor device and programming method

Abstract

A semiconductor device and a programming method capable of performing programming with suppressed power consumption are provided. A programming method of a NAND type flash memory of the present invention prepares a block for high-speed programming and a block for write-back for finally storing data, and in response to a programming instruction inputted from the outside in a power saving mode, data of 1 / 2 pages is programmed at high speed in even pages and odd pages of the block for high-speed programming, respectively, and thereafter, in a state where the power saving mode is eliminated, data is read out from the block for high-speed programming, and the read-out data is normally programmed to the block for write-back.

Description

Technical Field

[0001] This invention relates to a semiconductor device such as a NAND flash memory, and particularly to a programming method capable of operating with low power. Background Technology

[0002] In programming NAND flash memory, incremental step pulse programming (ISPP) is used to control the threshold distribution of memory cells. ISPP applies a programming pulse Vpgm0 to the selected page and applies a programming pulse Vpgm1, which is one step voltage higher than the programming pulse Vpgm0, to memory cells that are determined to be unqualified in the program verify. This enables the narrowing of the threshold distribution width (e.g., Japanese Patent No. 5583185).

[0003] Internet of Things (IoT) devices that utilize solar power or batteries require power-saving modes to reduce power consumption during periods of insufficient power supply, such as nighttime when solar power generation is effectively stopped or when battery capacity is low.

[0004] When such IoT devices incorporate NAND flash memory, the NAND flash memory is required to operate with low power. However, programming the flash memory requires a programming voltage of approximately 20V to the selected pages and a pass voltage of approximately 10V to the non-selected pages, necessitating relatively high power consumption. Furthermore, if the programming verification fails, the process is repeated until it succeeds, further consuming power. Summary of the Invention

[0005] The present invention addresses this existing problem and aims to provide a semiconductor device and programming method capable of performing programming that suppresses power consumption.

[0006] The programming method of the NAND flash memory of the present invention includes the steps of: allocating at least one block to a high-speed programming block and allocating at least one block to a storage block for final data storage; in response to a programming instruction input from an external source, high-speed programming 1 / 2 page of data in two selected pages of the high-speed programming block respectively; and reading the data of the two selected pages of the high-speed programming block and normally programming the read data into the storage block.

[0007] The semiconductor device of the present invention includes: a NAND-type memory cell array; and a programming unit for programming selected pages of the memory cell array. The programming unit includes a normal programming mode and a high-speed programming mode. The high-speed programming mode includes: allocating at least one block to a high-speed programming block and allocating at least one block to a storage block for final data storage; in response to a programming instruction input from an external source, high-speed programming half a page of data in two selected pages of the high-speed programming block; and reading the data from the two selected pages of the high-speed programming block and normally programming the read data into the storage block.

[0008] According to the present invention, half a page of data is programmed at high speed in separate high-speed programming blocks, thus reducing power consumption caused by high-speed programming compared to conventional programming. Attached Figure Description

[0009] Figure 1 This is a block diagram of the structure of a NAND flash memory according to an embodiment of the present invention.

[0010] Figure 2 This is a diagram illustrating the structure of the memory cell array and word line selection / driving circuit according to an embodiment of the present invention.

[0011] Figure 3 This is a diagram illustrating the functionality of the low-power / high-speed programming mode in an embodiment of the present invention.

[0012] Figure 4 This is a diagram illustrating the block management actions in low-power / high-speed programming mode.

[0013] Figure 5 This is a diagram illustrating the allocation of write-back blocks and high-speed programming blocks.

[0014] Figure 6 This is a diagram illustrating the actions of high-speed programming in low-power / high-speed programming mode.

[0015] Figure 7 This is a diagram illustrating high-speed programming in a low-power / high-speed programming mode.

[0016] Figure 8 This is a diagram of the voltage waveform during high-speed programming in low-power / high-speed programming mode.

[0017] Figure 9 This is a diagram illustrating the write-back process in low-power / high-speed programming mode.

[0018] Figure 10 This is a diagram illustrating the write-back process in low-power / high-speed programming mode.

[0019] Figure 11This is a diagram illustrating the allocation example of new write-back blocks and high-speed programming blocks based on low-power / high-speed programming mode block management.

[0020] [Explanation of Symbols]

[0021] 100: Flash Memory

[0022] 110: Memory cell array

[0023] 120: Input / Output Buffer

[0024] 130: Address Register

[0025] 140: Controller

[0026] 150: Word line selection / drive circuit

[0027] 152: Block Selection Circuit

[0028] 154: Block Selection Transistor

[0029] 156: Drive Circuit

[0030] 156A: Short-circuit circuit

[0031] 156B: Discharge Circuit

[0032] 160: Page buffer / sensing circuit

[0033] 170: Column Selection Circuit

[0034] 180: Internal voltage generation circuit

[0035] 190: Bit line selection circuit

[0036] Ax: Row address information

[0037] Ay: Column address information

[0038] BL0, BL1~BLn-2, ​​BLn-1: Bit lines

[0039] BLe: Even bit line / bit line

[0040] BLK0, BLK1~BLKm-1: Blocks

[0041] BLK12: Write-back blocks / blocks

[0042] BLK13, BLK14: High-speed programming blocks / blocks

[0043] BLo: Odd bit line / bit line

[0044] BSEL: Block Selection Signal

[0045] ExVDD: External power supply voltage

[0046] MC0, MC1 to MC30, MC31: Storage units

[0047] NU: NAND string

[0048] P0, P2, P4, P6: Page / Even Page

[0049] P1, P3, P5, P7: Pages / Odd-numbered pages

[0050] S10: Block Management / Steps

[0051] S20: High-speed programming / steps

[0052] S30: Write-back / Steps

[0053] S100, S110, S120, S200, S210, S220, S300, S310, S320, S330, S340: Steps

[0054] SGD, SGS: Select gate line

[0055] SL: Source Line

[0056] TR1: Bit line side select transistor

[0057] TR2: Source-side select transistor

[0058] t1, t2, t3, t4, t5, t6, t7, t8, t9: Time points

[0059] Vers: Erasure voltage

[0060] Vpass: Through voltage

[0061] Vpgm, Vpgm1, Vpgm2, VWW: Programming voltage

[0062] Vpgm0: Programming pulse

[0063] Vread: Readout voltage

[0064] WL0, WL1~WL30, WL31: Word lines

[0065] WL-SL: Select wordline

[0066] WL-inh1, WL-inh2: Non-selective word lines Detailed Implementation

[0067] The semiconductor device of the present invention includes, for example, a NAND flash memory, or a microprocessor, microcontroller, logic, application-specific integrated circuit (ASIC), processor for processing images or sound, processor for processing signals such as wireless signals, etc. In the following description, a NAND flash memory is used as an example.

[0068] like Figure 1 As shown, the flash memory 100 of this embodiment includes the following components: a memory cell array 110, which forms a plurality of memory cells; an input / output buffer 120, which is connected to an external input / output terminal (I / O); an address register 130, which receives address data from the input / output buffer 120; a controller 140, which controls each part based on instruction data from the input / output buffer 120 or external control signals; and a word line selection / driving circuit 150, which selects blocks or word lines based on the row address information Ax from the address register 130. The page buffer / sensing circuit 160 holds data read from the selected page of the memory cell array 110 or data to be programmed to the selected page; the column selection circuit 170 selects columns (bit lines) within the page buffer / sensing circuit 160 based on column address information Ay from the address register 130; and the internal voltage generation circuit 180 generates various voltages required for reading, programming, and erasing (programming voltage Vpgm, read voltage Vread, erase voltage Vers, programming or read pass voltage Vpass, etc.).

[0069] like Figure 2 As shown, the memory cell array 110 includes m blocks BLK0, BLK1, ..., BLKm-1. Multiple NAND string NUs are formed within each block. Each NAND string NU includes multiple memory cells (MC0 to MC31) connected in series, a bit-line select transistor TR1, and a source-line select transistor TR2. The NAND string NU can be a two-dimensional structure formed on the substrate surface or a three-dimensional structure formed vertically from the substrate surface. Furthermore, the memory cells can store binary data or multi-valued data.

[0070] Bit-line select transistor TR1 is connected to a corresponding bit line, and source-line select transistor TR2 is connected to each NAND string NU via a common source line SL. The gates of multiple memory cells in the row direction are connected to the corresponding word lines WL0 to WL31 in a common manner. The gate of bit-line select transistor TR1 is connected to the select gate line SGD, and the gate of source-line select transistor TR2 is connected to the select gate line SGS. The word lines WL0 to WL31, select gate line SGD, and select gate line SGS of each block are connected to the drive circuit 156 via block select transistor 154. Bit lines BL0 to BLn-1 extending along the column direction are connected to each block in a common manner, with one end connected to the page buffer / sensing circuit 160 via bit line select circuit 190. Bit line select circuit 190 selects an even-numbered bit line BLe or an odd-numbered bit line BLo, and connects the selected bit line BLe / bit line BLo to the page buffer / sensing circuit 160.

[0071] The word line selection / driving circuit 150 includes a block selection circuit 152, a block selection transistor 154, and a driving circuit 156. The block selection circuit 152 supplies a block selection signal BSEL, used to select a block based on row address information Ax, to each block selection transistor 154. For example, when selecting block BLK0, the block selection transistor 154 is turned on by the activated block selection signal BSEL; for other blocks, the block selection transistor 154 is turned off by the inactive block selection signal BSEL. The voltage level of the activated block selection signal BSEL is controlled by a voltage generated by the internal voltage generation circuit 180.

[0072] The driving circuit 156 drives the select gate line SGD / select gate SGS line and word lines WL0 to WL31 based on the voltage supplied from the internal voltage generation circuit 180. The select gate line SGD / select gate line SGS and word lines WL0 to WL31 are connected to the bit line-side select transistor TR1, the source line-side select transistor TR2, and the memory cells MC0 to MC31 of the selected block via the activated block select transistor 154.

[0073] During the read operation, a voltage (e.g., 0V) is applied to the select word line, a read pass voltage (e.g., 4.5V) is applied to the non-select word line, an H-level voltage (e.g., 4.5V) is applied to the select gate line SGD / select gate line SGS, and 0V is applied to the source line SL. During the programming operation, a high programming voltage Vpgm (e.g., 15V–20V) is applied to the select word line, a programming pass voltage (e.g., 10V) is applied to the non-select word line, an H-level voltage is applied to the select gate line SGD, and an L-level voltage is applied to the select gate line SGS. During the erase operation, 0V is applied to the select word line within the selected block, and an L-level voltage is applied to the select gate line SGD / select gate line SGS.

[0074] The drive circuit 156 also includes a short-circuit circuit 156A and a discharge circuit 156B connected to word lines WL0 to WL31. The short-circuit circuit 156A and discharge circuit 156B operate during programming verification in high-speed programming under low-power / high-speed programming mode. After programming and before programming verification begins, the short-circuit circuit 156A disconnects the select word line and the non-select word line from the internal voltage generation circuit 180, short-circuiting the select word line (which holds the programming voltage) and the non-select word line (which holds the programming pass voltage), allowing the select word line and the non-select word line to share the same voltage.

[0075] The discharge circuit 156B discharges the charge on the select word lines and non-select word lines to the discharge node by electrically connecting one or more non-select word lines shorted by the short-circuit circuit 156A to a discharge node at a certain potential (e.g., an external power supply voltage of 3.3V ExVDD). This maintains a certain voltage on the select word lines and non-select word lines. This certain voltage is adjusted based on the discharge time of the discharge circuit 156B or the number of word lines discharged. Subsequently, the select word lines and non-select word lines are connected to the internal voltage generation circuit 180, with the select word lines driven by the verification readout voltage and the non-select word lines driven by the readout pass voltage. The short-circuit circuit 156A and the discharge circuit 156B can reuse the power supplied to the select word lines and non-select word lines during programming during verification readout, thereby achieving power saving during programming operations. Details of the operation of the short-circuit circuit 156A and the discharge circuit 156B will be described later.

[0076] The controller 140 includes a microcontroller or state machine containing read-only memory (ROM) / random access memory (RAM) and controls read operations, programming operations, erase operations, etc. In one embodiment, the programming operation has a normal programming mode and a low-power / high-speed programming mode. The controller 140 executes the normal programming mode during periods when relatively high power consumption is allowed, and executes the low-power / high-speed programming mode during periods when power consumption is suppressed.

[0077] Next, the programming operation of the NAND flash memory 100 in this embodiment will be described. The controller 140 selects a low-power / high-speed programming mode or a standard programming mode based on externally input instructions or control signals, and executes programming in the selected mode. For example, an IoT device equipped with NAND flash memory monitors the remaining battery level, the operating status of the IoT device, or the power generation status of solar power, and supplies instructions or control signals to the controller 140 based on these monitoring results.

[0078] In another embodiment, the controller 140 can autonomously determine the power condition and select a low-power / high-speed programming mode or a normal programming mode. For example, the controller 140 includes a timer that measures time and selects the low-power / high-speed programming mode or the normal programming mode based on its measurement results.

[0079] Next, the low-power / high-speed programming mode of this embodiment will be described. (Refer to...) Figure 3 The low-power / high-speed programming mode includes functions such as block management S10, high-speed programming S20, and write-back S30.

[0080] Figure 4 This is the block management (S10) operation flow. The controller 140 performs block management when programming instructions are input from the outside or at any other time. First, the controller 140 determines the write-back block (S100) where data should be ultimately stored based on the programming instructions. The write-back block is a block used to ultimately store data temporarily written through high-speed programming, and this block is an erased block.

[0081] The controller 140 also determines two high-speed programming blocks (S110). These high-speed programming blocks are blocks used for temporary data storage via high-speed programming; these blocks are erased blocks. When programming data on the selection page of a high-speed programming block, the controller 140 maintains the relationship between the input address and the address of the high-speed programming block.

[0082] Furthermore, block management performs garbage collection to determine whether a block has been used for write-back or high-speed programming, or wear leveling to average the number of times a block has been rewritten (S120).

[0083] Figure 5This example illustrates the allocation of write-back blocks and high-speed programming blocks. Here, it's assumed that blocks BLK10 and BLK11 are already used, while blocks BLK12 through BLK17 are unused (erasetrated), and blocks are used sequentially starting from the newest address. In this case, controller 140 allocates block BLK12 as a write-back block and allocates two blocks, BLK13 and BLK14, as high-speed programming blocks. The write-back blocks and high-speed programming blocks may not be allocated as shown in the example. Figure 5 As shown, continuous blocks can be allocated as discontinuous blocks according to loss balance.

[0084] Next, high-speed programming (S20) will be explained. (Refer to...) Figure 6 When programming instructions, addresses, or data are input from the outside, the controller 140 responds by setting the data of the page to be programmed in the page buffer / sensing circuit 160 (S200).

[0085] Next, the controller 140 selects the even-numbered bit lines of the page buffer / sensing circuit 160 via the bit line selection circuit 190, and selects the even-numbered word lines of the high-speed programming block (hereinafter referred to as even pages) via the word line selection / drive circuit 150, and high-speed programs half a page of even-numbered data on the selected even-numbered page (S210). Next, the controller 140 selects the odd-numbered bit lines of the page buffer / sensing circuit 160 via the bit line selection circuit 190, and selects the odd-numbered word lines of the high-speed programming block (hereinafter referred to as odd pages) via the word line selection / drive circuit 150, and high-speed programs half a page of odd-numbered data on the selected odd-numbered page (S220). Here, an example is shown where programming is initially performed on even pages and then on odd pages; programming can also be performed initially on odd pages and then on even pages.

[0086] Here, high-speed programming refers to programming that requires less power and takes less time than normal programming. In one embodiment, high-speed programming is configured such that the programming pulse height (programming voltage) is lower and the programming pulse width (programming time) is longer than in normal programming. These settings ensure that fewer ISPP-based programming pulses are applied compared to normal programming. For example, the ISPP-based programming voltage is 0.5V lower than in normal programming, and the programming pulse width is set to twice that of normal programming. The programming pulse width and programming voltage are adjusted such that, for example, programming verification of all memory cells passes after two ISPP-based programming pulses are applied.

[0087] Furthermore, in high-speed programming, half a page of data is programmed on even-numbered bit lines of even-numbered pages and half a page of data on odd-numbered bit lines of odd-numbered pages, while suppressing coupling between bit lines, thus ensuring sufficient read margin for the high-speed programmed memory cells. Therefore, high-speed programmed memory cells can guarantee data retention for a certain period (e.g., 24 hours).

[0088] Figure 7 An example of high-speed programming is shown. For ease of explanation, assume a block consists of 8 pages (P0 to P7). When programming instructions, addresses, and data are input from the outside, in response, the data to be programmed for one page is set in the page buffer / sensing circuit 160. Then, the even-numbered bits of the page buffer / sensing circuit 160 are selected, and the selected half-page data is high-speed programmed to the even-numbered page P0 of block BLK13. Subsequently, the odd-numbered bits of the page buffer / sensing circuit 160 are selected, and the selected half-page data is high-speed programmed to the odd-numbered page P1 of block BLK13.

[0089] When the next programming instruction is input from the outside, the controller 140 performs high-speed programming of half a page's even-numbered data bits on even-numbered page P2 of block BLK13, and then performs high-speed programming of half a page's odd-numbered data bits on odd-numbered page P3 of block BLK13. After using all pages of block BLK13 in high-speed programming, the controller 140 then performs high-speed programming on pages of block BLK14.

[0090] Figure 7 An example is shown where all pages P0 to P7 of blocks BLK13 and BLK14 are high-speed programmed. Even-numbered and odd-numbered data bits are alternately programmed in blocks BLK13 and BLK14, and a checkerboard pattern (including squares or grids) is programmed within the blocks. In the checkerboard pattern, memory cells adjacent to programmed memory cells are not programmed, thus suppressing coupling between memory cells. Furthermore, the controller 140 maintains the relationship between externally input addresses and the page addresses of the high-speed programmed block BLK13. This relationship is utilized in the write-back process described later.

[0091] In the high-speed programming of the chessboard pattern, an example is shown where programming proceeds sequentially from a new page address (P0 (even), P1 (odd), P2 (even), P3 (odd)). However, this is just one example, and other orders are possible. For instance, programming could proceed from page P0 (even), page P3 (odd), page P4 (even), page P7 (odd), and so on, followed by page P1 (odd), page P2 (even), page P5 (odd), page P6 (even), and so on.

[0092] Figure 8This is a diagram of the voltage waveforms for each part during high-speed programming. VWW is the programming voltage generated by the internal voltage generation circuit 180. WL-SL are the select word lines, and WL-inh1 and WL-inh2 are the non-select word lines. For example, in... Figure 7 In block BLK13, when programming even-numbered pages P0, the select word line WL-SL corresponds to page P0, and the non-select word lines WL-inh1 and WL-inh2 correspond to pages P1 to P7. The non-select word line WL-inh2 is one or more non-select word lines electrically coupled to a discharge node with a positive potential before programming verification; the remaining non-select word lines are non-select word lines WL-inh1.

[0093] Between time t1 and time t2, a programming voltage Vpgm1 generated by the internal voltage generation circuit 180 is applied to the select word lines WL-SL, and a programming pass voltage Vpass (e.g., 10V) is applied to the non-select word lines WL-inh1 and WL-inh2.

[0094] At time t2, the programming voltage Vpgm1 decreases. Simultaneously, all word lines are disconnected from the internal voltage generation circuit 180, becoming floating. That is, the programming voltage Vpgm1 is maintained on the selected word lines WL-SL, while the pass voltage Vpass is maintained on the non-selected word lines WL-inh1 and WL-inh2.

[0095] Between time t2 and time t3, short-circuit circuit 156A short-circuits all word lines, namely the select word lines WL-SL and the non-select word lines WL-inh1 and WL-inh2. As a result, the programming voltage Vpgm1 and the pass voltage Vpass are shared by all word lines. For example, if the select word line WL-SL is maintained at 18V as the programming voltage Vpgm1, and the remaining seven non-select word lines WL-inh1 and WL-inh2 are maintained at 10V as the pass voltage Vpass, then when all word lines are short-circuited, a voltage of approximately 11V ((70V+18V) / 8) is maintained on each word line.

[0096] During time t4-t5, discharge circuit 156B electrically connects the non-selected word lines WL-inh2 to a discharge node with a positive potential, discharging a portion of the charge held by all word lines to the discharge node. The discharge node is a potential lower than the shared voltage across the short circuit, such as the external power supply voltage ExVDD (e.g., 3.3V). By appropriately selecting the discharge time (t4-t5) to the discharge node and the discharge resistor (the number of non-selected word lines WL-inh2), the voltage of all word lines after discharge is adjusted to the desired magnitude. For example, all word lines after discharge are adjusted to the same voltage as the read-through voltage Vpass (4.5V) verified by the readout.

[0097] Between time t6 and time t7, a read-through voltage generated by the internal voltage generation circuit 180 is applied to the non-select word lines WL-inh1 and WL-inh2, and a read-out voltage is applied to the select word line WL-SL for programming verification. The discharged voltage is maintained on the non-select word lines WL-inh1 and WL-inh2, thus reducing the voltage supply from the internal voltage generation circuit 180.

[0098] Between time t8 and time t9, in order to program the memory cells that have failed verification, a programming voltage Vpgm2, which is one step higher, is applied to the select word lines WL-SL, and a programming pass voltage Vpass is applied to the non-select word lines WL-inh1 and WL-inh2. High-speed programming is completed by applying two programming pulses.

[0099] Before performing programming verification, the programming voltage Vpgm / pass voltage Vpass used during programming is used for programming verification, thus reducing power consumption during verification.

[0100] Next, refer to Figure 9 The process Figure 3 The details of the write-back (S30) will be explained. In the case of high-speed programming (S300), the controller 140 monitors the end of the retention guarantee period for the high-speed programmed memory unit (step S310). The method for monitoring the end of the retention guarantee period is not particularly limited; for example, the controller 140 can know the timing of the end of the retention guarantee period through instructions or control signals from an external host computer. Alternatively, the controller 140 itself can know the timing of the end of the retention guarantee period from a timer or similar means for managing time.

[0101] Before the end of the warranty period, the controller 140 reads the data written to the page in the high-speed programming block and programs the read data to the page in the write-back block BLK12 (S320). The programming at this time is normal page programming, and the programming voltage is slightly higher than that in high-speed programming, so the number of times the programming pulse based on ISPP is applied is not limited to two.

[0102] In a preferred embodiment, the controller 140 performs write-back during periods of unrestricted power use (e.g., periods when relatively large amounts of power are supplied to IoT devices, periods when power-saving mode is disabled, or idle periods). The controller 140 may perform write-back in response to external commands or control signals, and the controller 140 may also manage the timing of write-back using timers or similar mechanisms.

[0103] Write-back can be done as follows Figure 7It can be implemented after using all pages of the two high-speed programming blocks BLK13 and BLK14 as shown, or it can be implemented after using a portion of the pages of blocks BLK13 and BLK14.

[0104] Figure 10 It shows in Figure 7 The example shown illustrates a write-back process implemented after programming all pages of blocks BLK13 and BLK14. Here, it is assumed that high-speed programming proceeds sequentially from page P0 to page P7.

[0105] The controller 140 reads the data of the even-numbered page P0 of block BLK13 and sets the read data to the even-numbered bits of the page buffer / sensing circuit 160. Then, it reads the data of the odd-numbered page P1 of block BLK13 and sets the read data to the odd-numbered bits of the page buffer / sensing circuit 160. Finally, it programs the data of one page set in the page buffer / sensing circuit 160 to page P0 of block BLK12.

[0106] The controller 140 identifies whether there are any pages that have not been written back in the high-speed programming block (S330). If so, it reads the data of even-numbered page P2 of block BLK13 and sets the read data to the even-numbered page of the page buffer / sensing circuit 160. Then, it reads the data of odd-numbered page P3 of block BLK13 and sets the read data to the odd-numbered bit of the page buffer / sensing circuit 160. Next, it programs the data of one page set in the page buffer / sensing circuit 160 to page P1 of block BLK12. Subsequently, the write-back process is performed in the same way up to page P7 of block BLK14. Finally, the data of each page of both blocks BLK13 and BLK14 is stored in block BLK12. The controller 140 maintains the relationship between the address input from the outside and the address of block BLK12.

[0107] When the write-back is complete (S330), the controller 140 erases the high-speed programming block (S340) to prepare for the next high-speed programming. Figure 3 When the block management S10 shown is finished writing back, as follows: Figure 11 As shown, block BLK13 is allocated to the write-back block, and blocks BLK14 and BLK15 are allocated to the high-speed programming block. In a preferred embodiment, when high-speed programming is performed on the high-speed programming block BLK14, the controller 140 programs data to memory cells that were not used in the previous high-speed programming. That is, high-speed programming is performed on the odd-numbered bits of even-numbered pages P0, P2, P4, and P6 of block BLK14.

[0108] When the high-speed programming of blocks BLK14 and BLK15 is completed, a write-back of blocks BLK14 and BLK15 is performed, erasing blocks BLK14 and BLK15. Block BLK14 is allocated to the next write-back block, and blocks BLK15 and BLK16 are allocated to high-speed programming blocks. During high-speed programming of block BLK15, the even-numbered bits of even-numbered pages P0, P2, P4, and P6, which were unused in the previous high-speed programming, and the odd-numbered bits of odd-numbered pages P1, P3, P5, and P7 are selected as the memory units to be programmed.

[0109] This high-speed programming method evens out the programming frequency or stress caused by programming of the storage cells within the block, improves the reliability of high-speed programming, and ensures sufficient read margin for the storage cells.

[0110] According to this embodiment, a low-power / high-speed programming mode is set in the NAND flash memory to reduce power consumption during programming operations. Therefore, even when electronic devices such as IoT devices are in power-saving mode, power-saving programming can be performed accordingly. In addition, during periods where relatively high power consumption is permissible, data programmed using low-power / high-speed programming is written back using normal programming, thereby allowing programming to be performed according to the power status of electronic devices such as IoT devices.

[0111] In the embodiment described, an example is shown of allocating blocks with contiguous block addresses to write-back blocks and high-speed programming blocks. However, this is just one example. Write-back blocks and high-speed programming blocks do not necessarily need to have contiguous addresses and can be allocated blocks with arbitrary addresses.

[0112] Additionally, in the embodiments described, such as Figure 7 As shown, high-speed programming was performed on the even-numbered bits of even-numbered pages P0, P2, P4, and P6 of blocks BLK13 and BLK14, and on the odd-numbered bits of odd-numbered pages P1, P3, P5, and P7. However, it is not limited to this; high-speed programming can also be performed on the odd-numbered bits of even-numbered pages P0, P2, P4, and P6 of blocks BLK13 and BLK14, and on the even-numbered bits of odd-numbered pages P1, P3, P5, and P7.

[0113] Furthermore, in the embodiments described, such as Figure 7The diagram illustrates an example of high-speed programming on even and odd pages of block BLK13, followed by high-speed programming on even and odd pages of block BLK14 after all pages of block BLK13 have been used. However, this is not a limitation; it is also possible to high-speed program half a page of data on either an even or odd page of block BLK13, and then high-speed program half a page of data on either an odd or even page of block BLK14. In this case, the write-back reads data from either an even or odd page of block BLK13 and an odd or even page of block BLK14, and programs the read page of data into the selected page of the write-back block.

[0114] Furthermore, in the described embodiment, an example of allocating two blocks for high-speed programming is shown, but this is not a limitation; there may be one or more high-speed programming blocks. Data stored in one or more high-speed programming blocks is written back to the write-back block during idle periods when power-saving mode is disabled or during periods when relatively high power is supplied. Additionally, in the described embodiment, an example of allocating one block for write-back is shown, but this is not a limitation; multiple blocks may be allocated to write-back. In this case, data read from the high-speed programming block is programmed into the selected write-back block.

[0115] Preferred embodiments of the present invention have been described in detail, but the present invention is not limited to specific embodiments and various modifications and alterations can be made within the scope of the spirit of the invention as described in the claims.

Claims

1. A programming method, specifically a programming method for NAND flash memory, comprising: The steps of assigning at least one block to a high-speed programming block and at least one block to a storage block for final data storage; In response to programming instructions input from an external source, the step of high-speed programming 1 / 2 page of data into each of the two selected pages of the high-speed programming block; as well as The steps include reading data from two selected pages of the high-speed programming block and typically programming the read data into the storage block. In this high-speed programming step, compared to the normal programming step, the programming pulse voltage is lower and the number of programming pulses applied due to verification failure is less.

2. The programming method according to claim 1, wherein, The high-speed programming steps include: during programming verification, short-circuiting the select word line that holds the programming voltage and the non-select word line that holds the programming pass voltage, so that the short-circuited word lines share a certain potential, applying a verification readout voltage to the select word line, and applying a readout pass voltage to the non-select word line.

3. The programming method according to claim 2, wherein, The high-speed programming steps also include discharging one or more short-circuited word lines to generate the specified potential.

4. The programming method according to claim 1, wherein, The high-speed programming step is performed during periods when power consumption is limited or in power-saving mode, while the normal programming step is performed during periods when power consumption is unrestricted or when power-saving mode is disabled.

5. The programming method according to claim 1, wherein, The high-speed programming step involves programming 1 / 2 page of data into the even-numbered and odd-numbered pages of the high-speed programming block, respectively.

6. The programming method according to claim 1, wherein, The high-speed programming step involves programming the high-speed programming into a chessboard pattern using blocks.

7. The programming method according to claim 6, wherein, The chessboard pattern is generated by programming the even-numbered or odd-numbered positions on even-numbered pages and the odd-numbered or even-numbered positions on odd-numbered pages.

8. The programming method according to claim 5, wherein, The high-speed programming steps include a programming loop in the order of pages P0, P3, P4, P7, ... of the high-speed programming block, and a programming loop in the order of pages P1, P2, P5, P6, ...

9. The programming method according to claim 1, wherein, The programming method includes the step of erasing the high-speed programming block. When an erased block is reassigned to a high-speed programming block, the high-speed programming step is performed in a different memory cell than the one used in the previous high-speed programming.

10. A semiconductor device, comprising: NAND-type memory cell array; as well as The programming unit performs programming on the selection page of the memory cell array. The programming component includes a normal programming mode and a high-speed programming mode. The high-speed programming mode includes: At least one block is assigned to the high-speed programming block, and at least one block is assigned to the storage block used for final data storage; In response to programming instructions input from an external source, 1 / 2 page of data is high-speed programmed into each of the two selected pages in the high-speed programming block; and Read the data from the two selected pages of the high-speed programming block, and then typically program the read data into the storage block. In this high-speed programming mode, compared to the normal programming mode, the programming pulse voltage is lower and the number of programming pulses applied due to verification failures is less.

11. The semiconductor device according to claim 10, wherein, The high-speed programming mode includes: during programming verification, short-circuiting the select word line that holds the programming voltage and the non-select word line that holds the programming pass voltage, so that the short-circuited word lines share a certain potential, applying a verification readout voltage to the select word line and applying a readout pass voltage to the non-select word line.

12. The semiconductor device according to claim 11, wherein, The high-speed programming mode also discharges one or more short-circuited word lines to generate the specified potential through the discharge.

13. The semiconductor device according to claim 10, wherein, The high-speed programming mode is implemented during periods when power consumption is limited or in power-saving mode, while the normal programming mode is implemented during periods when power consumption is unrestricted or when power-saving mode is disabled.

Images