Semiconductor device and method of forming the same

Abstract

A semiconductor device and a method of forming the same, the method comprising: providing a substrate having a first fin and a second fin adjacent to each other on the substrate; forming a first gate structure across the first fin on the substrate, the first gate structure covering a top surface of a portion of a sidewall of the first fin; forming a second gate structure across the second fin on the substrate, the second gate structure covering a top surface of a portion of a sidewall of the second fin; forming a first sacrificial layer on a top and a sidewall of the first fin on both sides of the first gate structure after forming the first gate structure and the second gate structure; forming a first protective layer on a sidewall of the first sacrificial layer; removing the first sacrificial layer and the first fin on both sides of the first gate structure to form a first recess, the first recess exposing a sidewall of the first protective layer; forming a first doped layer in the first recess; and forming a second doped layer in the second fin on both sides of the second gate structure. The method improves the performance of the semiconductor device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor device and a method for forming the same. Background Technology

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are evolving towards higher component density and higher integration. Transistors, as the most basic semiconductor devices, are currently widely used. However, traditional planar devices have weakened control over channel current, resulting in short-channel effects that lead to leakage current and ultimately affect the electrical performance of semiconductor devices.

[0003] To overcome the short-channel effect of transistors and suppress leakage current, the prior art has proposed the FinFET (Fin Field-Effect Transistor). The FinFET is a common multi-gate device. The structure of the FinFET includes: a fin and an isolation layer located on the surface of a semiconductor substrate, the isolation layer covering part of the sidewall of the fin, and the surface of the isolation layer being lower than the top of the fin; a gate structure located on the surface of the isolation layer, as well as the top and sidewall surfaces of the fin; and source doped layers and drain doped layers located in the fin on both sides of the gate structure.

[0004] However, as the size of semiconductor devices decreases, the distance between transistors decreases, and the source or drain doped layers of adjacent transistors are prone to short circuits, resulting in poor performance of the formed semiconductor devices. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a semiconductor device and a method for forming the same, so as to improve the performance of the semiconductor device.

[0006] To address the aforementioned technical problems, the present invention provides a method for forming a semiconductor device, comprising: providing a substrate having adjacent first fins and second fins; forming a first gate structure across the first fins on the substrate, the first gate structure covering a portion of the sidewalls and top surface of the first fins; forming a second gate structure across the second fins on the substrate, the second gate structure covering a portion of the sidewalls and top surface of the second fins; after forming the first gate structure and the second gate structure, forming a first sacrificial layer on the top and sidewalls of the first fins on both sides of the first gate structure; forming a first protective layer on the sidewalls of the first sacrificial layer; removing the first sacrificial layer and the first fins on both sides of the first gate structure, forming a first groove in the first fin, the first groove exposing the sidewalls of the first protective layer; forming a first doped layer in the first groove; and forming a second doped layer in the second fins on both sides of the second gate structure.

[0007] Optionally, the material of the first sacrificial layer includes: SiGe, Si, or SiC.

[0008] Optionally, when the material of the first sacrificial layer is SiGe or Si, the method for forming the first sacrificial layer further includes: oxidizing the first sacrificial layer to form a first oxide layer; removing the first oxide layer and the first fin on both sides of the first gate structure, and forming a first groove in the first fin.

[0009] Optionally, the method for forming the second doped layer includes: forming a second sacrificial layer on the top and sidewalls of the second fins on both sides of the second gate structure; forming a second protective layer on the sidewalls of the second sacrificial layer; removing the second sacrificial layer and the second fins on both sides of the second gate structure to form a second groove, the second groove exposing the sidewalls of the second protective layer; and forming a second doped layer in the second groove.

[0010] Optionally, the material of the second sacrificial layer includes SiGe, Si, or SiC.

[0011] Optionally, when the material of the second sacrificial layer is SiGe or Si, the method for forming the second sacrificial layer includes: oxidizing the second sacrificial layer to form a second oxide layer; removing the second oxide layer and the second fin on both sides of the second gate structure to form a second groove.

[0012] Optionally, a second sacrificial layer is formed after the first sacrificial layer is formed; or, the first sacrificial layer is formed after the second sacrificial layer is formed.

[0013] Optionally, the second sacrificial layer is formed during the formation of the first sacrificial layer.

[0014] Optionally, the substrate includes a first region and a second region, the first fin is located in the first region of the substrate, and the second fin is located in the second region of the substrate; the substrate further includes: an isolation layer, the isolation layer covering a portion of the sidewall of the first fin and a portion of the sidewall of the second fin; the first gate structure and the second gate structure are also located on the isolation layer; the first sacrificial layer and the second sacrificial layer are also located on the isolation layer.

[0015] Optionally, the first protective layer is formed after the first sacrificial layer and the second sacrificial layer are formed.

[0016] Optionally, the method for forming the first protective layer includes: forming an initial first protective layer on a first fin and a second fin, the initial first protective layer covering the top and sidewalls of a first sacrificial layer, the top and sidewalls of a second sacrificial layer, a first gate structure, a second gate structure, and the surface of an isolation layer; forming a first mask layer on the surface of the initial first protective layer, the first mask layer covering the surface of the initial first protective layer in the second region; after forming the first mask layer, etching back the initial first protective layer exposed by the first mask layer until the surface of the first sacrificial layer and the surface of the isolation layer in the first region are exposed; forming a first protective layer on the sidewall of the first fin, the first protective layer covering the sidewall of the first sacrificial layer; after etching back the initial first protective layer exposed by the first mask layer, removing the first mask layer.

[0017] Optionally, it also includes: after forming the first doped layer, forming a second protective layer, the second protective layer further covering the surface of the second isolation layer.

[0018] Optionally, the method for forming the second protective layer includes: forming an initial first protective layer on the surface of the first doped layer and the second fin, wherein the initial second protective layer further covers the sidewall surface of the first protective layer and the surface of the isolation layer in the first region; removing the initial second protective layer and the initial first protective layer on the top of the second sacrificial layer to expose the top surface of the second sacrificial layer, and such that the initial first protective layer on the surface of the second sacrificial layer is formed as the second protective layer.

[0019] Optionally, the method for forming the second groove includes: removing the second sacrificial layer to form an initial second groove in the second region, the initial second groove exposing the second fins and the second protective layer sidewalls on both sides of the second gate structure; after forming the initial second groove, removing the second fins exposed by the initial second groove to form the second groove.

[0020] Optionally, the height of the first doped layer is greater than the height of the first protective layer; the height difference between the first doped layer and the first protective layer is 1 nm to 15 nm.

[0021] Optionally, the first doped layer covers the top surface of the first protective layer.

[0022] Optionally, the height of the second doped layer is greater than the height of the second protective layer; the height difference between the second doped layer and the second protective layer is 1 nm to 8 nm.

[0023] Optionally, the second doped layer covers the top surface of the second protective layer.

[0024] Optionally, the material of the first protective layer includes: SiN, SiCN, SiBN, or SiON.

[0025] The present invention also provides a semiconductor device formed using any one of the above methods.

[0026] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0027] In the semiconductor device formation method provided by the present invention, a first protective layer is located on the sidewall of the first doped layer. The first protective layer restricts the growth of the first doped layer, making it difficult for the first doped layer to form sharp points, thereby making it less likely for the first doped layer to bridge with adjacent doped layers. Simultaneously, the first groove is formed by removing the first sacrificial layer and the first fin. The first sacrificial layer increases the volume of the first groove, and the volume of the first doped layer is correspondingly larger, resulting in a larger surface area. This leads to a higher contact resistance between the subsequently formed plug and the first doped layer, thereby improving the performance of the semiconductor device.

[0028] Furthermore, the second protective layer restricts the growth of the second doped layer, making it less likely for the second doped layer to form sharp points, thus reducing the probability of bridging between the first and second doped layers. This optimizes the performance of the semiconductor device.

[0029] Furthermore, the first doped layer covers the sidewall of the first protective layer, and the height of the first doped layer is higher than that of the first protective layer, which further increases the volume of the first doped layer, thereby better reducing contact resistance and improving the performance of the semiconductor device. Attached Figure Description

[0030] Figures 1 to 2 This is a schematic diagram of the semiconductor device fabrication process;

[0031] Figures 3 to 16 This is a schematic diagram of the semiconductor device formation process in one embodiment of the present invention. Detailed Implementation

[0032] As described in the background section, existing semiconductor devices have poor performance.

[0033] For a method of fabricating an SRAM device, please refer to [reference needed]. Figure 1 and Figure 2 , Figure 2 For along Figure 1A cross-sectional schematic diagram of the dicing line Aa includes: a substrate 100 having adjacent first fins 110 and second fins 111, and an isolation layer 101 covering a portion of the sidewalls of the first fins 110 and the second fins 111; a first gate structure 130 formed across the first fins 110 on the isolation layer; a first source / drain doped layer 150 formed in the first fins 110 on both sides of the first gate structure 130; a second gate structure 140 formed across the second fins 111 on the isolation layer; and a second source / drain doped layer 160 formed in the second fins 111 on both sides of the second gate structure 140, wherein the second source / drain doped layer 160 and the first source / drain doped layer 150 are adjacent.

[0034] However, the SRAM memory formed by the above method has poor performance. When the first gate structure is used to form a pull-up transistor, the transistor type is P-type. Due to the different growth rates of the first source / drain doped layer 150 in different crystal orientations, <111> The growth is slowest on the crystal-up direction, and the epitaxial crystal surface will stop at the (111) crystal surface, while it will continue to grow on other surfaces, thus forming a tip. Correspondingly, when the second gate structure is also used to form a pull-up transistor, the second source / drain doped layer 160 will also form a tip. As semiconductor devices develop towards high density, the distance between the transistors that make up the semiconductor device is getting smaller and smaller, and the space between the second source / drain doped layer 160 and the first source / drain doped layer 150 is getting smaller and smaller. In order to avoid bridging between the first source / drain doped layer 150 and the second source / drain doped layer, a first sidewall 121 and a second sidewall 122 are formed on the sidewalls of the first source / drain doped layer 150 and the second source / drain doped layer 160, respectively. The first sidewall 121 and the second sidewall 122 restrict the shape of the first source / drain doped layer 150 and the second source / drain doped layer 160, so that the surfaces of the first source / drain doped layer 250 and the second source / drain doped layer 160 are less likely to form tips, thus making bridging less likely.

[0035] However, due to the limitations of the first and second sidewalls, the first source / drain doped layer 150 and the second source / drain doped layer 160 have small volumes and correspondingly small surface areas. Consequently, the contact resistance between the subsequently formed plug and the first source / drain doped layer 150 or the second source / drain doped layer 160 is large, which in turn affects the performance of the formed SRAM device.

[0036] In this invention, a first sacrificial layer is formed on the first fin, a first protective layer is formed on the sidewall of the first sacrificial layer, the first sacrificial layer and the first fin are removed to form a first groove, and a first doped layer is formed in the first groove. The first doped layer is restricted by the first protective layer, making it difficult for the surface to form a sharp point, thus making it less likely to bridge with adjacent doped layers. At the same time, due to the formation of the first sacrificial layer, the volume of the first groove is increased, resulting in a larger volume of the first doped layer, reducing the contact resistance, thereby improving the performance of the semiconductor device.

[0037] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0038] Figures 3 to 16 This is a schematic diagram of the semiconductor device formation process in one embodiment of the present invention.

[0039] Please refer to Figure 3 and Figure 4 , Figure 4 The corresponding area I in the middle is Figure 3 Cross-sectional view along the M-M1 direction, Figure 4 The corresponding area II is Figure 3 A cross-sectional view along the M2-M3 direction provides a semiconductor substrate 200.

[0040] The semiconductor substrate 200 has adjacent first fin 211, second fin 212 and isolation layer 201, the isolation layer 201 covering part of the sidewalls of the first fin 211 and the second fin 212.

[0041] The semiconductor substrate 200 includes region I and region II, the first fin 211 is located in region I of the semiconductor substrate 200, and the second fin 212 is located in region II of the semiconductor substrate 200.

[0042] In this embodiment, the formed device is an SRAM device. The first fin 211 is used to form the pull-up transistor of the SRAM device. The device type formed by the second fin 212 is different from the device type formed by the first fin 211, and is used to form the pull-down transistor of the SRAM device.

[0043] In one embodiment, the first fin 211 is used to form a pull-up transistor of the SRAM device, and the second fin 212 is used to form a pull-up transistor of the SRAM device. In another embodiment, the first fin 211 is used to form a pull-down transistor of the SRAM device, and the type of device formed by the second fin 212 may be the same as or different from the type of device formed by the first fin 211.

[0044] The semiconductor substrate 200 is made of semiconductor materials such as silicon, germanium, silicon germanide, gallium arsenide, and indium gallium arsenide, wherein the silicon material includes monocrystalline silicon, polycrystalline silicon, or amorphous silicon. The semiconductor substrate 200 can also be a semiconductor-on-insulator structure, which includes an insulator and a semiconductor material layer located on the insulator. The semiconductor material layer is made of semiconductor materials such as silicon, germanium, silicon germanide, gallium arsenide, and indium gallium arsenide.

[0045] In this embodiment, the semiconductor substrate 200 is made of single-crystal silicon.

[0046] The first fin 211 is used to form a first transistor, and the second fin 212 is used to form a second transistor. In this embodiment, the first transistor and the second transistor are adjacent. In actual manufacturing, the type of the second transistor is determined according to the desired circuit layout. In this embodiment, the first transistor is a pull-up transistor, so the first transistor type is P-type, and the second transistor is a pull-down transistor, so the second transistor type is N-type.

[0047] In this embodiment, the first fin 211 and the second fin 212 are formed by patterning the semiconductor substrate 200. In other embodiments, a fin material layer may be formed on the semiconductor substrate 200, and then the fin material layer may be patterned to form the first fin 211 and the second fin 212.

[0048] In this embodiment, the first fin 211 and the second fin 212 are made of monocrystalline silicon. In other embodiments, the first fin 211 and the second fin 212 are made of monocrystalline germanium silicon or other semiconductor materials.

[0049] In this embodiment, the method further includes forming an isolation layer 201 on the semiconductor substrate 200, the isolation layer 201 covering a portion of the sidewall surface of the first fin 211 and the second fin 212. The material of the isolation layer 201 includes silicon oxide.

[0050] Please refer to Figure 5 , Figure 5 and Figure 4 With consistent cross-sectional direction, a first gate structure 221 is formed on the semiconductor substrate 200, spanning the first fin 211 and covering part of the top surface and part of the sidewall surface of the first fin 211; a second gate structure 222 is formed on the semiconductor substrate 200, spanning the second fin 212 and covering part of the top surface and part of the sidewall surface of the second fin 212.

[0051] The first gate structure 221 includes a first gate dielectric layer (not shown) spanning the first fin 211, a first gate electrode layer (not shown) located on the first gate dielectric layer, and a first gate protective layer (not shown) located on top of the first gate electrode layer. The second gate structure 222 includes a second gate dielectric layer (not shown) spanning the second fin 212, a second gate electrode layer (not shown) located on the second gate dielectric layer, and a second gate protective layer (not shown) located on top of the second gate electrode layer. The first gate dielectric layer is located on a portion of the surface of the I-region isolation layer 201 and covers a portion of the top surface and a portion of the sidewall surface of the first fin 111. The second gate dielectric layer is located on a portion of the surface of the II-region isolation layer 201 and covers a portion of the top surface and a portion of the sidewall surface of the second fin 112.

[0052] In this embodiment, the first gate dielectric layer and the second gate dielectric layer are made of silicon oxide. In other embodiments, the first gate dielectric layer and the second gate dielectric layer are made of a high-k dielectric material (K greater than 3.9). The first gate electrode layer and the second gate electrode layer are made of polycrystalline silicon. The first gate protective layer and the second gate protective layer are made of SiN, SiCN, SiBN, or SiON.

[0053] In this embodiment, the method further includes: forming a first offset sidewall on the sidewall of the first gate structure and forming a second offset sidewall on the sidewall of the second gate structure.

[0054] The first offset sidewall protects the first gate layer sidewall, and the second offset sidewall protects the second gate layer sidewall.

[0055] After forming the first gate structure 221 and the second gate structure 222, a first sacrificial layer is formed on the top and sidewalls of the first fins 211 on both sides of the first gate structure 221. (See wall reference for the method of forming the first sacrificial layer.) Figure 6 and Figure 7 .

[0056] Please refer to Figure 6 A first sacrificial layer 202 is formed on the top and sidewall of the first fin 211 on both sides of the first gate structure 221.

[0057] The first sacrificial layer 202 is used to define the position of the subsequently formed first protective layer and increase the volume of the subsequently formed first groove so as to increase the volume of the subsequently formed first doped layer.

[0058] The material of the first sacrificial layer 202 includes SiGe, Si, or SiC. The Si material includes: monocrystalline silicon, polycrystalline silicon, doped silicon, etc.

[0059] In this embodiment, the material of the initial first sacrificial layer 202 is monocrystalline silicon.

[0060] The process for forming the first sacrificial layer 202 includes an epitaxial growth process.

[0061] In this embodiment, a second sacrificial layer 203 is formed on the top and sidewall of the second fin 212 on both sides of the second gate structure 222.

[0062] The material of the second sacrificial layer 203 includes SiGe, Si, or SiC. The Si material includes: monocrystalline silicon, polycrystalline silicon, doped silicon, etc.

[0063] In this embodiment, the material of the second sacrificial layer 203 is monocrystalline silicon.

[0064] The second sacrificial layer 203 is used to define the position of the subsequently formed second protective layer and increase the volume of the subsequently formed second groove so as to increase the volume of the subsequently formed second doped layer.

[0065] In this embodiment, a second sacrificial layer 203 is formed during the formation of the first sacrificial layer 202.

[0066] In other embodiments, the first sacrificial layer and the second sacrificial layer are not formed simultaneously.

[0067] Please refer to Figure 7 The first sacrificial layer 202 is oxidized to form the first oxide layer 213.

[0068] In this embodiment, the first oxide layer 213 is used to increase the volume of the subsequently formed first groove, so as to increase the volume of the subsequently formed first doped layer.

[0069] In this embodiment, the material of the first oxide layer 213 is silicon oxide.

[0070] In this embodiment, the method further includes: oxidizing the second sacrificial layer 203 to form a second oxide layer 214.

[0071] The material of the second oxide layer 214 includes silicon oxide.

[0072] The second oxide layer 214 is formed during the formation of the first oxide layer 213.

[0073] In other embodiments, after the first oxide layer 213 is formed, a second oxide layer 214 is formed; after the second oxide layer 214 is formed, the first oxide layer 213 is formed.

[0074] The first sacrificial layer 203 is oxidized to form a first oxide layer 213, so that the material of the first oxide layer 213 is different from the material of the first fin 201. When the first oxide layer 213 and the first fin are removed to form the first groove, the depth and morphology of the first groove are easy to control.

[0075] In other embodiments, no oxidation treatment is performed, and no first oxide layer or second oxide layer is formed.

[0076] Please refer to Figure 8 An initial first protective layer 230 is formed on the first fin portion 211 and the second fin portion 212, the initial first protective layer 230 covering the top and sidewalls of the first sacrificial layer.

[0077] In this example, the first sacrificial layer 203 is oxidized to form a first oxide layer 213, and the initial first protective layer 230 covers the top and sidewalls of the first oxide layer 213.

[0078] In this embodiment, the initial first protective layer 230 also covers the top and sidewalls of the second oxide layer 214, the first gate structure 221, the second gate structure 222, and the surface of the isolation layer 201.

[0079] The initial first protective layer 230 provides a material layer for the subsequent formation of the first and second protective layers.

[0080] The process for forming the initial first protective layer 230 includes one or more combinations of chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

[0081] Please refer to Figure 9 The initial first protective layer 230 of the first region I is etched back until the surface of the first oxide layer 213 is exposed, and the first protective layer 231 is formed on the sidewall of the first oxide layer 213.

[0082] Specifically, a first mask layer (not shown) is formed on the surface of the initial first protective layer 230, and the first mask layer covers the surface of the initial first protective layer 230 in the second region II; after the first mask layer is formed, the initial first protective layer 230 exposed by the first mask layer is etched back until the surface of the first oxide layer 213 and the surface of the isolation layer 201 in the first region I are exposed, and a first protective layer 231 is formed on the sidewall of the first fin 211, and the first protective layer 231 covers the sidewall of the first oxide layer 213.

[0083] The first protective layer 231 is used to limit the shape of the subsequent first doped layer.

[0084] In this embodiment, the method further includes: after etching back the initial first protective layer exposed by the first mask layer, removing the first mask layer.

[0085] The material of the first mask layer is photoresist. The process for removing the first mask layer is an ashing process.

[0086] The material of the first protective layer 213 includes: SiN, SiCN, SiBN or SiON.

[0087] In this embodiment, the first protective layer 213 is made of silicon nitride.

[0088] The material of the first protective layer 231 is different from the material of the first oxide layer 213.

[0089] The material of the first protective layer 231 is different from that of the first oxide layer 213, which ensures that the shape of the first protective layer 231 is not affected when the first oxide layer 213 is removed in the future, thereby ensuring that the first doped layer is not prone to forming sharp points.

[0090] Please refer to Figure 10The first oxide layer 213 and the first fin 211 on both sides of the first gate structure 221 are removed to form a first groove 204, and the first groove 204 exposes the sidewall of the first protective layer 231.

[0091] In this embodiment, after removing the first oxide layer 213, the first fin portion 211 is removed to form the first groove 204.

[0092] In one embodiment, the first sacrificial layer and the first fin are removed to form a first groove. The removal of the first sacrificial layer and the first fin can be performed in the same process or in two separate steps.

[0093] The first groove 204 provides space for the subsequent formation of the first doped layer. The volume of the first groove is determined by the position of the first protective layer.

[0094] The process for removing the first oxide layer 213 and the first fin 211 on both sides of the first gate structure 221 includes: a dry etching process or a wet etching process.

[0095] In this embodiment, the process of removing the first oxide layer 213 and the first fin 211 on both sides of the first gate structure 221 is a dry etching process.

[0096] Please refer to Figure 11 A first doped layer 251 is formed in the first groove 204.

[0097] The process for forming the first doped layer 251 is an epitaxial growth process. During the epitaxial growth process to form the first doped layer 251, in-situ doping of the first doped layer 251 is also included, wherein the doping ions are first ions.

[0098] When the first gate structure 221 is used to form a P-type device, the material of the first doped layer 251 includes silicon germanium doped with first ions, the first ions being of P-type conductivity, and the first ions including boron ions and BF ions. 2- The material of the first doped layer 251 includes silicon doped with a first ion, the first ion having an N-type conductivity type, and the first ion including phosphorus ions or arsenic ions.

[0099] In this embodiment, the first transistor is P-type, the first doped layer 251 is made of silicon-germanium doped with a first ion, which is a boron ion. The atomic percentage of germanium in the silicon-germanium is 35% to 80%, and the concentration of the boron ion is 1.0E20 atm / cm³. 3 ~5.0E21atm / cm 3 .

[0100] The shape of the first doped layer 251 is limited by the first protective layer 231 on the sidewall of the first groove 204 and is formed in the first groove 204. In order to make the volume of the first doped layer 251 as large as possible, the height of the first doped layer 251 along the normal direction of the semiconductor substrate is as high as possible.

[0101] The height of the first doped layer 251 is greater than the height of the first protective layer 231.

[0102] In this embodiment, the height difference between the first doped layer and the first protective layer is 1nm to 15nm.

[0103] To further increase the volume of the first doped layer 251, the first doped layer 251 covers the top surface of the first protective layer 231 along a direction parallel to the plane of the semiconductor substrate.

[0104] The first protective layer 231 restricts the growth of the first doped layer 251, making it less likely for the first doped layer 251 to form sharp points, thus reducing the likelihood of bridging between the first doped layer 251 and adjacent doped layers. Simultaneously, the first groove 204 is formed by removing the first oxide layer 213 and the first fin 211. The increased volume of the first oxide layer 231 leads to a correspondingly larger volume of the first doped layer 251, resulting in a larger surface area and consequently, a higher contact resistance between the subsequently formed plug and the first doped layer 251. Furthermore, a larger volume of the first doped layer 251 results in greater channel stress. In summary, the performance of the semiconductor device is improved.

[0105] Next, a second doped layer is formed in the second fin 212 on both sides of the second gate structure 222.

[0106] Please refer to Figure 12 An initial second protective layer 240 is formed on the surface of the first doped layer 251 and the second fin 212. The initial second protective layer 240 covers the surface of the initial first protective layer 230, the sidewall surface of the first protective layer 231, and the surface of the isolation layer 201 of the first region I on the second fin 212.

[0107] The initial second protective layer 240 is used to protect the first doped layer 251 and the isolation layer 201 of the first region I.

[0108] The process for forming the initial second protective layer 240 includes one or more combinations of chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

[0109] The material of the initial second protective layer 240 includes: SiN, SiCN, SiBN or SiON.

[0110] In this embodiment, the material of the initial second protective layer 240 is silicon nitride.

[0111] The material of the initial second protective layer 240 is different from the material of the second oxide layer 214.

[0112] The material of the initial second protective layer 240 is different from that of the second oxide layer 214, which can reduce the impact on the isolation layer 210 and the first doped layer 251 at the bottom of the initial second protective layer 240 in the first region I when the second oxide layer 214 is removed subsequently.

[0113] Please refer to Figure 13 Remove the initial second protective layer 240 and the initial first protective layer 230 on the top of the second oxide layer 214 to expose the top surface of the second oxide layer 214, and make the initial first protective layer 230 on the surface of the second oxide layer 214 form the second protective layer 232.

[0114] The second protective layer 232 is used to limit the shape of the subsequent second doped layer.

[0115] The second protective layer 232 also covers the surface of the second zone II isolation layer 201.

[0116] The method for removing the initial second protective layer 240 and the initial first protective layer 230 on top of the second oxide layer 214 includes: forming a second mask layer (not shown) on the surface of the initial second protective layer 240, the second mask layer exposing the surface of the initial second protective layer 240 on top of the second fin 212 of the second region II; after forming the second mask layer, etching the initial second protective layer 240 and the initial first protective layer 230 exposed by the second mask layer until the top surface of the second oxide layer 214 is exposed.

[0117] After etching back the initial second protective layer 240 and the initial first protective layer 230 exposed by the second mask layer, the second mask layer is removed.

[0118] The material of the second mask layer is photoresist. The process for removing the second mask layer is an ashing process.

[0119] Please refer to Figure 14 The second oxide layer 214 is removed to form an initial second groove 205, which exposes the second fin 212 and the sidewall of the second protective layer 232 on both sides of the second gate structure 222.

[0120] The process for removing the second oxide layer 214 includes a dry etching process or a wet etching process.

[0121] In this embodiment, the process for removing the second oxide layer 214 is a dry etching process.

[0122] The second oxide layer 214 is made of silicon oxide, and the second protective layer 232 is made of silicon nitride. A gas with high etching selectivity for both silicon oxide and silicon nitride is selected to minimize damage to the second protective layer 232 while removing the second oxide layer 214.

[0123] Please refer to Figure 15 After forming the initial second groove 205, the second fin 212 exposed by the initial second groove 205 is removed to form the second groove 206.

[0124] The process for removing the second fin 212 exposed by the initial second groove 205 includes: an anisotropic dry etching process or anisotropic wet etching process.

[0125] In this embodiment, the process for removing the second fin 212 exposed by the initial second groove 205 is an anisotropic dry etching process.

[0126] The second groove 206 provides space for the subsequent formation of the second doped layer. The volume of the second groove is determined by the position of the second protective layer.

[0127] Please refer to Figure 16 A second doped layer 252 is formed in the second groove 206.

[0128] The process for forming the second doped layer 252 is an epitaxial growth process. During the epitaxial growth process to form the second doped layer 252, in-situ doping of the second doped layer 252 is also included, wherein the dopant ions are second ions.

[0129] When the second gate structure 222 is used to form a P-type device, the material of the second doped layer 252 includes silicon germanium doped with second ions, the conductivity type of the second ions being P-type, and the second ions including boron ions and BF ions. 2- The second doped layer 252 is made of silicon doped with a second ion, the second ion being of N-type conductivity, and the second ion being either phosphorus ion or arsenic ion.

[0130] In this embodiment, the second transistor is of type N, and the material of the second doped layer 252 is silicon doped with a second ion, namely phosphorus ions. The concentration of phosphorus ions in the second doped layer is 5.0E20 atm / cm³. 3 ~8.0E21atm / cm 3 .

[0131] The shape of the second doped layer 252 is limited by the second protective layer 232 on the sidewall of the second groove 206 and is formed in the second groove 206. In order to make the volume of the second doped layer 252 as large as possible, the height of the second doped layer 252 along the normal direction of the semiconductor substrate is as high as possible.

[0132] The height of the second doped layer 252 is greater than the height of the second protective layer 232.

[0133] In this embodiment, the height difference between the second doped layer 252 and the second protective layer 232 is 1nm to 8nm.

[0134] To further increase the volume of the second doped layer 252, the second doped layer 252 covers the top surface of the second protective layer 232 along a direction parallel to the plane of the semiconductor substrate.

[0135] The larger the volume of the second doped layer 252, the greater the channel stress generated, and the smaller the contact resistance between the second doped layer and the subsequently formed plug, thereby improving the performance of the semiconductor device.

[0136] The second protective layer 232 restricts the growth of the second doped layer 252, making it less likely for the second doped layer 252 to form sharp points, thus reducing the probability of bridging between the first doped layer 251 and the second doped layer 252. This optimizes the performance of the semiconductor device.

[0137] Accordingly, this embodiment also provides a semiconductor device formed using the above method.

[0138] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor device, characterized in that, include: A substrate is provided, wherein adjacent first and second fins are provided on the substrate; A first gate structure is formed on the substrate, spanning the first fin, the first gate structure covering part of the sidewall and top surface of the first fin; A second gate structure is formed across the second fin on the substrate, the second gate structure covering part of the sidewall and top surface of the second fin; After the first gate structure and the second gate structure are formed, a first sacrificial layer is formed on the top and sidewall of the first fin on both sides of the first gate structure. A first protective layer is formed on the sidewall of the first sacrificial layer; Remove the first sacrificial layer and the first fin on both sides of the first gate structure, and form a first groove in the first fin, the first groove exposing the sidewall of the first protective layer; A first doped layer is formed within the first groove; A second doped layer is formed in the second fin on both sides of the second gate structure; The first doped layer and the second doped layer are source and drain doped layers; The method for forming the second doped layer includes: forming a second sacrificial layer on the top and sidewalls of the second fins on both sides of the second gate structure; forming a second protective layer on the sidewalls of the second sacrificial layer; removing the second sacrificial layer and the second fins on both sides of the second gate structure to form a second groove, the second groove exposing the sidewalls of the second protective layer; and forming a second doped layer in the second groove. The method for forming the second sacrificial layer includes: oxidizing the second sacrificial layer to form a second oxide layer; removing the second oxide layer and the second fin on both sides of the second gate structure to form a second groove.

2. The method for forming a semiconductor device according to claim 1, characterized in that, The material of the first sacrificial layer includes: SiGe, Si, or SiC.

3. The method for forming a semiconductor device according to claim 2, characterized in that, When the material of the first sacrificial layer is SiGe or Si, the method for forming the first sacrificial layer further includes: oxidizing the first sacrificial layer to form a first oxide layer; removing the first oxide layer and the first fin on both sides of the first gate structure, and forming a first groove in the first fin.

4. The method for forming a semiconductor device according to claim 1, characterized in that, The material of the second sacrificial layer includes SiGe, Si, or SiC.

5. The method for forming a semiconductor device according to claim 1, characterized in that, After the first sacrificial layer is formed, the second sacrificial layer is formed; or, after the second sacrificial layer is formed, the first sacrificial layer is formed.

6. The method for forming a semiconductor device according to claim 1, characterized in that, The second sacrificial layer is formed during the formation of the first sacrificial layer.

7. The method for forming a semiconductor device according to claim 1, characterized in that, The substrate includes a first region and a second region, the first fin is located in the first region of the substrate, and the second fin is located in the second region of the substrate; the substrate further includes: an isolation layer, the isolation layer covering a portion of the sidewall of the first fin and a portion of the sidewall of the second fin; the first gate structure and the second gate structure are also located on the isolation layer; the first sacrificial layer and the second sacrificial layer are also located on the isolation layer.

8. The method for forming a semiconductor device according to claim 7, characterized in that, After the first sacrificial layer and the second sacrificial layer are formed, the first protective layer is formed.

9. The method for forming a semiconductor device according to claim 8, characterized in that, The method for forming the first protective layer includes: forming an initial first protective layer on a first fin and a second fin, the initial first protective layer covering the top and sidewalls of a first sacrificial layer, the top and sidewalls of a second sacrificial layer, a first gate structure, a second gate structure, and the surface of an isolation layer; forming a first mask layer on the surface of the initial first protective layer, the first mask layer covering the surface of the initial first protective layer in a second region; after forming the first mask layer, etching back the initial first protective layer exposed by the first mask layer until the surface of the first sacrificial layer and the surface of the isolation layer in the first region are exposed; forming a first protective layer on the sidewall of the first fin, the first protective layer covering the sidewall of the first sacrificial layer; and after etching back the initial first protective layer exposed by the first mask layer, removing the first mask layer.

10. The method for forming a semiconductor device according to claim 9, characterized in that, It also includes: after forming the first doped layer, forming a second protective layer, the second protective layer also covering the surface of the second isolation layer.

11. The method for forming a semiconductor device according to claim 10, characterized in that, The method for forming the second protective layer includes: forming an initial first protective layer on the surface of the first doped layer and the second fin, the initial first protective layer further covering the sidewall surface of the first protective layer and the surface of the isolation layer in the first region; removing the initial second protective layer and the initial first protective layer on the top of the second sacrificial layer to expose the top surface of the second sacrificial layer, and forming the initial first protective layer on the surface of the second sacrificial layer as the second protective layer.

12. The method for forming a semiconductor device according to claim 11, characterized in that, The method for forming the second groove includes: removing the second sacrificial layer to form an initial second groove in the second region, wherein the initial second groove exposes the second fins and the sidewalls of the second protective layer on both sides of the second gate structure; after forming the initial second groove, removing the second fins exposed by the initial second groove to form the second groove.

13. The method for forming a semiconductor device according to claim 1, characterized in that, The height of the first doped layer is greater than the height of the first protective layer; the height difference between the first doped layer and the first protective layer is 1 nm to 15 nm.

14. The method for forming a semiconductor device according to claim 13, characterized in that, The first doped layer covers the top surface of the first protective layer.

15. The method for forming a semiconductor device according to claim 1, characterized in that, The height of the second doped layer is greater than the height of the second protective layer; the height difference between the second doped layer and the second protective layer is 1 nm to 8 nm.

16. The method for forming a semiconductor device according to claim 15, characterized in that, The second doped layer covers the top surface of the second protective layer.

17. The method for forming a semiconductor device according to claim 1, characterized in that, The material of the first protective layer includes: SiN, SiCN, SiBN or SiON.

18. A semiconductor device formed using the forming method according to any one of claims 1 to 17.

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