Overlay measurement mark

Abstract

The present disclosure provides a stack measurement mark for confirming a stack error between two successive layers of a substrate. The stack measurement mark includes a first axis, a second axis, a target feature, a first alignment feature, and a second alignment feature. The second axis intersects the first axis. The target feature is disposed at an intersection of the first axis and the second axis. The first alignment feature is disposed on the first axis, the second alignment feature is disposed on the second axis, and the first and second alignment features are disposed in pairs.

Description

Technical Field

[0001] This application claims priority to U.S. Patent Applications Nos. 17 / 672,862 and 17 / 673,155 (i.e., priority date “February 16, 2022”), the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a pairing mark for checking alignment accuracy. In particular, it relates to a pairing measurement mark for aligning different layers of a substrate. Background Technology

[0003] The semiconductor integrated circuit industry has experienced rapid growth. Technological advancements in integrated circuit materials and design have led to several generations of integrated circuits, each generation being smaller and more complex than the last. Today, semiconductor devices and integrated circuits comprise multiple multilayer structures with dimensions smaller than one micrometer.

[0004] As is known in the art, a lithography process is a step in determining critical dimensions during the manufacture of semiconductor integrated circuit devices. An electronic circuit pattern is formed by first transferring a pattern on a reticle to a photoresist layer using a lithography process, and then, in a subsequent etching process, transferring the pattern from the photoresist layer to a next material layer, such as a dielectric layer or a metal layer.

[0005] Successful lithography on a wafer depends on control over critical dimensions and alignment precision. As integrated circuits continue to shrink in size, especially below 20 nanometers, precisely aligning multiple layers has become increasingly difficult. Therefore, the measurement of precision, i.e., the measurement of overlap error, is crucial to the semiconductor manufacturing process. An overlap mask is used as a tool to measure overlap error and, after lithography, to determine whether a photoresist pattern is precisely aligned with the previous layer on a chip.

[0006] If all or part of the overlay masks are not properly aligned, the resulting features may not align correctly with adjacent layers. This can lead to degraded component performance or complete component failure. While existing overlay (measurement) marks have been used to prevent incorrect alignment, this method is not entirely satisfactory for small-sized components.

[0007] The above description of "prior art" is merely to provide background information and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art to this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention

[0008] One embodiment of this disclosure provides an overlay measurement mark for confirming an overlay error between two consecutive layers of a substrate. The overlay measurement mark includes a first axis, a second axis, a target feature, a first alignment feature, and a second alignment feature. The second axis intersects the first axis. The target feature is disposed at an intersection of the first and second axes. The first alignment feature is disposed on the first axis, and the second alignment feature is disposed on the second axis, and the first and second alignment features are disposed in pairs.

[0009] In some embodiments, the first axis, the second axis, the target feature, the first alignment feature, and the second alignment feature are disposed in at least one cutting line of the substrate.

[0010] In some embodiments, a shortest distance between the first axis and the second alignment feature is equal to a shortest distance between the second axis and the first alignment feature.

[0011] In some embodiments, the target feature is disposed on a first layer of the substrate, while the first axis, the second axis, the first alignment feature, and the second alignment feature are disposed on a second layer above or below the first layer.

[0012] In some embodiments, the target feature includes a two-line segment, and when the first layer and the second layer are correctly aligned, the first axis and the second axis respectively overlap with the equal-line segment.

[0013] In some embodiments, the first axis is orthogonal to the second axis.

[0014] In some embodiments, the target feature has a cross shape.

[0015] In some embodiments, the first alignment feature and the second alignment feature are each composed of a plurality of repetitious microstructures.

[0016] In some embodiments, the first alignment feature and the second alignment feature each have a square outline and are composed of a plurality of square microstructures.

[0017] In some embodiments, these microstructures are separated from each other by a pair of vacant regions.

[0018] In some embodiments, the vacant regions have a first width, and the microstructures have a second width, the second width being greater than the first width.

[0019] In some embodiments, the gap includes a horizontal gap and a vertical gap, the first axis extends through the horizontal gap of the first alignment feature located at the first axis, and the second axis extends through the vertical gap of the second alignment feature located at the second axis.

[0020] One embodiment of this disclosure provides an overlay measurement mark for confirming the relative positions of multiple consecutive patterned layers of a substrate. The overlay measurement mark includes a first axis, a second axis, a target feature, and multiple alignment features. The second axis is orthogonal to and intersects the first axis. The target feature is disposed at an intersection of the first and second axes. The multiple alignment features are disposed along the first and second axes.

[0021] In some embodiments, a distance between alignment features of adjacent pairs is fixed.

[0022] In some embodiments, the alignment features of the adjacent pairs are separated from the intersection of the first axis and the second axis by an equal distance, and the alignment features of the adjacent pairs are configured to determine the relative positions of the plurality of consecutive patterned layers.

[0023] In some embodiments, the first axis divides the second axis into an upper segment and a lower segment; the second axis divides the first axis into a left segment and a right segment; the plurality of alignment features disposed at the upper segment and the lower segment are provided to determine the relative positions of the plurality of consecutively patterned layers in an array region of the substrate; and the plurality of alignment features disposed at the lower segment and the upper segment are provided to determine the relative positions of the plurality of consecutively patterned layers in a surrounding region adjacent to the array region.

[0024] In some embodiments, manufacturing one of the plurality of alignment features close to the target feature is performed before manufacturing another of the plurality of alignment features located away from the target feature.

[0025] In some embodiments, the first axis, the second axis, the target feature, and the plurality of alignment features are disposed in a plurality of cutting lines on the substrate.

[0026] In some embodiments, the first axis and the second axis have a length of approximately 15 nanometers.

[0027] In some embodiments, the target feature is disposed on a first structural layer of the substrate, and the first axis, the second axis, and the plurality of alignment features are disposed on a second structural layer located above or below the first structural layer.

[0028] In some embodiments, the plurality of alignment features are divided into four equal parts via a pair of vacant areas, and the first axis or the second axis extends through one of the vacant areas.

[0029] In some embodiments, the superimposed measurement markers have a reflective symmetry or a rotational symmetry.

[0030] One embodiment of this disclosure provides a method for identifying a stacking error during semiconductor manufacturing. The method includes forming a first structural layer on a wafer, the first structural layer including a target feature; forming a second structural layer on the first structural layer, the second structural layer including a first axis, a second axis, and a pair of alignment features, wherein the pair of alignment features are disposed at the first axis and the second axis; and using a position of the first axis relative to the target feature and a position of the second axis relative to the target feature to determine a relative displacement between the first structural layer and the second structural layer.

[0031] In some embodiments, the method further includes recording an image of a substrate, the substrate including the wafer, the first structural layer, and the second structural layer; wherein the relative displacement of the first structural layer and the second structural layer is determined based on the at least one image.

[0032] In some embodiments, the first axis is formed to bisect one of the pair of alignment features; the second axis is formed to intersect the first axis to bisect the other of the pair of alignment features; and the first structural layer and the second structural layer are correctly aligned when an intersection of the first axis and the second axis overlaps with the target feature.

[0033] In some embodiments, the first axis is formed to bisect one of the pair of alignment features; the second axis, which intersects the first axis, is formed to bisect the other of the pair of alignment features; and when the intersection of the first axis and the second axis deviates from the target feature, the first structural layer and the second structural layer are not properly aligned.

[0034] In some embodiments, when one of the first axis and the second axis deviates from the target feature, the first structural layer and the second structural layer are not properly aligned.

[0035] In some embodiments, the second structural layer is formed using a photolithography process.

[0036] In some embodiments, the second structural layer includes a photoresist material.

[0037] In some embodiments, the first axis, the second axis, the alignment feature, and the target feature are located in at least one dicing line on the wafer.

[0038] Because of the configuration of the overlapping measurement marks, which include the first axis and the second axis that intersect and extend through the centers of the alignment features, the overlapping measurement can be performed effectively and quickly to correct the process and keep the overlapping error within several desired limits.

[0039] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, enabling a better understanding of the detailed description that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily used to achieve the same purpose as this disclosure by modifying or designing other structures or processes. Those skilled in the art to which this disclosure pertains will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the appended claims. Attached Figure Description

[0040] When referring to the drawings in conjunction with the embodiments and claims, a more comprehensive understanding of the disclosure of this application can be obtained. The same element symbols in the drawings refer to the same elements.

[0041] Figure 1 This is a top view schematic diagram illustrating the base of some embodiments of this disclosure.

[0042] Figure 2 This is an enlarged schematic diagram, for example. Figure 1 Region A in the middle.

[0043] Figure 3 This is a block diagram illustrating a dynamic random access memory (DRAM) according to some embodiments of the present disclosure.

[0044] Figure 4 This is a top view schematic diagram illustrating a first axis, a second axis, a first alignment feature, and a second alignment feature in some embodiments of this disclosure.

[0045] Figure 5 This is a top view schematic diagram illustrating alignment features of some embodiments of the present disclosure.

[0046] Figure 6 This is a top view schematic diagram illustrating some embodiments of the present disclosure for aligning stacked measurement marks on different layers of a wafer.

[0047] Figure 7 This is a top view schematic diagram illustrating some embodiments of the present disclosure of stacking measurement marks used for measuring stacking errors.

[0048] Figure 8 This is a top view schematic diagram, illustrating a portion of a substrate including multiple grain regions and a stack of measurement markers.

[0049] Figure 9This is a flowchart illustrating methods for determining overlap errors during semiconductor manufacturing processes according to some embodiments of this disclosure.

[0050] Figure 10 This is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of overlapping measurement marks in some embodiments of the present disclosure.

[0051] Figure 11 This is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of overlapping measurement marks in some embodiments of the present disclosure.

[0052] Figure 12 This is a top view schematic diagram illustrating an intermediate stage in the formation of overlapping measurement marks in some embodiments of this disclosure.

[0053] Figure 13 This is a sectional view, illustrating along... Figure 12 The section along line A-A'.

[0054] Figure 14 This is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of overlapping measurement marks in some embodiments of the present disclosure.

[0055] Figure 15 This is a top view schematic diagram illustrating an intermediate stage in the formation of overlapping measurement marks in some embodiments of this disclosure.

[0056] Figure 16 This is a sectional view, illustrating along... Figure 15 The section along line B-B'.

[0057] Figure 17 This is a top view schematic diagram illustrating an intermediate stage in the formation of overlapping measurement marks in some embodiments of this disclosure.

[0058] Figure 18 This is a sectional view, illustrating along... Figure 17 The cross section with section line C-C'.

[0059] Figure 19 This is a top view schematic diagram illustrating an intermediate stage in the formation of overlapping measurement marks in some embodiments of this disclosure.

[0060] Figure 20 This is a sectional view, illustrating along... Figure 19 The cross section of section line D-D'.

[0061] The reference numerals in the attached figures are explained as follows:

[0062] 10: Base

[0063] 110: Grain region

[0064] 112: Array area

[0065] 1124: Memory cell

[0066] 114: Surrounding Area

[0067] 1142: Address Buffer

[0068] 1144: Column Decoder

[0069] 1146: Sensing Amplifier

[0070] 1148: Line Decoder

[0071] 1150: Input / Output Buffer

[0072] 1152: Clock Generator

[0073] 120: First cutting line

[0074] 130: Second cutting line

[0075] 140: Wafer

[0076] 150: First Floor

[0077] 151: First structural layer

[0078] 160: Second layer

[0079] 162: Second structural layer

[0080] 170: Third Floor

[0081] 180: Photoresist layer

[0082] 182: Characteristic Pattern

[0083] 200: Overlapping measurement marks

[0084] 210: First Axis

[0085] 212: Second Axis

[0086] 214: Target Features

[0087] 2142: Line Segment

[0088] 2144: Line segment

[0089] 215a: First alignment feature

[0090] 215b: Second alignment feature

[0091] 216: Alignment Feature

[0092] 2162: Vacant Area

[0093] 2164: Square microstructure

[0094] 220: First Alignment Group

[0095] 222a: Alignment feature

[0096] 222b: Alignment feature. 222c: Alignment feature.

[0097] 222d: Alignment feature

[0098] 230: Second Alignment Group

[0099] 232a: Alignment Features

[0100] 232b: Alignment Feature

[0101] 232c: Alignment Feature

[0102] 232d: Alignment Feature 300: Method

[0103] BL: Bitline

[0104] d: Shortest distance

[0105] D1: First Direction

[0106] D2: Second Direction

[0107] L: Length S301: Step S302: Step S303: Step S304: Step S306: Step S308: Step

[0108] W1: First width

[0109] W2: Second width

[0110] WL: Character Line

[0111] x: displacement

[0112] y: displacement Detailed Implementation

[0113] The embodiments or examples of this disclosure shown in the accompanying drawings will now be described using specific language. It should be understood that the scope of this disclosure is not intended to be limited thereto. Any modifications or improvements to the described embodiments, and any further applications of the principles described herein, will be considered commonplace by those skilled in the art. Component numbers may be repeated throughout the embodiments, but this does not necessarily mean that a feature of one embodiment is applicable to another embodiment, even if they share the same component numbers.

[0114] It should be understood that while the terms “first,” “second,” “third,” etc., may be used in this text to describe different elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish an element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, the terms “first element,” “component,” “region,” “layer,” or “section” discussed below may be referred to as a second element, component, region, layer, or part without departing from the teachings of this text.

[0115] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when the terms “comprises” and / or “comprising” are used in this specification, these terms specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups of the foregoing.

[0116] Figure 1 This is a top view schematic diagram illustrating the base 10 of some embodiments of this disclosure. Please refer to... Figure 1 The substrate 10 includes a plurality of grain regions 110, which are separated from each other by a plurality of first dicing lines 120 and a plurality of second dicing lines 130. The first dicing lines 120 extend along a first direction D1, and the second dicing lines 130 extend along a second direction D2. In some embodiments, the first direction D1 extends in a horizontal direction, and the second direction D2 extends in a vertical direction, and the second direction D2 is substantially orthogonal to the first direction D1.

[0117] Furthermore, each of the first dicing lines 120 intersects the second dicing lines 130 at right angles. Accordingly, the grain regions 110 divided by the first dicing lines 120 and the second dicing lines 130 generally have a straight shape and are arranged in a matrix on the substrate 10.

[0118] The substrate 10 can undergo various processes, including thin-film forming, lithography, ion implantation, and cleaning, to form multiple integrated circuits in the die regions 110, wherein these integrated circuits are functional units, and the functional units ultimately become a single die or chip. In some embodiments, different features and multiple structural layers to form these integrated circuits are fabricated in and on a single wafer 140 using multiple processes, including oxidation, deposition, doping, diffusion, resist application and stripping, exposure, development, etching, metallization, annealing, and chemical mechanical polishing, but not limited thereto. The integrated circuit may include multiple doped regions, multiple insulating features, and different layers not described separately but combined to form different microelectronic components, including a logic element (e.g., a microcontroller) or a memory element (e.g., a dynamic random access memory or a non-volatile memory).

[0119] The wafer 140 of the substrate 10 may comprise silicon. Alternatively or additionally, the wafer 140 may comprise other semiconductor materials, such as group III-V semiconductor materials. Examples of such layers on the wafer 140 include multiple dielectric layers, multiple doped layers, and multiple conductive layers comprising multiple metallic materials. In some embodiments, the first dicing lines 120 and the second dicing lines 130 may have a width of approximately 30 to 100 micrometers, depending on the dimensions of the integrated circuits fabricated in and on the wafer 140.

[0120] After manufacturing, the substrate 10 is partitioned into multiple individual integrated circuits using a technique such as dicing or sawing. Typically, it is sawed along the first dicing lines 120 and the second dicing lines 130 to partition into the die regions 110. For example, these individual integrated circuits may be packaged separately. Alternatively, these individual integrated circuits may be packaged in multiple multi-chip modules. In particular, when a dicing operation is performed, the area of ​​the wafer along the first dicing lines 120 and the second dicing lines 130 is wasted.

[0121] Figure 2 This is an enlarged schematic diagram, for example. Figure 1 Area A within. Please refer to... Figure 2 The die region 110 may include an array region 112 and a surrounding region 114, with the surrounding region 114 adjacent to the array region 112. For example, when the integrated circuit is a dynamic random access memory, a memory cell array (e.g., ...) is provided in the array region 112. Figure 3 As shown, it includes multiple memory cells 1124 for storing data, and multiple peripheral circuit bits requiring external input and output are located in the peripheral area 114.

[0122] Please refer to Figure 3 In some embodiments, memory cells 1124 are located at an intersection of a word line WL and a bit line BL. The surrounding circuitry for accessing the memory cells 1124 may include, but is not limited to, an address buffer 1142, a column decoder 1144, multiple sense amplifiers 1146, a row decoder 1148, an input / output (I / O) buffer 1150, and a clock generator 1152. The address buffer 1142 acquires an externally provided address to select one of the memory cells 1124 in the memory cell array 1122, and generates an internal row address and an internal column address in response to the externally provided address.

[0123] A column decoder 1144, which decodes the internal column address to select a column (word line) specified by the internal column address, is electrically coupled to an address buffer 1142 and the word line WL. Sensing amplifiers 1146, electrically coupled to an I / O buffer 1150 and the bit line BL, are configured to detect and amplify data connected to the memory cell 1124 to the word line WL selected by the column decoder 1144. A row decoder 1148, electrically coupled to the sensing amplifiers 1146, uses the internal column address from the address buffer 1142 to select the corresponding row (bit line) in the memory cell array 112.

[0124] Clock generator 1152 is electrically coupled to address buffer 1142, sense amplifier 1146, line decoder 1148, and I / O buffer 1150. Clock generator 1152 may be an electronic oscillator that generates a clock signal to synchronize the operation of the peripheral circuitry of the integrated circuit.

[0125] During a read operation, one of the sense amplifiers 1146 amplifies a voltage difference generated in a selected bit line based on the stored data in a selected memory cell 1124, and outputs the amplified result as read data to an external device via I / O buffer 1150. During a write operation, based on the write data input via I / O buffer 1150, a voltage difference with a predetermined amplitude is generated in a selected bit line, thereby storing the write data in a selected memory cell 1124.

[0126] Please refer to this again. Figure 2 According to some embodiments, each array region 112 is surrounded by one of the surrounding regions 114. In addition, each surrounding region 114 may optionally include a sealing ring 116 surrounding another array region 112 to prevent cracks from being transmitted to that individual array region 112 of the substrate 10 during the separation of such grain regions 110.

[0127] Typically, the integrated circuit is confined within the die region 110 and does not extend into or cross the first dicing lines 120 and the second dicing lines 130 of the substrate 10 to be sawn. However, reliability and functional measurement markers are configured in the first dicing lines 120 and the second dicing lines 130 to measure and characterize multiple structural variations at the wafer level. In some embodiments, on multiple product wafers 140, the measurement markers are placed in the first dicing lines 120 and the second dicing lines 130 to obtain different physical characteristics and performance metrics associated with at least one specific process node.

[0128] For example, an overlay measurement mark 200 for correcting an alignment to keep multiple overlap errors within multiple desired limits may be formed in the first dicing lines 120 and the second dicing lines 130, allowing the overlay measurement mark 200 to be placed on the wafer 140 without occupying space on the integrated circuit. In some embodiments, the overlay measurement mark 200 is suitable for an image-based overlay measurement technique. It is worth noting that the overlay measurement mark 200 in the first dicing lines 120 and the second dicing lines 130 is destroyed when a dicing operation is performed.

[0129] The overlapping measurement mark 200 may include a first axis 210, a second axis 212, a target feature 214, a first alignment feature 215a, and a second alignment feature 215b. The first axis 210 extends in a first direction D1, while the second axis 212 extends in a second direction D2, which is orthogonal to the first direction D1. The target feature 214, having a cross shape, is disposed at an intersection of the first axis 210 and the second axis 212. The first alignment feature 215a is disposed on the first axis 210, and the second alignment feature 215b is disposed on the second axis 212.

[0130] Furthermore, the first alignment feature 215a and the second alignment feature 215b are paired to determine an overlap error between two consecutive layers of the substrate 10. Figure 4 As described, a shortest distance d between the first axis 210 and the second alignment feature 215b is equal to a shortest distance d between the second axis 212 and the first alignment feature 215a.

[0131] It is generally believed that the size of the overlay measurement mark 200 should be as large as possible to maximize the amount of information used for overlay measurement. However, the upper limit of the size of the overlay measurement mark 200 can be determined by the field of view of a measuring tool (not shown) used to measure the number of overlaps and / or cut lines. This field of view generally refers to an optical perimeter that defines the image area available for the overlay measurement mark 200 captured by the measuring tool, and the number of cut lines generally refers to the available space allowed for the placement of the first cut lines 120 and the second cut lines 130 of the overlay measurement mark 200. For example, the first axis 210 and the second axis 212 may have a length L that is not greater than 28 micrometers. In some embodiments, the length L of the first axis 210 and the second axis 212 is approximately 15 micrometers.

[0132] Figure 5 This is a top-view schematic diagram illustrating alignment feature 216 of some embodiments of the present disclosure. The geometry of alignment feature 216 is configured to find a suitable balance between image resolution of the measuring instrument and process robustness. Please refer to... Figure 5 The alignment features 216 have a square outline. However, the size and shape of the alignment features 216 can vary widely. For example, the alignment features 216 can form multiple shapes, such as circles, triangles, rectangles, polygons, and similar shapes.

[0133] In some embodiments, each alignment feature 216 is divided into four equal parts by a plurality of vacant regions 2162 having a first width W1. In some embodiments, the alignment features 216 are composed of a plurality of square microstructures 2164, which are separated by a pair of intersecting vacant regions 2162. Figure 5 As described, these microstructures 2164 have a second width W2, which is greater than the first width W1. It is noteworthy that a lower limit of a feature dimension of each microstructure 2164 is determined by the resolution limit of the measuring instrument.

[0134] Figure 6 This is a top view schematic diagram illustrating some embodiments of the present disclosure for aligning stacking measurement marks 200 on different layers of wafer 140. Please refer to... Figure 6 The overlapping measurement mark 200 may include a first axis 210, a second axis 212, a target feature 214, and a plurality of alignment features 216. The first axis 210 extends in a first direction D1, and the second axis 212 extends in a second direction D2, with the first axis 210 and the second axis 212 intersecting at a right angle. The target feature 214 is disposed at an intersection of the first axis 210 and the second axis 212.

[0135] In some embodiments, the target feature 214 may be composed of two line segments 2142 and 2144 intersecting in an X shape (e.g., ...). Figure 7 It consists of (as shown). Please refer to the following: Figure 6 These alignment features 216 are positioned along the first axis 210 and the second axis 212 at an equal distance between adjacent pairs of alignment features 216. In other words, the distance between adjacent pairs of alignment features is fixed. Please refer to... Figure 6 and Figure 7 Some alignment features 216 are disposed on either side of line segment 2142 of target feature 214, and other alignment features 216 are disposed on either side of line segment 2144 of target feature 214. In some embodiments, the overlap measurement mark 200 has a cross-shaped profile.

[0136] Please refer to Figure 6 For analytical purposes, the overlay measurement mark 200 can be divided into multiple segments. Any number of segments can be used for this analysis of overlap error. In some embodiments, the overlay measurement mark 200 is divided into four segments. In some embodiments, the first axis 210 can divide the second axis 212 into two equal segments, such as an upper segment and a lower segment. Similarly, the second axis 212 can divide the first axis 210 into two equal segments, such as a left segment and a right segment.

[0137] The alignment features 216 are divided into a first alignment group 220 and a second alignment group 230 according to their positions. For example, the first alignment group 220 may include the alignment features 216 disposed at the left segment of the first axis 210 and the upper segment of the second axis 212, while the second alignment group 230 may include the alignment features 216 disposed at the right segment of the first axis 210 and the lower segment of the second axis 212.

[0138] In some embodiments, such alignment features 216 of the first alignment group 220 may be provided to determine whether an overlap error exists in the array region 112 (e.g., Figure 8 As shown), these alignment features 216 can provide the second alignment group 230 to determine whether an overlap error exists in the surrounding area 114. The number of these alignment features 216 in each segment can vary widely. As shown, the number of these alignment features 216 in each segment is the same as the number of these alignment features 216 in other segments; therefore, the overlap measurement mark 200 can have a reflective symmetry or a rotational symmetry.

[0139] Please refer to this again. Figure 6The alignment features 216 in the array region 112 or surrounding region 114 are paired for measuring the overlap error of different layers of the substrate 10. In some embodiments, the alignment features 216 disposed at the first axis 210 and separated from the second axis 212 by a predetermined distance, and the alignment features 216 disposed at the second axis 212 and separated from the first axis 210 by the predetermined distance, are paired for measuring overlap, such as... Figure 7 As shown. In short, the alignment features 216, which are separated by the same shortest distance from the intersections of the first and second axes 210, 212 and are in the same alignment group, are paired to determine the relative positions of the two consecutive patterned layers of the substrate 10.

[0140] like Figure 5 and Figure 7 As described, the first axis 210 is set to extend through the horizontal gap area 2162 of the alignment feature 216 provided at the first axis 210, and the second axis 212 is designed to extend through the longitudinal gap area 2162 of the alignment feature 216 provided at the second axis 212, in order to help measure the overlap error.

[0141] Please refer to Figure 6 The first and second alignment groups 220 and 230 respectively include four pairs of alignment features 222a to 222d and 232a to 232d. It is worth noting that these alignment features 216, represented by different shades of gray, can represent multiple alignment features 216 disposed at different layers of the substrate 10. A first pair of alignment features 222a, closest to the target feature 214, can be provided to determine whether an overlap error exists in an active region of the array (e.g., an active region in array region 112); a second pair of alignment features 222b can be provided to determine whether an overlap error exists in a single bit line contact point; a third pair of alignment features 222c can be provided to determine whether an overlap error exists in multiple bit lines; and a fourth pair of alignment features 222d, furthest from the target feature 214, can be provided to determine whether an overlap error exists in multiple bit lines.

[0142] Furthermore, a fifth pair of alignment features 232a closest to the target feature 214 may be provided to determine whether an overlap error exists in an array region of the surrounding region 114; a sixth pair of alignment features 232b may be provided to determine whether an overlap error occurs in at least one gate conductor of the surrounding region 114; a seventh pair of alignment features 232c may be provided to determine whether an overlap error exists in at least one contact support point; and an eighth pair of alignment features 232d furthest from the target feature 214 may be provided to determine whether an overlap error exists in at least one PFET contact point. It can be observed that the alignment features 216 located near the target feature 214 are formed on the wafer 140 before the alignment features 216 located far from the target feature 214 are formed.

[0143] Figure 9 This is a flowchart illustrating a method 300 for determining overlap error during semiconductor manufacturing, according to some embodiments of the present disclosure. Figure 10 This is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of overlapping measurement marks according to some embodiments of this disclosure. Please refer to... Figure 9 and Figure 10 The method 300 for determining overlap errors during semiconductor manufacturing may begin at step S301, which involves depositing a first layer 150 on a wafer 140. The wafer 140 may typically be a silicon wafer. The wafer 140 may include different doping compositions depending on design requirements well known in the art. The wafer 140 may also include other elemental semiconductors, such as germanium. Alternatively, the wafer 140 may include compound semiconductors and / or alloy semiconductors.

[0144] After the first layer 150 is deposited, a photoresist layer 180 is applied to the entire wafer 140 using a spin coating process, and then dried using a soft bake process. The photoresist layer 180, comprising a photosensitive material, is then exposed and developed to form a shape as shown. Figure 11 The feature pattern 182 shown exposes some portions of the first layer 150. Next, method 300 performs a step S302, executing a patterning process to etch the first layer 150 via the feature pattern 182, thereby forming a target feature 214 (such as...). Figure 12 and Figure 13 A first structural layer 151 (as shown). After the target feature 214 is generated using, for example, an ashing process or a wet etching process, the feature pattern 182 is removed.

[0145] Please refer to Figure 12The wafer 140 includes multiple grain regions 110, which are separated by multiple first dicing lines 120 and multiple second dicing lines 130. Various components, including transistors, diodes, capacitors, resistors, fuses, or the like, are formed in the grain regions 110. A first structural layer 151 for forming these components includes multiple first patterned structures 152 in an array region 112 and target features 214 in the dicing lines 120 and 130. The target features 214 are formed in the first dicing lines 120 and the second dicing lines 130 using the same process used to form the first patterned structures 152 in the array region 112. In other words, the target features 214 are formed as part of the process for manufacturing the first patterned structures 152, allowing the process to be tested and verified without contaminating or interfering with the production of the patterned structures 152. In some embodiments, the first structural layer 150 may be formed during the front-end-of-line (FEOL) process.

[0146] Please refer to Figure 9 and Figure 14 Then, method 300 proceeds to step S303, in which a second layer 160 is deposited on the first structural layer 151. In some embodiments, prior to the deposition of the second layer 160, a third layer 170 is selectively deposited on the first structural layer 151. The second layer 160 may include a photoresist material. Next, some portions of the second layer 160 are exposed to radiation (not shown), and then developed to thereby form a second structural layer 162, as shown. Figure 15 and Figure 16 As shown, the second structural layer 162 includes a first axis 210, a second axis 212, and a pair of alignment features 216 located in the first and second dicing lines 120, 130. In other words, the second structural layer 162 is formed using a photolithography process. In some embodiments, the second structural layer 160 may be a pattern that will be used to protect a portion of the third layer 170 during etching.

[0147] like Figure 15 As described, a first axis 210 intersects a second axis 212, and a pair of alignment features 216 are disposed at the first axis 210 and the second axis 212. Specifically, the first axis 210 extends along a first direction D1, and the second axis 212 extends along a second direction D2, which is substantially perpendicular to the first direction D1. Furthermore, the first axis 210 and the second axis 212 intersect at a right angle. Moreover, one alignment feature 216 is disposed at the first axis 210, and the other alignment feature 216 is disposed at the second axis 212.

[0148] The first axis 210 bisects one of the alignment features 216 disposed thereon, and the second axis 212 bisects the other alignment feature 216 disposed thereon. In other words, the first axis 210 and the second axis 212 serve as multiple reference lines for overlapping measurements.

[0149] After forming a stack of measurement marks including the first axis 210, the second axis 212, the target feature 214, and the alignment features 216, a measuring tool (not shown) is provided to record an image of the first axis 210, the second axis 212, the target feature 214, and the alignment features 216 (step S306). It is noteworthy that if the first structural layer 151 and the second structural layer 162 are used to determine a relative displacement using this measuring tool, the second structural layer 162 and the third layer 170 selectively penetrate and allow light to pass through without significant light scattering.

[0150] Then, method 300 proceeds to step S308, in which a relative displacement between the first structural layer 151 and the second structural layer 162 is determined using the alignment feature 216 relative to a position of the target feature 214. In some embodiments, the overlap measurement is performed immediately after the second structural layer 162, which includes photoresist material, is developed, meaning that the photoresist is developed away in the area exposed to light, thus leaving the overlap pattern in the photoresist.

[0151] In this disclosure, the first axis 210 and the second axis 212 are oriented relative to the alignment features 216. Therefore, the precise alignment of the first structural layer 150 and the second structural layer 160 can be determined by comparing a position of the first axis 210 relative to the target feature 214 and by comparing a position of the second axis 212 relative to the target feature 214. Alternatively, the precise alignment of the first structural layer 150 and the second structural layer 160 can be determined by comparing an intersection of the first and second axes 210, 212 relative to the target feature 214.

[0152] Please refer to Figure 15 and Figure 16 In some embodiments, the first structural layer 151 and the second structural layer 162 are correctly aligned once the first axis 210 and the second axis 212 extend through the target structure 214. Alternatively, it is determined that the first structural layer 151 and the second structural layer 162 are correctly aligned when an intersection of the first axis 210 and the second axis 212 overlaps with the target feature 216.

[0153] Please refer to Figure 17 and Figure 18 Because a displacement x exists between the second axis 212 and the target feature 214, the second structural layer 162 is not correctly aligned with the first structural layer 151. Please refer to... Figure 19 and Figure 20Because a displacement y exists between the second axis 212 and the target feature 214, the second structural layer 162 is not correctly aligned with the first structural layer 151. In other words, an overlap error exists between the first structural layer 151 and the second structural layer 162.

[0154] Generally, a large overlap error results in a significant misalignment between the first structural layer 151 and the second structural layer 162. If the overlap error is too large, it may jeopardize the performance of a manufactured integrated circuit; therefore, the substrate 10 with unacceptable overlap errors can be reworked by removal and re-deposition of photoresist—re-exposure and re-development. Rework is generally undesirable, but it is better than completely scrapping the wafer 140.

[0155] In summary, due to the configuration of the overlap measurement marks 200, which include the first axis 210 and the second axis 212 extending through the centers of the alignment feature 216, the overlap measurement for the process correction can be performed efficiently and quickly in order to keep the overlap error within the desired range.

[0156] One embodiment of this disclosure provides an overlay measurement mark. The overlay measurement mark includes a first axis, a second axis, a target feature, a first alignment feature, and a second alignment feature. The second axis intersects the first axis. The target feature is disposed at the intersection of the first and second axes. The first alignment feature is disposed on the first axis, and the second alignment feature is disposed on the second axis, and the first and second alignment features are disposed in pairs.

[0157] One embodiment of this disclosure provides an overlay measurement mark for confirming the relative positions of multiple consecutive patterned layers of a substrate. The overlay measurement mark includes a first axis, a second axis, a target feature, and multiple alignment features. The second axis is orthogonal to and intersects the first axis. The target feature is disposed at an intersection of the first and second axes. The multiple alignment features are disposed along the first and second axes.

[0158] One embodiment of this disclosure provides a method for identifying a stacking error during semiconductor manufacturing. The method includes forming a first structural layer on a wafer, the first structural layer including a target feature; forming a second structural layer on the first structural layer, the second structural layer including a first axis, a second axis, and a pair of alignment features, wherein the pair of alignment features are disposed at the first axis and the second axis; and using a position of the first axis relative to the target feature and a position of the second axis relative to the target feature to determine a relative displacement between the first structural layer and the second structural layer.

[0159] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives may be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above may be implemented using different methods, and other processes or combinations thereof may be substituted for many of the processes described above.

[0160] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Therefore, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A stacking measurement marker for confirming a stacking error between two consecutive layers of a substrate, comprising: The first structural layer includes a target feature; as well as A second structural layer is deposited on the first structural layer, wherein the second structural layer comprises: First axis; A second axis intersects the first axis. The target feature of the first structural layer is located at an intersection of the first axis and the second axis of the second structural layer; A first alignment feature is disposed on and aligned with the first axis; and A second alignment feature is disposed on and aligned with the second axis; The first alignment feature and the second alignment feature are set in pairs; The relative displacement between the first structural layer and the second structural layer is determined by the position of the first axis of the second structural layer relative to the target feature of the first structural layer and the position of the second axis of the second structural layer relative to the target feature of the first structural layer.

2. The overlapping measurement mark as claimed in claim 1, wherein the first axis, the second axis, the target feature, the first alignment feature, and the second alignment feature are disposed in at least one cutting line of the substrate.

3. The overlapping measurement mark as claimed in claim 1, wherein a shortest distance between the first axis and the second alignment feature is equal to a shortest distance between the second axis and the first alignment feature.

4. The overlapping measurement mark as claimed in claim 2, wherein the first structural layer further includes a plurality of first patterned structures, wherein the second structural layer further includes a plurality of second patterned structures, wherein the second patterned structures are correspondingly disposed on the first patterned structures.

5. The overlapping measurement mark as claimed in claim 4, wherein the target feature includes two line segments, and when the first layer and the second layer are correctly aligned, the first axis and the second axis respectively overlap with the line segments.

6. The overlapping measurement mark as claimed in claim 1, wherein the first axis is orthogonal to the second axis.

7. The overlapping measurement mark as claimed in claim 6, wherein the target feature has a cross shape.

8. The overlapping measurement mark as claimed in claim 1, wherein the first alignment feature and the second alignment feature are each composed of a plurality of repeating microstructures.

9. The overlapping measurement mark as claimed in claim 1, wherein the first alignment feature and the second alignment feature each have a square outline and are composed of a plurality of square microstructures, wherein the plurality of microstructures are separated from each other by a pair of gap regions.

10. The overlapping measurement mark of claim 9, wherein the vacancy region has a first width and the plurality of microstructures have a second width, the second width being greater than the first width.

11. The overlapping measurement mark of claim 9, wherein the pair of gaps includes a horizontal gap and a longitudinal gap, the first axis extends through the horizontal gap of the first alignment feature located at the first axis, and the second axis extends through the longitudinal gap of the second alignment feature located at the second axis.

12. A pairing measurement mark, comprising: First axis; A second axis, which is orthogonal to and intersects the first axis; A target feature is set at an intersection of the first axis and the second axis; as well as Multiple alignment features are provided along the first axis and the second axis and aligned with the first axis and the second axis; The relative displacement of two or more consecutive patterned layers is determined by a position of the first axis relative to the target feature and a position of the second axis relative to the target feature.

13. The overlapping measurement mark of claim 12, wherein a distance between alignment features of adjacent pairs is fixed, and the first axis and the second axis have a length of approximately 15 nanometers.

14. The overlay measurement mark of claim 13, wherein the alignment features of the adjacent pairs are separated from the intersection of the first axis and the second axis by an equal distance, and the alignment features of the adjacent pairs are configured to determine the relative positions of the plurality of consecutive patterned layers.

15. The overlay measurement mark of claim 12, wherein the first axis divides the second axis into an upper segment and a lower segment; the second axis divides the first axis into a left segment and a right segment; the plurality of alignment features disposed at the upper segment and the lower segment are provided to determine the relative positions of the plurality of consecutively patterned layers in an array region of the substrate; and the plurality of alignment features disposed at the lower segment and the upper segment are provided to determine the relative positions of the plurality of consecutively patterned layers in a surrounding region adjacent to the array region.

16. The overlapping measurement mark of claim 12, wherein the manufacturing of one of the plurality of alignment features near the target feature is performed before the manufacturing of another of the plurality of alignment features located away from the target feature.

17. The overlay measurement mark of claim 15, wherein the first axis, the second axis, the target feature, and the plurality of alignment features are disposed in the plurality of cut lines of the substrate.

18. The overlay measurement mark of claim 15, wherein the target feature is disposed on a first structural layer of the substrate, and the first axis, the second axis, and the plurality of alignment features are disposed on a second structural layer located above or below the first structural layer.

19. The overlapping measurement mark of claim 12, wherein the plurality of alignment features are divided into four equal parts by a pair of gaps, and the first axis or the second axis extends through one of the gaps.

20. The superimposed measurement mark as claimed in claim 12, wherein the superimposed measurement mark has a reflection symmetry or rotational symmetry.

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