Noise cancellation passive mixer
By employing a noise cancellation circuit with dual downmixer parallel branches in the Mixer-First structure, and utilizing a CMOS complementary push-pull structure and a passive single-balanced structure for noise cancellation, the contradiction between low power consumption and noise performance in the Mixer-First structure in the RF receiving system is resolved, achieving optimization of low power consumption and high noise figure.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- THE 54TH RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
- Filing Date
- 2023-06-12
- Publication Date
- 2026-07-21
AI Technical Summary
The Mixer-First structure is difficult to simultaneously meet the requirements of low power consumption and high noise performance in RF receiving systems, especially in terms of gain and noise performance.
The noise cancellation circuit employs a dual downmixer parallel branch, including an RF transconductance stage circuit, a mixer switching stage circuit, and a transimpedance amplifier stage circuit. It utilizes a CMOS complementary push-pull structure and a passive single-balanced structure for noise cancellation, and achieves noise cancellation and signal superposition through loop negative feedback and capacitive coupling.
While maintaining low power consumption, the noise figure and conversion gain have been optimized, improving the mixer's linearity and circuit performance.
Smart Images
Figure CN116614090B_ABST
Abstract
Description
Technical Field
[0001] This invention proposes a noise-cancelling passive mixer, belonging to the field of mixer technology. Background Technology
[0002] In radio frequency (RF) receiving systems, the mixer is responsible for converting RF signals to baseband or intermediate frequency (IF) bands. It is a core module in the receiving link, acting as the link between RF and IF signals, and its power consumption accounts for a considerable portion of the total power consumption in the receiving link. Therefore, optimizing the mixer's power consumption is crucial for achieving low power consumption in the overall receiving circuit. Furthermore, the mixer needs to have sufficiently high conversion gain and a low noise figure.
[0003] To meet these requirements, the Mixer-First RF front-end structure has been proposed and applied in recent years. The main idea of the Mixer-First structure is to eliminate the low-noise amplifier module, first converting the RF signal to a low-IF band before subsequent processing. Since processing signals in the RF band consumes a lot of power, while processing low-IF signals requires less power, this structure can effectively reduce power consumption while improving linearity. However, due to the lack of RF gain, the gain and noise performance of the Mixer-First structure receiver front-end are difficult to meet specifications. Summary of the Invention
[0004] To address the aforementioned issues, this invention proposes a noise-cancelling passive mixer based on a Mixer-First structure. This mixer employs a noise cancellation circuit with dual down-mixing parallel branches, featuring both a low-gain mode and a high-performance mode. In high-performance mode, the two branches conduct in parallel, enabling noise cancellation and RF signal superposition, thus optimizing the circuit's noise figure and conversion gain while achieving low power consumption.
[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows:
[0006] A noise-cancelling passive mixer includes an RF transconductance stage circuit, a mixer switching stage circuit, and a transimpedance amplifier stage circuit.
[0007] The radio frequency transconductance stage circuit adopts a CMOS complementary push-pull structure circuit. The radio frequency signal is coupled to the NMOS and PMOS transistors of the CMOS structure transconductance stage through capacitors respectively. Both the NMOS and PMOS transistors operate in the subthreshold region.
[0008] The mixer switching stage circuit consists of two passive single-balanced down-converter parallel circuits. The current generated by the down-conversion in the auxiliary branch has the opposite polarity to the current in the main branch, and the N and P outputs in the two branches are cross-superimposed in reverse to ensure that the main signal is not canceled or weakened. At the same time, the noise of the transconductance stage is negatively fed back to the input through the loop, and is out of phase with the equivalent input noise of the transconductance stage, thereby achieving noise cancellation.
[0009] The aforementioned transimpedance amplifier stage circuit suppresses DC offset voltage caused by self-mixing through a parallel feedback resistor and capacitor.
[0010] Furthermore, the radio frequency transconductance stage circuit includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a first capacitor C1, a second capacitor C2, a third capacitor C3, a first resistor R1, a second resistor R2, and a third resistor R3.
[0011] In this configuration, the source of the first PMOS transistor is connected to the power supply voltage, and its drain is connected to the gate of the third PMOS transistor. The gates of both the first PMOS and the first NMOS transistor are connected to the low-power negative enable terminal LPMODN. The positive terminal of the first resistor is connected to the gate of the third PMOS transistor, and its negative terminal is connected to the drain of the first NMOS transistor. The drain of the second PMOS transistor is connected to the source of the first NMOS transistor, and its source is connected to the drain of the first NMOS transistor. The gates of both the second PMOS and the second NMOS transistor are connected to the low-power positive enable terminal LPMODEP. The positive terminal of the second resistor is connected to the source of the first NMOS transistor. The negative terminal of the second resistor is connected to the drain of the third NMOS transistor; the gate of the third NMOS transistor is connected to the negative terminal of the third resistor; the source of the third NMOS transistor and the source of the second NMOS transistor are grounded; the drain of the second NMOS transistor is connected to the gate of the third NMOS transistor; the positive terminal of the third resistor is connected to the reference voltage VBLAN1; the negative terminal of the second capacitor is connected to the drain of the second NMOS transistor; the positive terminals of the second capacitor and the first capacitor are connected to the input RF signal voltage RFIN; the negative terminal of the first capacitor is connected to the gate of the third PMOS transistor; the positive terminal of the third capacitor is connected to the drain of the third NMOS transistor; and the negative terminal of the third capacitor is connected to the output coupling current IRF.
[0012] Furthermore, the mixer switching stage circuit includes a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a ninth NMOS transistor MN9, a tenth NMOS transistor, an eleventh NMOS transistor MN11, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a ninth capacitor C9, a tenth capacitor C10, an eleventh capacitor C11, a twelfth capacitor C12, a thirteenth capacitor C13, a fourteenth capacitor C14, a fifteenth capacitor C15, a sixteenth capacitor C16, and a seventeenth capacitor C17.
[0013] In this configuration, the drain of the fourth NMOS transistor is connected to the upper plate of the fourth capacitor; the sources of the fourth, fifth, sixth, and seventh NMOS transistors are connected to the lower plate of the third capacitor; and the gates of the fourth and tenth NMOS transistors are connected to the negative terminal of the input local oscillator signal (LOIN). The drain of the fifth NMOS transistor is connected to the lower plate of the fourth capacitor; and the gates of the fifth and eleventh NMOS transistors are connected to the positive terminal of the input local oscillator signal (LOIP). The positive terminal of the tenth capacitor is connected to the upper plate of the fourth capacitor, and the negative terminal of the tenth capacitor is grounded. The positive terminal of the eleventh capacitor is connected to the lower plate of the fourth capacitor, and the negative terminal of the eleventh capacitor is grounded. The drain of the sixth NMOS transistor is connected to the upper plate of the fifth capacitor; and the gates of the sixth and ninth NMOS transistors are connected to the negative terminal of the input quadrature local oscillator signal (LOQN). The drain of the seventh NMOS transistor is connected to the lower plate of the fifth capacitor; and the gates of the seventh and eighth NMOS transistors are connected to the positive terminal of the input quadrature local oscillator signal (LOQP). The thirteenth... The positive terminal of capacitor 11 is connected to the lower plate of capacitor 5, and the negative terminal of capacitor 12 is grounded. The positive terminal of capacitor 12 is connected to the upper plate of capacitor 5, and the negative terminal of capacitor 12 is grounded. The drain of NMOS transistor 8 is connected to the upper plate of capacitor 7. The drain of NMOS transistor 9 is connected to the lower plate of capacitor 7. The positive terminal of capacitor 6 is connected to the upper plate of capacitor 7, and the negative terminal of capacitor 6 is grounded. The positive terminal of capacitor 14 is connected to the upper plate of capacitor 7, and the negative terminal of capacitor 14 is connected to the lower plate of capacitor 7. The positive terminal of capacitor 15 is connected to the lower plate of capacitor 7, and the negative terminal of capacitor 15 is grounded. The drain of NMOS transistor 10 is connected to the upper plate of capacitor 8. The drain of NMOS transistor 11 is connected to the lower plate of capacitor 8. The positive terminal of capacitor 9 is connected to the lower plate of capacitor 8, and the negative terminal of capacitor 9 is grounded. The positive terminal of capacitor 17 is connected to the upper plate of capacitor 8, and the negative terminal of capacitor 17 is connected to the lower plate of capacitor 8. The positive terminal of capacitor 16 is connected to the upper plate of capacitor 8, and the negative terminal of capacitor 16 is grounded.
[0014] Furthermore, the transimpedance amplifier stage circuit includes a fourth resistor R4, a fifth resistor R5, an eighteenth capacitor C18, a nineteenth capacitor C19, and a first transconductance operational amplifier OTA.
[0015] Specifically, the negative input terminal of the first transconductance operational amplifier is connected to the negative terminal of the input current signal, the positive input terminal of the first transconductance operational amplifier is connected to the positive terminal of the input current signal, the positive output terminal of the first transconductance operational amplifier is connected to the negative terminal of the output voltage, and the negative output terminal of the first transconductance operational amplifier is connected to the positive terminal of the output voltage; the positive terminal of the fourth resistor is connected to the negative input terminal of the first transconductance operational amplifier, and the negative terminal of the fourth resistor is connected to the positive output terminal of the first transconductance operational amplifier; the positive terminal of the fifth resistor is connected to the positive input terminal of the first transconductance operational amplifier, and the negative terminal of the fifth resistor is connected to the negative output terminal of the first transconductance operational amplifier; the positive terminal of the eighteenth capacitor is connected to the positive terminal of the fourth resistor, and the negative terminal of the eighteenth capacitor is connected to the negative terminal of the fourth resistor; the positive terminal of the nineteenth capacitor is connected to the positive terminal of the fifth resistor, and the negative terminal of the nineteenth capacitor is connected to the negative terminal of the fifth resistor.
[0016] The beneficial effects of this invention are as follows:
[0017] 1. The present invention adopts a passive structure, which has better linearity and lower power consumption.
[0018] 2. The present invention employs a noise cancellation circuit with dual downmixer parallel branches. In high-performance mode, the two branches are conducted in parallel. For the input RF signal, the noise cancellation network optimizes the noise figure and improves the conversion gain.
[0019] In summary, compared to traditional Mixer-First mixers, the noise-cancelling passive mixer based on the Mixer-First structure of this invention significantly optimizes the noise figure and conversion gain of the circuit. Attached Figure Description
[0020] Figure 1 This is a circuit diagram of a preferred example of a noise-cancelling passive mixer according to the present invention.
[0021] Figure 2 The simulation results of the noise figure of the noise-cancelling passive mixer of the present invention in the low-power mode with transconductance stage cancellation and the high-performance mode with noise cancellation are shown.
[0022] Figure 3 The simulation results of the conversion gain of the noise-cancelling passive mixer of the present invention in the low-power mode with transconductance stage cancellation and the high-performance mode with noise cancellation are shown. Detailed Implementation
[0023] A noise-cancelling passive mixer includes an RF transconductance stage circuit, a mixer switching stage circuit, and a transimpedance amplifier stage circuit; wherein:
[0024] The RF transconductance stage employs a CMOS complementary push-pull structure circuit. The RF signal is coupled to the NMOS and PMOS transistors of the CMOS transconductance stage via capacitors, which helps to increase the equivalent transconductance and reduce the noise figure. Both transistors operate in the subthreshold region using low supply voltage and current multiplexing techniques to meet low power consumption requirements.
[0025] The mixer switching stage employs two passive, single-balanced down-converter parallel circuits. The current generated by the down-conversion in the auxiliary branch has the opposite polarity to the current in the main branch, causing the N and P outputs in the two branches to be cross-superimposed in reverse, thus ensuring that the main signal is not canceled or weakened. At the same time, the noise of the transconductance stage is negatively fed back to the input through a loop, and is out of phase with the equivalent input noise of the transconductance stage, thereby achieving noise cancellation.
[0026] To suppress the DC offset voltage caused by self-mixing, a parallel negative feedback circuit is introduced in the transimpedance amplifier stage. A feedback resistor and capacitor are connected in parallel across the input and output terminals of the transimpedance amplifier stage.
[0027] This mixer employs a passive structure, resulting in better linearity and lower power consumption. Furthermore, it utilizes a noise cancellation circuit with dual downmixing parallel branches. In high-performance mode, both branches conduct in parallel, and the noise cancellation network optimizes the noise figure and improves the conversion gain for the input RF signal.
[0028] The core of this noise-cancelling passive mixer is a noise-cancelling Mixer-First circuit structure with dual down-conversion paths, featuring both low-gain and high-performance modes. In high-performance mode, the two branches conduct in parallel, canceling noise signals and superimposing the main signal, achieving low power consumption while optimizing the circuit's noise figure and conversion gain. In the auxiliary branch, lacking the transconductance stage found in the main branch, the down-conversion current has the opposite polarity to the current in the main branch, causing the N and P outputs of the two branches to be out of phase and cross-superimposed, thus ensuring that the main signal is not canceled or weakened. The noise from the transconductance stage in the main branch is negatively fed back to the input via a loop, out of phase with the equivalent input noise of the transconductance stage, thereby achieving noise cancellation.
[0029] Figure 1 The diagram shown is a preferred example circuit diagram of a noise-cancelling passive mixer.
[0030] like Figure 1 As shown, in this example, the RF transconductance stage includes: a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a first capacitor C1, a second capacitor C2, a third capacitor C3, a first resistor R1, a second resistor R2, and a third resistor R3; wherein:
[0031] The source of the first PMOS transistor MP1 is connected to the power supply voltage, and the drain is connected to the gate of MP3. The gates of MP1 and MN1 are connected to the low-power negative enable terminal LPMODN. The positive terminal of R1 is connected to the gate of MP3, and the negative terminal of R1 is connected to the drain of MN1. The drain of MP2 is connected to the source of MN1, and the source of MP2 is connected to the drain of MN1. The gates of MP2 and MN2 are connected to the low-power positive enable terminal LPMODEP. The positive terminal of R2 is connected to the source of MN1, and the negative terminal of R2 is connected to the drain of MN3. The gate of MN3 is connected to the negative terminal of R3, and the sources of MN3 and MN2 are grounded. The drain of MN2 is connected to the gate of MN3. The positive terminal of R3 is connected to the reference voltage VBLAN1. The negative terminal of C2 is connected to the drain of MN2, and the positive terminals of C2 and C1 are connected to the input RF signal voltage RFIN. The negative terminal of C1 is connected to the gate of MP3. The positive terminal of C3 is connected to the drain of MN3, and the negative terminal of C3 is connected to the output coupling current IRF.
[0032] The mixer switching stage includes: NMOS transistors MN4, MN5, MN6, MN7, MN8, MN9, MN10, and MN11; capacitors C4, C5, and C6; C7, C8, C9, C10, and C11; C12, C13, C14, C15, and C16; and C17.
[0033] The drain of the fourth NMOS transistor MN4 is connected to the upper plate of C4; the sources of MN4, MN5, MN6, and MN7 are connected to the lower plate of C3; the gates of MN4 and the tenth NMOS transistor are connected to the negative terminal of the input local oscillator signal (LOIN); the drain of MN5 is connected to the lower plate of C4; the gates of MN5 and MN11 are connected to the positive terminal of the input local oscillator signal (LOIP); the positive terminal of C10 is connected to the upper plate of C4, and the negative terminal of C10 is grounded; the positive terminal of C11 is connected to the lower plate of C4, and the negative terminal of C11 is grounded; the drain of MN6 is connected to the upper plate of C5; the gates of MN6 and MN9 are connected to the negative terminal of the input quadrature local oscillator signal (LOQN); the drain of MN7 is connected to the lower plate of C5; the gates of MN7 and MN8 are connected to the positive terminal of the input quadrature local oscillator signal (LOQP); the positive terminal of C13 is connected to the lower plate of C5, and the negative terminal of C13 is grounded; the positive terminal of C12... Connect the upper plate of C5, and ground the negative terminal of C12; connect the drain of MN8 to the upper plate of C7; connect the drain of MN9 to the lower plate of C7; connect the positive terminal of C6 to the upper plate of C7, and ground the negative terminal of C6; connect the positive terminal of C14 to the upper plate of C7, and ground the negative terminal of C14; connect the positive terminal of C15 to the lower plate of C7, and ground the negative terminal of C15; connect the drain of the tenth NMOS transistor to the upper plate of C8; connect the drain of MN11 to the lower plate of C8; connect the positive terminal of C9 to the lower plate of C8, and ground the negative terminal of C9; connect the positive terminal of C17 to the upper plate of C8, and ground the negative terminal of C17; connect the positive terminal of C16 to the upper plate of C8, and ground the negative terminal of C16.
[0034] The transimpedance amplifier stage includes: fourth resistor R4, fifth resistor R5, eighteenth capacitor C18, nineteenth capacitor C19, and first transconductance operational amplifier OTA;
[0035] The negative input terminal of OTA is connected to the negative terminal of the input current signal, the positive input terminal of OTA is connected to the positive terminal of the input current signal, the positive output terminal of OTA is connected to the negative terminal of the output voltage, and the negative output terminal of OTA is connected to the positive terminal of the output voltage; the positive terminal of R4 is connected to the negative input terminal of OTA, and the negative terminal of R4 is connected to the positive output terminal of OTA; the positive terminal of R5 is connected to the positive input terminal of OTA, and the negative terminal of R5 is connected to the negative output terminal of OTA; the positive terminal of C18 is connected to the positive terminal of R4, and the negative terminal of C18 is connected to the negative terminal of R4; the positive terminal of C19 is connected to the positive terminal of R5, and the negative terminal of C19 is connected to the negative terminal of R5.
[0036] Figure 2 The figure shown is a simulation result of the noise figure of the noise-cancelling passive mixer in this embodiment in the low-power mode with transconductance stage cancellation and the high-performance mode with noise cancellation.
[0037] Figure 2The simulation curves of the noise figure for the low-power mode with the transconductance stage removed and the high-performance mode with noise cancellation are shown. At an ambient temperature of 300K and a process corner of tt, the high-performance mode RF front-end with noise cancellation has a noise figure of approximately 4dB within the operating bandwidth, while the low-gain mode RF front-end with the transconductance stage removed has a noise figure of approximately 16.5dB within the operating bandwidth. This further demonstrates the effectiveness of noise cancellation technology in improving the noise figure.
[0038] Figure 3 The figure shown is a simulation result of the conversion gain of the noise-cancelling passive mixer in this embodiment in the low-power mode with transconductance stage cancellation and the high-performance mode with noise cancellation.
[0039] Figure 3 The simulation curves of the conversion gain for the low-power mode with the transconductance stage removed and the high-performance mode with noise cancellation are shown. At an ambient temperature of 300K and a process angle of tt, the operating band conversion gain of the high-performance mode RF receiver front-end with noise cancellation is greater than 55dB, while the operating band conversion gain of the low-gain mode RF receiver front-end with the transconductance stage removed is greater than 45dB. This further demonstrates the effect of noise cancellation technology on improving the conversion gain.
[0040] In summary, this invention proposes a novel noise cancellation circuit structure with dual down-mixer parallel branches. The input RF voltage signal is converted into a current signal by the transconductance amplifier stage in the main branch, and then capacitively coupled to a four-way quadrature passive mixer for down-conversion, generating I and Q differential intermediate frequency (IF) signals. Simultaneously, the four-way quadrature passive mixer in the auxiliary branch directly down-converts the signal to generate I and Q differential IF signals. Because the transconductance stage's inverter-like structure inverts the signal once, the circuit design ensures that the IF signals generated by the two branches at the down-mixer output port are cross-superimposed in opposite directions, achieving noise cancellation while preventing signal attenuation. The noise cancellation passive mixer circuit proposed in this invention optimizes the noise figure of the link while meeting low power consumption requirements, effectively alleviating the contradiction between low power consumption, noise figure, and gain in the Mixer-First structure.
[0041] The above description is merely a preferred embodiment of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention. These improvements and modifications should also be considered within the scope of protection of the present invention.
Claims
1. A noise-cancelling passive mixer, characterized in that, This includes the radio frequency transconductance stage circuit, the mixer switching stage circuit, and the transimpedance amplifier stage circuit; The radio frequency transconductance stage circuit adopts a CMOS complementary push-pull structure circuit. The radio frequency signal is coupled to the NMOS and PMOS transistors of the CMOS structure transconductance stage through capacitors respectively. Both the NMOS and PMOS transistors operate in the subthreshold region. The mixer switching stage circuit consists of two passive single-balanced down-converter parallel circuits. The current generated by the down-conversion in the auxiliary branch has the opposite polarity to the current in the main branch, and the N and P outputs in the two branches are cross-superimposed in reverse to ensure that the main signal is not canceled or weakened. At the same time, the noise of the transconductance stage is negatively fed back to the input through the loop, and is out of phase with the equivalent input noise of the transconductance stage, thereby achieving noise cancellation. The aforementioned transimpedance amplifier stage circuit suppresses DC offset voltage caused by self-mixing through a parallel feedback resistor and capacitor. The radio frequency transconductance stage circuit includes a first PMOS transistor (MP1), a second PMOS transistor (MP2), a third PMOS transistor (MP3), a first NMOS transistor (MN1), a second NMOS transistor (MN2), a third NMOS transistor (MN3), a first capacitor (C1), a second capacitor (C2), a third capacitor (C3), a first resistor (R1), a second resistor (R2), and a third resistor (R3). In this configuration, the source of the first PMOS transistor is connected to the power supply voltage, and its drain is connected to the gate of the third PMOS transistor. The gates of both the first PMOS and the first NMOS transistor are connected to the low-power negative enable terminal (LPMODN). The positive terminal of the first resistor is connected to the gate of the third PMOS transistor, and its negative terminal is connected to the drain of the first NMOS transistor. The drain of the second PMOS transistor is connected to the source of the first NMOS transistor, and the source of the second PMOS transistor is connected to the drain of the first NMOS transistor. The gates of both the second PMOS and the second NMOS transistor are connected to the low-power positive enable terminal (LPMODEP). The positive terminal of the second resistor is connected to the source of the first NMOS transistor. The negative terminal of the second resistor is connected to the drain of the third NMOS transistor; the gate of the third NMOS transistor is connected to the negative terminal of the third resistor; the source of the third NMOS transistor and the source of the second NMOS transistor are grounded; the drain of the second NMOS transistor is connected to the gate of the third NMOS transistor; the positive terminal of the third resistor is connected to the reference voltage (VBLAN1); the negative terminal of the second capacitor is connected to the drain of the second NMOS transistor; the positive terminals of the second capacitor and the first capacitor are connected to the input RF signal voltage (RFIN); the negative terminal of the first capacitor is connected to the gate of the third PMOS transistor; the positive terminal of the third capacitor is connected to the drain of the third NMOS transistor; and the negative terminal of the third capacitor is connected to the output coupling current IRF.
2. The noise-cancelling passive mixer according to claim 1, characterized in that, The mixer switching stage circuit includes a fourth NMOS transistor (MN4), a fifth NMOS transistor (MN5), a sixth NMOS transistor (MN6), a seventh NMOS transistor (MN7), an eighth NMOS transistor (MN8), a ninth NMOS transistor (MN9), a tenth NMOS transistor (MN10), an eleventh NMOS transistor (MN11), a fourth capacitor (C4), a fifth capacitor (C5), a sixth capacitor (C6), a seventh capacitor (C7), an eighth capacitor (C8), a ninth capacitor (C9), a tenth capacitor (C10), an eleventh capacitor (C11), a twelfth capacitor (C12), a thirteenth capacitor (C13), a fourteenth capacitor (C14), a fifteenth capacitor (C15), a sixteenth capacitor (C16), and a seventeenth capacitor (C17). In this configuration, the drain of the fourth NMOS transistor is connected to the upper plate of the fourth capacitor; the sources of the fourth, fifth, sixth, and seventh NMOS transistors are connected to the lower plate of the third capacitor; and the gates of the fourth and tenth NMOS transistors are connected to the negative terminal of the input local oscillator signal (LOIN). The drain of the fifth NMOS transistor is connected to the lower plate of the fourth capacitor; and the gates of the fifth and eleventh NMOS transistors are connected to the positive terminal of the input local oscillator signal (LOIP). The positive terminal of the tenth capacitor is connected to the upper plate of the fourth capacitor, and the negative terminal of the tenth capacitor is grounded. The positive terminal of the eleventh capacitor is connected to the lower plate of the fourth capacitor, and the negative terminal of the eleventh capacitor is grounded. The drain of the sixth NMOS transistor is connected to the upper plate of the fifth capacitor; and the gates of the sixth and ninth NMOS transistors are connected to the negative terminal of the input quadrature local oscillator signal (LOQN). The drain of the seventh NMOS transistor is connected to the lower plate of the fifth capacitor; and the gates of the seventh and eighth NMOS transistors are connected to the positive terminal of the input quadrature local oscillator signal (LOQP). The positive terminal of the thirteenth capacitor is connected to the lower plate of the fifth capacitor, and the negative terminal of the thirteenth capacitor is grounded; the positive terminal of the twelfth capacitor is connected to the upper plate of the fifth capacitor, and the negative terminal of the twelfth capacitor is grounded; the drain of the eighth NMOS transistor is connected to the upper plate of the seventh capacitor; the drain of the ninth NMOS transistor is connected to the lower plate of the seventh capacitor; the positive terminal of the sixth capacitor is connected to the upper plate of the seventh capacitor, and the negative terminal of the sixth capacitor is grounded; the positive terminal of the fourteenth capacitor is connected to the upper plate of the seventh capacitor, and the negative terminal of the fourteenth capacitor is connected to the lower plate of the seventh capacitor. The positive terminal of the fifteenth capacitor is connected to the lower plate of the seventh capacitor, and the negative terminal of the fifteenth capacitor is grounded; the drain of the tenth NMOS transistor is connected to the upper plate of the eighth capacitor; the drain of the eleventh NMOS transistor is connected to the lower plate of the eighth capacitor; the positive terminal of the ninth capacitor is connected to the lower plate of the eighth capacitor, and the negative terminal of the ninth capacitor is grounded; the positive terminal of the seventeenth capacitor is connected to the upper plate of the eighth capacitor, and the negative terminal of the seventeenth capacitor is connected to the lower plate of the eighth capacitor; the positive terminal of the sixteenth capacitor is connected to the upper plate of the eighth capacitor, and the negative terminal of the sixteenth capacitor is grounded.
3. The noise cancellation passive mixer according to claim 2, characterized in that, The transimpedance amplifier stage circuit includes a fourth resistor (R4), a fifth resistor (R5), an eighteenth capacitor (C18), a nineteenth capacitor (C19), and a first transconductance operational amplifier (OTA). Specifically, the negative input terminal of the first transconductance operational amplifier is connected to the negative terminal of the input current signal, the positive input terminal of the first transconductance operational amplifier is connected to the positive terminal of the input current signal, the positive output terminal of the first transconductance operational amplifier is connected to the negative terminal of the output voltage, and the negative output terminal of the first transconductance operational amplifier is connected to the positive terminal of the output voltage; the positive terminal of the fourth resistor is connected to the negative input terminal of the first transconductance operational amplifier, and the negative terminal of the fourth resistor is connected to the positive output terminal of the first transconductance operational amplifier; the positive terminal of the fifth resistor is connected to the positive input terminal of the first transconductance operational amplifier, and the negative terminal of the fifth resistor is connected to the negative output terminal of the first transconductance operational amplifier; the positive terminal of the eighteenth capacitor is connected to the positive terminal of the fourth resistor, and the negative terminal of the eighteenth capacitor is connected to the negative terminal of the fourth resistor; the positive terminal of the nineteenth capacitor is connected to the positive terminal of the fifth resistor, and the negative terminal of the nineteenth capacitor is connected to the negative terminal of the fifth resistor.