Audio driving circuit, method, chip and audio playing device

Abstract

The application discloses an audio driving circuit, method, chip and audio playing device, wherein the audio driving circuit comprises a processor, a calibration module and a driving module; the processor is connected between the driving module and the calibration module, and is used for extracting a misadjustment voltage deviation in a mute section of audio output by the driving module, and sending the misadjustment voltage deviation to the calibration module; the calibration module is connected between the processor and the driving module, and is used for accessing initial audio, calibrating the initial audio by using the misadjustment voltage deviation, obtaining a calibration signal, and sending the calibration signal to the driving module; and the input end of the driving module is connected to the calibration module, and is used for driving audio by using the calibration signal, and outputting the driven audio. The application can eliminate noises such as pop sound in the mute section of the initial audio, and improve the listening experience in a mute environment.

Description

Technical Field

[0001] This application relates to the field of circuit technology, specifically to an audio driving circuit, method, chip, and audio playback device. Background Technology

[0002] Audio driver circuits are a crucial component of audio playback devices such as headphones and / or speakers, playing a decisive role in the audio quality played back by these devices. Figure 1a The following is an example of a basic audio driver architecture for mono, which can be used to illustrate the concept. The audio driver circuit may include a digital-to-analog converter (DAC). Figure 1a The DAC and driver module shown Figure 1a As shown in PA), the digital signal data stream is converted into an analog output signal by a digital-to-analog converter (DAC), and then sent to the input terminals INP / INN of the audio driver module to generate the output terminals OUTP / OUTN. These outputs drive an external speaker to play the corresponding audio. Ideally, when the audio DAC and driver circuit are turned on, the output voltages of the output ports OUTP / OUTN should be the same, such as... Figure 1b (1) As shown in the ideal case; however, as Figure 1b As shown in the actual situation (2), due to the Gaussian random deviation in the circuit of the corresponding chip, a DC offset Vos will be generated in the digital-to-analog converter and the drive circuit. Therefore, when the digital-to-analog converter and the drive circuit are turned on, the output voltages of OUTP and OUTN are not equal, such as Figure 1b In reality (2), there is a certain DC offset voltage ΔV. Therefore, at the moment the audio digital-to-analog converter and drive circuit are turned on, this DC offset voltage ΔV will act on the speaker, causing noise (such as popping sound) during audio playback.

[0003] Traditional solutions employ relevant technologies to calibrate the initial input audio signal, but the calibration effect is limited and the calibration process is complex. Summary of the Invention

[0004] In view of this, this application provides an audio driving circuit, method, chip, and audio playback device to solve the problems of limited calibration effect and complex calibration process in traditional audio signal calibration schemes.

[0005] This application provides an audio driver circuit, including a processor, a calibration module, and a driver module; The processor is connected between the driver module and the calibration module, and is used to extract the offset voltage deviation in the silent segment of the audio output by the driver module, and send the offset voltage deviation to the calibration module. The calibration module is connected between the processor and the driver module, and is used to receive the initial audio, calibrate the initial audio using the offset voltage deviation, obtain a calibration signal, and send the calibration signal to the driver module; The input terminal of the driving module is connected to the calibration module, and is used to drive the audio using the calibration signal and output the driven audio.

[0006] Optionally, the audio driving circuit further includes an analog-to-digital converter, a first switching component, and a second switching component; The input terminal of the analog-to-digital converter is connected to the output terminal of the drive module through the first switch assembly and the second switch assembly, respectively. The output terminal is connected to the input terminal of the processor. The converter is used to acquire a first acquisition signal when the first switch assembly is turned on and send the first acquisition signal to the processor. When the second switch assembly is turned on, the converter acquires a second acquisition signal and sends the second acquisition signal to the processor. The first acquisition signal is based on the common-mode voltage with a positive offset voltage deviation superimposed. The second acquisition signal is based on the common-mode voltage with a negative offset voltage deviation superimposed. The processor is used to determine the offset voltage deviation based on the first acquisition signal and the second acquisition signal.

[0007] Optionally, the processor is configured to extract the DC component of the first acquired signal to obtain a first DC signal, extract the DC component of the second acquired signal to obtain a second DC signal, and determine the offset voltage deviation based on the first DC signal and the second DC signal.

[0008] Optionally, the first DC signal includes: data1=VCM+Vos, the second DC signal includes: data2=VCM-Vos; the offset voltage deviation includes: Vos=(data1-data2) / 2; where data1 represents the first DC signal, data2 represents the second DC signal, VCM represents the common-mode voltage, and Vos represents the offset voltage deviation.

[0009] Optionally, the driving module includes a first audio terminal for outputting a positive output signal and a second audio terminal for outputting a negative output signal; the first switching component includes a first sub-switch and a second sub-switch, and the second switching component includes a third sub-switch and a fourth sub-switch; The first input terminal of the analog-to-digital converter is connected to the second audio terminal via the first sub-switch and to the first audio terminal via the third sub-switch. The second input terminal is connected to the second audio terminal via the fourth sub-switch and to the first audio terminal via the second sub-switch.

[0010] Optionally, the audio driving circuit further includes a digital-to-analog converter; the calibration module includes a first adder and a second adder; The input terminal of the digital-to-analog converter is connected to the initial audio, the first output terminal is connected to the first input terminal of the first adder, and the second output terminal is connected to the first input terminal of the second adder; the second input terminal of the first adder is connected to the output terminal of the processor, and the output terminal is connected to the first input terminal of the driver module; the second input terminal of the second adder is connected to the output terminal of the processor, and the output terminal is connected to the second input terminal of the driver module.

[0011] Optionally, the driving module includes a first MOSFET, a second MOSFET, a third MOSFET, a fourth MOSFET, a fifth MOSFET, a first amplifier, and a second amplifier; The gate of the first MOSFET is connected to one input terminal of the first adder, and its source is connected to one output terminal of the first adder, the source of the second MOSFET, and the drain of the third MOSFET. Its drain is connected to the other output terminal of the first adder, the drain of the fourth MOSFET, and the first input terminal of the first amplifier. The gate of the second MOSFET is connected to one input terminal of the second adder, its source is connected to one output terminal of the second adder, and its drain is connected to the other output terminal of the second adder, the drain of the fifth MOSFET, and the second input terminal of the first amplifier. The gate of the third MOSFET is connected to an internal reference voltage, and its source is connected to an external power supply. The gate of the fourth MOSFET is connected to the gate of the fifth MOSFET, and its source is grounded. The source of the fifth MOSFET is grounded. The first output terminal of the first amplifier is connected to the first input terminal of the second amplifier, and the second output terminal is connected to the second input terminal of the second amplifier. The first output terminal of the second amplifier is the first audio terminal, and the second output terminal is the second audio terminal.

[0012] Optionally, each adder includes multiple logic control units connected in parallel, each logic control unit includes two logic control terminals, and each logic control terminal is used to receive the encoded signal sent by the processor to control the channel of each MOS transistor in the driving module and calibrate the initial audio.

[0013] Optionally, the logic control unit includes multiple MOS transistor groups connected in parallel; each MOS transistor group is respectively connected to two high-order control bits and one low-order control bit corresponding to the encoded signal.

[0014] Optionally, the MOS transistor group includes a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor, and a ninth MOS transistor; The gate of the sixth MOS transistor is connected to a high-level control bit, its source is connected to one output terminal of the corresponding adder, and its drain is connected to the source of the seventh MOS transistor; the gate of the seventh MOS transistor is connected to a low-level control bit, and its drain is connected to the source of the eighth MOS transistor and the drain of the ninth MOS transistor; the gate of the eighth MOS transistor is connected to the offset voltage deviation, and its drain is connected to the other output terminal of the corresponding adder; the gate of the ninth MOS transistor is connected to another high-level control bit, and its source is connected to one output terminal of the corresponding adder.

[0015] This application also provides an audio driving method, including: Extract the offset voltage deviation in the silent section of the output audio; The initial audio signal is calibrated using the offset voltage deviation to obtain a calibration signal; The calibration signal is used for audio driving.

[0016] Optionally, extracting the offset voltage deviation in the silent segment of the output audio includes: The first acquisition signal and the second acquisition signal are extracted sequentially from the silent segment of the output audio; the first acquisition signal is based on the common-mode voltage with a positive offset voltage deviation superimposed, and the second acquisition signal is based on the common-mode voltage with a negative offset voltage deviation superimposed. The offset voltage deviation is determined based on the first acquisition signal and the second acquisition signal.

[0017] Optionally, determining the offset voltage deviation based on the first acquired signal and the second acquired signal includes: Extract the DC component of the first acquired signal to obtain the first DC signal; Extract the DC component of the second acquired signal to obtain the second DC signal; The offset voltage deviation is determined based on the first DC signal and the second DC signal.

[0018] This application also provides an audio driver chip, including any of the above-mentioned audio driver circuits.

[0019] This application also provides an audio playback device, including any of the above-mentioned audio driver chips.

[0020] Optionally, the audio playback device further includes a playback component; the first input terminal of the playback component is connected to a first audio terminal, and the second input terminal is connected to a second audio terminal.

[0021] The audio driving circuit, method, chip, and audio playback device described in this application allow the processor to extract offset voltage deviation from the silent segment of the output audio and send this deviation to a calibration module. The calibration module uses the offset voltage deviation to calibrate the silent segment in the initial audio and sends the resulting calibration signal to the driving module. This enables the driving module to use the calibration signal for audio driving, eliminating noise such as popping sounds in the silent segment of the initial audio and improving the listening experience in quiet environments. The process of calibrating the silent segment of the initial audio using the offset voltage deviation can be superimposed within the corresponding analog circuit, simplifying the calibration process and improving calibration efficiency. The entire audio driving process does not require sampling of the VCM (common-mode voltage), simplifying the corresponding circuit structure and reducing power consumption. The driving module uses simple devices such as multiple MOSFETs and amplifiers for audio driving, resulting in a simple structure, high reliability, and good driving effect. The calibration module uses multiple parallel logic control units to logically control the MOSFETs of the driving module to perform addition and / or subtraction operations, simplifying the corresponding calculation process and reducing power consumption during the calculation process while simplifying the circuit structure. As can be seen, the above-mentioned audio driver circuit can improve the audio driving effect from many aspects, simplify the structure and driving process of the audio driver circuit, thereby reducing the corresponding power consumption and improving the playback quality of the corresponding audio playback device. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1a This is a schematic diagram of the structure of a traditional audio driver chip. Figure 1b , Figure 1c and Figure 1d This is a schematic diagram illustrating the audio driving process analysis of a traditional solution; Figure 1e A schematic diagram of another audio driver chip structure in a traditional solution; Figure 2 This is a schematic diagram of an audio driver circuit structure according to an embodiment of this application; Figure 3 This is a schematic diagram of the audio driver circuit structure according to another embodiment of this application; Figure 4 This is a schematic diagram of the audio driver circuit structure according to another embodiment of this application; Figure 5 This is a schematic diagram of the operation process of the audio driving circuit in one embodiment of this application; Figure 6This is a schematic diagram of the drive module structure according to an embodiment of this application; Figure 7 This is a schematic diagram of an adder structure according to an embodiment of this application; Figure 8 This is a schematic diagram of the logic control unit structure according to an embodiment of this application; Figure 9 This is a schematic diagram of a MOS transistor group structure according to an embodiment of this application; Figure 10 This is a schematic diagram of an audio playback device according to an embodiment of this application. Detailed Implementation

[0024] The inventors studied the initial audio signal calibration scheme and discovered relevant methods to reduce Gaussian random bias in the circuitry of the chip, such as... Figure 1c As shown in (1), this reduces its impact; directly reducing Gaussian random bias requires a large area and power consumption, and due to the irregularity of the chip layout, it is difficult to reduce it to the desired offset voltage. Some solutions are as follows: Figure 1c As shown in (2), this voltage difference is established slowly. Since it is established slowly, most of its signal energy will not fall within the range of 20 to 20 kHz, which is outside the range of human hearing, so abnormal sounds cannot be heard. However, this method will cause the audio digital-to-analog converter and the drive circuit to take too long to turn on, which is not conducive to the use scenario that requires fast response.

[0025] Another solution is to use auto-zeroing or chopping techniques to achieve very low offset voltage, such as... Figure 1d As shown, the self-zeroing technique is used to dynamically store the offset voltage of the circuit at the output of the operational amplifier. When outputting, this stored information is superimposed on the output signal to complete the conversion. The chopping technique dynamically swaps the input ports of the operational amplifier to shift the offset voltage to a high frequency and turn it into a high-frequency signal. Both of these techniques will generate a certain amount of high-frequency energy at the output, requiring certain filtering circuits and additional clock signals, which increases the complexity of the circuit.

[0026] Other solutions employ calibration techniques, such as... Figure 1eThe diagram illustrates a digital domain calibration technique. In the chip housing the audio driver circuit, a digital-to-analog converter (DAC) and an analog-to-digital converter (ADC) are typically combined to achieve the recording and playback functions of the audio system. This solution utilizes the on-board ADC. During calibration, the digital input signal is 0. First, the analog signal (VCM + Vos) output from the driver circuit is input to the ADC for conversion into a digital signal. The data processing module then obtains the DC signal data data1 = VCM + Vos. Next, the ADC input is switched to the ADC's common-mode signal VCM, converted back to a digital signal, and processed again to obtain the DC signal data data2 = VCM. Subtracting the two digital signals yields the offset voltage data dcal = Vos, which is stored in the chip. During normal operation, the stored offset voltage signal dcal is superimposed on the digital signal to cancel the offset voltage in the path, thus making the offset voltage output by the driver circuit 0. This method performs addition, subtraction, multiplication, and division operations on the digital signal, completing the calibration in the digital domain.

[0027] The inventors analyzed various solutions and further discovered: 1. When the initial audio signal input is 0 (i.e., there is no playback signal), a certain offset voltage signal is superimposed on it. This results in a certain voltage at the output of the digital-to-analog converter (DAC), causing a certain amount of noise from the DAC to reach the output of the driver circuit via the power amplifier (PA), leading to noise at the output and a deterioration in listening experience in a quiet environment. 2. To solve the problem in point 1, the digital signal superimposed with the offset voltage signal needs a certain fade-in / fade-out during startup and shutdown. Otherwise, there will still be a popping sound during startup and shutdown, increasing software overhead and failing to achieve a fast response effect. 3. Since the calibration process requires analog-to-digital conversion of the VCM (common-mode voltage), sampling of the VCM is necessary. Therefore, the VCM must have driving capability, increasing the requirements for the VCM and power consumption.

[0028] Based on the aforementioned technical problems, the audio driving circuit, method, chip, and audio playback device provided in this application allow the processor to extract the offset voltage deviation from the silent segment of the output audio, send the offset voltage deviation to the calibration module, and the calibration module to calibrate the initial audio using the offset voltage deviation. The resulting calibration signal is then sent to the driving module, enabling the driving module to use the calibration signal for audio driving. This eliminates noise such as popping sounds in the silent segment of the initial audio, improving the listening experience in quiet environments. Furthermore, the process of calibrating the initial audio using the offset voltage deviation can be superimposed within the corresponding analog circuit, simplifying the calibration process and improving calibration efficiency. The entire audio driving process does not require sampling the VCM, simplifying the corresponding audio driving circuit structure and reducing power consumption during the audio driving process.

[0029] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In the absence of conflict, the following embodiments and their technical features can be combined with each other.

[0030] The first aspect of this application provides an audio driver circuit, as referenced... Figure 2 As shown, the audio driving circuit includes a processor 110, a calibration module 200, and a driving module 300. Specifically, the first input terminal of the calibration module 200 is connected to the initial audio, the output terminal is connected to the input terminal of the driving module 300, the second input terminal is connected to the output terminal of the processor 110, and the input terminal of the processor 110 is connected to the output terminal of the driving module 300. Here, the output terminal of the driving module 300 outputs audio, which can also be referred to as the audio output terminal of the corresponding audio driving circuit.

[0031] The processor 110 is connected between the driver module 300 and the calibration module 200, and is used to extract the offset voltage deviation in the silent segment of the audio output by the driver module 300, and send the offset voltage deviation to the calibration module 200. The calibration module 200 is connected between the processor 110 and the driver module 300. It is used to receive the initial audio, calibrate the initial audio using the offset voltage deviation, obtain a calibration signal, and send the calibration signal to the driver module 300. The input terminal of the driving module 300 is connected to the calibration module 200, and is used to drive the audio using the calibration signal and output the driven audio.

[0032] Specifically, the calibration module 200 uses the offset voltage deviation to calibrate the silent segment in the initial audio, obtains the calibration signal of the silent segment, and sends the calibration signal to the drive module 300 so that the drive module 300 uses the calibration signal to drive the corresponding silent segment and eliminate noise such as popping sounds in the silent segment.

[0033] The processor 110 may include logic circuitry capable of signal extraction and / or correlation operations to extract offset voltage deviation in the silent segment of the output audio. The calibration module 200 may include at least one adder to perform addition or subtraction operations on the offset voltage deviation and the initial audio to calibrate the initial audio. Optionally, the calibration module 200 may also include logic circuitry capable of implementing corresponding addition and / or subtraction functions to achieve these functions through logic control.

[0034] In the aforementioned audio driving circuit, the processor 110 can extract the offset voltage deviation in the silent segment of the output audio and send the offset voltage deviation to the calibration module 200. The calibration module 200 uses the offset voltage deviation to calibrate the initial audio and sends the obtained calibration signal to the driving module 300, so that the driving module 300 uses the calibration signal to drive the audio. This can eliminate noise such as popping sounds in the silent segment of the initial audio and improve the listening experience in a quiet environment. The process of calibrating the initial audio using the offset voltage deviation can be superimposed on the corresponding analog circuit, which can simplify the calibration process and improve calibration efficiency. The entire audio driving process does not require sampling of VCM (common mode voltage), which can simplify the corresponding circuit structure and reduce power consumption.

[0035] In one embodiment, reference Figure 3 As shown, the audio driving circuit also includes an analog-to-digital converter 121 and a first switching component (such as...). Figure 3 As shown in S11 and S12) and the second switch assembly (such as Figure 3 (As shown in S21 and S22); the input terminal of the analog-to-digital converter 121 is connected to the output terminal of the drive module 300 through the first switch assembly and the second switch assembly, respectively, and the output terminal is connected to the input terminal of the processor. It is used to acquire a first acquisition signal when the first switch assembly is turned on and send the first acquisition signal to the processor 110; and to acquire a second acquisition signal when the second switch assembly is turned on and send the second acquisition signal to the processor 110. The processor 110 is used to determine the offset voltage deviation based on the first acquisition signal and the second acquisition signal. The first acquisition signal is based on the common-mode voltage with a positive offset voltage deviation superimposed, and the second acquisition signal is based on the common-mode voltage with a negative offset voltage deviation superimposed. If the sign of the offset voltage deviation is positive, the positive offset voltage deviation is equal to the aforementioned offset voltage deviation, and the negative offset voltage deviation is equal to the opposite of the offset voltage deviation. The absolute values ​​of the positive and negative offset voltage deviations are equal, but their signs are opposite. By subtracting the second acquisition signal from the first acquisition signal, the common-mode voltage can be eliminated, resulting in twice the offset voltage deviation. This allows the processor 110 to quickly and accurately determine the offset voltage deviation based on the first and second acquisition signals.

[0036] In this embodiment, the processor 110 can determine the offset voltage deviation based on the first and second acquisition signals through simple addition and subtraction operations, resulting in a relatively simple calculation process. The first and second acquisition signals are digital signals converted by the analog-to-digital converter 121. That is, the analog-to-digital converter 121 converts each acquired signal into a corresponding digital signal (such as the first and second acquisition signals) before sending it to the processor 110 for calculation. This further simplifies the subsequent process by which the processor 110 determines the offset voltage deviation based on the first and second acquisition signals, which are represented in digital signal form.

[0037] Optionally, the first switch assembly and the second switch assembly can be connected to the processor 110 respectively, so that the processor 110 controls the on / off state of the first switch assembly and the second switch assembly according to specific signal acquisition requirements.

[0038] The aforementioned first and second switching components are used to control the on / off state of the signal acquisition paths corresponding to the output terminals of the drive module 300, respectively. The inventors discovered that in each signal acquisition path corresponding to the output terminal of the drive module 300, the common-mode voltage VCM is often fixed. Other components in the output audio (such as offset voltage deviation) can be inverted by swapping input paths and / or time-division multiplexing. Based on this discovery, this embodiment can acquire the first acquisition signal VCM+V' when the first switching component is on, and acquire the second acquisition signal VCM-V' when the second switching component is on, where V' represents other components in the signals acquired by each signal acquisition path besides the common-mode voltage VCM. After obtaining the acquisition signals acquired when the first and second switching components are respectively on, relatively simple operations such as addition and subtraction of the first and second acquisition signals can eliminate the common-mode voltage VCM in the entire acquisition signal, obtaining the other components.

[0039] Specifically, the processor 110 is used to extract the DC component of the first acquired signal to obtain a first DC signal, and to extract the DC component of the second acquired signal to obtain a second DC signal, so that the extracted first DC signal and second DC signal only include the common-mode voltage VCM and the offset voltage deviation Vos. Then, the offset voltage deviation is determined based on the first DC signal and the second DC signal. The offset voltage deviation can be obtained by performing simple addition and subtraction operations on the first DC signal and the second DC signal, which can simplify the process of determining the offset voltage deviation and thus simplify the circuit structure for obtaining the offset voltage deviation.

[0040] Optionally, the processor 110 can perform noise reduction processing such as low-pass filtering on the first acquired signal, extract a first DC signal based on the noise-reduced first acquired signal, perform noise reduction processing such as low-pass filtering on the second acquired signal, and extract a second DC signal based on the noise-reduced second acquired signal, so as to ensure the validity of the obtained first DC signal and second DC signal.

[0041] Optionally, the first DC signal includes: data1=VCM+Vos, the second DC signal includes: data2=VCM-Vos; the offset voltage deviation includes: Vos=(data1-data2) / 2; where data1 represents the first DC signal, data2 represents the second DC signal, VCM represents the common-mode voltage, and Vos represents the offset voltage deviation.

[0042] Specifically, such as Figure 3 As shown, the driving module 300 includes a first audio terminal for outputting a positive output signal OUTP and a second audio terminal for outputting a negative output signal OUTN; the first switching assembly includes a first sub-switch S11 and a second sub-switch S12, and the second switching assembly includes a third sub-switch S21 and a fourth sub-switch S22; the first input terminal of the analog-to-digital converter 121 is connected to the second audio terminal through the first sub-switch S11 and to the first audio terminal through the third sub-switch S21, the second input terminal is connected to the first audio terminal through the second sub-switch S12, and to the second audio terminal through the fourth sub-switch S22. Figure 3 As shown, when the first and second switching components switch, i.e., when the first sub-switch S11 and the second sub-switch S12 are turned on, and then switch to the third sub-switch S21 and the fourth sub-switch S22, the analog-to-digital converter 121 switches its input path, i.e., it switches from the first signal acquisition path connected by the first switching component to the second signal acquisition path. This allows for rapid switching between the first and second signal acquisition paths using a simple switching structure. In the first acquisition signal corresponding to the first signal acquisition path and the second acquisition signal corresponding to the second signal acquisition path, the common-mode voltage VCM remains constant, while the offset voltage deviation Vos is inverted. This means that the first acquisition signal corresponding to the first signal acquisition path includes a positive offset voltage deviation, and the second acquisition signal corresponding to the second signal acquisition path includes a negative offset voltage deviation. This allows the processor 110 to efficiently obtain the offset voltage deviation Vos using simple addition and subtraction logic.

[0043] In one embodiment, reference Figure 4As shown, the audio driving circuit further includes a digital-to-analog converter 123; the calibration module 200 includes a first adder 210 and a second adder 220; the input terminal of the digital-to-analog converter 123 is connected to the initial audio, the first output terminal is connected to the first input terminal of the first adder 210, and the second output terminal is connected to the first input terminal of the second adder 220; the second input terminal of the first adder 210 is connected to the output terminal of the processor 110, and the output terminal is connected to the first input terminal of the driving module 300; the second input terminal of the second adder 220 is connected to the output terminal of the processor 110, and the output terminal is connected to the second input terminal of the driving module 300. After the digital-to-analog converter 123 converts the initial audio into an analog signal, its first output terminal is used to output positive audio information INP, and its second output terminal is used to output negative audio information INN. In this way, the first adder 210 can perform addition and / or subtraction operations on the positive audio information INP to calibrate the positive audio information INP and obtain a first calibration signal. The second adder 220 can perform addition and / or subtraction operations on the negative audio information INN to calibrate the negative audio information INN and obtain a second calibration signal. The first calibration signal and the second calibration signal constitute the calibration signal output by the calibration module 200.

[0044] Specifically, the initial audio can be a digital signal, and the silent segment is the low-level (e.g., level 0) segment of the corresponding digital signal. When the processor 110 acquires the offset voltage deviation, it can control the digital-to-analog converter 123 to stop working, that is, not to perform digital-to-analog conversion on the initial audio. The processor acquires the first and second acquisition signals in the low-level segment of the digital signal, determines the offset voltage deviation, and pre-stores the offset voltage deviation. After obtaining the offset voltage deviation, the processor 110 can turn off the analog-to-digital converter 121 and turn on the digital-to-analog converter 123. It can also simultaneously start the first adder 210 and the second adder 220, sending the pre-stored offset voltage deviation to the first adder 210 and the second adder 220 respectively. This causes the digital-to-analog converter 123 to convert the initial audio into the corresponding analog audio signal. The positive audio information INP corresponding to the analog audio signal is sent to the first adder 210, and the negative audio information INN is sent to the second adder 220. The first adder 210 performs addition and / or subtraction operations on the received positive audio information INP according to the offset voltage deviation, and the second adder 220 performs addition and / or subtraction operations on the received negative audio information INN according to the offset voltage deviation, so as to calibrate the positive audio information INP and the negative audio information INN respectively, enabling the drive module to perform more accurate drive operations. Similarly, processor 110 can turn off digital-to-analog converter 123 and turn on analog-to-digital converter 121 during the silent segment of the initial audio (corresponding to the low-level segment of the digital signal) to acquire the first and second acquisition signals to determine the offset voltage deviation and pre-store the offset voltage deviation. After obtaining the offset voltage deviation, processor 110 turns off analog-to-digital converter 121 and turns on digital-to-analog converter 123, so that digital-to-analog converter 123 converts the initial audio into the corresponding analog audio signal. Positive audio information INP corresponding to the analog audio signal is sent to first adder 210, and negative audio information INN is sent to second adder 220. First adder 210 and second adder 220 respectively perform addition and / or subtraction operations on the received audio information according to the offset voltage deviation to calibrate the corresponding audio signals respectively.

[0045] Optionally, the operation process of the audio driver circuit can be referred to Figure 5 As shown, it includes: S151, the processor determines whether the offset voltage deviation is obtained. If yes, proceed to step S161; otherwise, proceed to step S152. S152, a low-level segment in the digital signal turns off the digital-to-analog converter and turns on the analog-to-digital converter; S153, turn on the first switch component, turn off the second switch component, and the analog-to-digital converter acquires the first acquisition signal; S154, The processor acquires the first DC signal from the first acquisition signal; S155, turn on the second switch assembly, turn off the first switch assembly, and the analog-to-digital converter acquires the second acquisition signal; S156, The processor acquires the second DC signal from the second acquisition signal; S157, The processor performs a subtraction operation on the first DC signal and the second DC signal to obtain the calculation result; S158, the processor determines the sign bit of the operation result and marks the operation result according to the sign bit to obtain the accurate offset voltage deviation for storage; for example, when the operation result is greater than 0, the sign bit is marked as 0, otherwise the sign bit is marked as 1, so as to identify the positive or negative sign of the operation result by the sign bit. S161, turn off the analog-to-digital converter and turn on the digital-to-analog converter. The adder reads the offset voltage deviation in the low-level segment of the digital signal and calibrates the corresponding audio signal. S162, input the high-level segment of the digital signal to enable the corresponding audio playback device to play sound.

[0046] Optionally, if the processor includes multiple storage bits for storing offset voltage deviations, the operation of the audio drive circuit after step S158 may further include: S159, feed back the previously calibrated memory bits to the adder, and repeat steps S151 to S158 until each memory bit of the processor has the latest offset voltage deviation, that is, each memory bit has been calibrated.

[0047] In one example, reference Figure 6 As shown, the driving module 300 includes a first MOSFET MP1, a second MOSFET MP2, a third MOSFET MP3, a fourth MOSFET MN1, a fifth MOSFET MN2, a first amplifier 311, and a second amplifier 312; (Reference) Figure 7 As shown: the first adder 210 may include a first logic control terminal and a second logic control terminal, and the second adder 220 may include a third logic control terminal and a fourth logic control terminal. Further, the first adder 210 may also include two output terminals (one of which may be represented by S and the other by D) and at least one input terminal (such as IN); the second adder 220 may also include two output terminals (one of which may be represented by S and the other by D) and at least one input terminal (such as IN).

[0048] The gate of the first MOSFET MP1 is connected to one input terminal of the first adder 210 to receive the positive audio information INP output by the digital-to-analog converter 123. Its source is connected to the first output terminal S (one output terminal of the first adder 210), the source of the second MOSFET MP2, and the drain of the third MOSFET MP3. The drain is connected to the second output terminal D (the other output terminal of the first adder 210), the drain of the fourth MOSFET MN1, and the first input terminal of the first amplifier 311. The gate of the second MOSFET MP2 is connected to one input terminal of the second adder 220 to receive the negative audio information INN from the DAC. Its source is connected to the first output terminal S (one input terminal of the second adder 220), the drain of the third MOSFET MP3, and the drain of the fourth MOSFET MN1. The first output terminal of the second amplifier 311 is connected to the second output terminal D (another input terminal of the second adder 220), the drain of the fifth MOS transistor MN2, and the second input terminal of the first amplifier 311, respectively. The gate of the third MOS transistor MP3 is connected to the internal reference voltage VB, and the source is connected to the external power supply terminal VDDH. The gate of the fourth MOS transistor MN1 is connected to the gate of the fifth MOS transistor MN2, and the source is grounded. The source of the fifth MOS transistor MN2 is grounded. The first output terminal of the first amplifier 311 is connected to the first input terminal of the second amplifier 312, and the second output terminal is connected to the second input terminal of the second amplifier 312. The first output terminal of the second amplifier 312 is the first audio terminal, outputting a positive output signal OUTP, and the second output terminal is the second audio terminal, outputting a negative output signal OUTN.

[0049] Optionally, such as Figure 6 As shown, the gates of the fourth MOSFET MN1 and the fifth MOSFET MN2 are also connected to a common-mode feedback level terminal, and the corresponding common-mode feedback level is a DC level. The first amplifier 311 and the second amplifier 312 may also include a power supply terminal and a ground terminal. The power supply terminals of both are connected to an external power supply terminal VDDH, and the ground terminals are both grounded. Optionally, the type of each MOSFET can be selected according to specific requirements, and the corresponding connection relationship can be adaptively adjusted to achieve advantages such as high reliability and / or small size while realizing the corresponding driving function. For example, the first MOSFET MP1, the second MOSFET MP2, and the third MOSFET MP3 can be PMOS transistors to simplify the circuit structure; the fourth MOSFET MN1 and the fifth MOSFET MN2 can be NMOS transistors to reduce their occupied area, etc. Figure 6The driver module 300 shown includes a three-stage operational amplifier (OP). The input stage (first stage) includes a first MOSFET MP1, a second MOSFET MP2, a third MOSFET MP3, a fourth MOSFET MN1, and a fifth MOSFET MN2. This input stage connects to two adders (e.g., the first adder and the second adder). Each adder is controlled by 8 bits of data. The highest bit indicates the enable of the adder, and the lower 7 bits (6:0) indicate the data size. Enabling each bit is equivalent to connecting a small MOSFET in parallel with the input MOSFET (e.g., the first MOSFET MP1 or the second MOSFET MP2), thus changing the size of the corresponding MOSFET. This is equivalent to adding an extra signal at the input ports INP / INN, effectively performing addition and / or subtraction operations. The second and third stages each include an amplifier to amplify the corresponding output signal.

[0050] The driver module 300 provided in this example uses multiple MOSFETs and amplifiers for audio driving, offering high reliability and excellent driving performance.

[0051] In one example, reference Figure 7 As shown, each adder (such as the first adder 210 and the second adder 220) includes multiple logic control units connected in parallel. Figure 7 The first logic control unit is outlined with a dashed line. Each logic control unit includes two logic control terminals. Each logic control terminal is used to receive the encoded signal sent by the processor 110 and control the channels of each MOS transistor in the driver module according to the corresponding encoded signal to calibrate the initial audio. Specifically, each adder includes one logic control terminal CTTLH and another logic control terminal CTTLL. One logic control terminal CTTLH can include a 9-bit signal, such as... Figure 7 As shown, the logic control terminal CTTLH can include multiple high-order control bits, such as CTTLH<1:0>, CTTLH<2:1>, ..., CTTLH<8:7>; Figure 7 Eight logic control units are shown. One logic control terminal CTTLH of the adder includes the high-order control bits CTTLH<1:0> of the first logic control unit, CTTLH<2:1> of the second logic control unit, ..., and the eighth logic control terminal CTTLH<8:7>. Another logic control terminal CTTLL of the adder can include a 16-bit signal. This logic control terminal CTTLL can be... Figure 7 The CTTLL<15:0> corresponding to each logic control unit in the adder. Optionally, one logic control terminal CTTLH and another logic control terminal CTTLL of the adder control the channels of each MOS transistor in the drive module 300 to calibrate the initial audio. Optionally, as Figure 7 As shown, the logic control terminal includes multiple control bits, which control the on / off state of the corresponding MOSFETs. These control bits include at least one low-order control bit (e.g., ...). Figure 7 CTTLL<15:0> etc. Figure 8 CTTLL <0> (etc.) and at least one high-order control bit (such as Figure 7 CTTLH<1:0> etc. Figure 8 CTTHL <1> (etc.). The control bits have a corresponding relationship with the ports provided by the relevant MOS transistors in the logic control unit. For example, the control bits can correspond one-to-one with each port, etc.

[0052] Specifically, refer to Figure 8 As shown, the logic control unit includes multiple MOS transistor groups connected in parallel; each MOS transistor group is connected to two high-order control bits and one low-order control bit corresponding to the encoded signal, that is, two high-order control bits and one low-order control bit generated by the processor 110 during encoding, to control the on / off state of the corresponding MOS group, realize the parallel on / off state of the corresponding MOS transistor (such as the eighth MOS transistor MP8) and the input MOS transistor (such as the first MOS transistor MP1 or the second MOS transistor MP2), and realize the corresponding addition / or subtraction operation. Figure 8 The first MOS transistor group has been outlined with a dashed line. Each MOS transistor group is connected to two high-order control bits of the code. For example, the gate of the sixth MOS transistor MP6 in the first MOS transistor group is connected to a high-order control bit CTTLH. <1> The gate of the ninth MOSFET MP9 is connected to another high-order control bit CTTLH. <0> And a low-level control bit, such as the gate of the seventh MOSFET MP7 in the first MOSFET group being connected to a low-level control bit CTTLL. <0> This controls the parallel connection between the eighth MOSFET MP8 and the input MOSFET (such as the first MOSFET MP1 or the second MOSFET MP2). Optionally, in the logic control unit, the number of MOSFET groups is equal to the total number of low-order control bits, which is 16, so that each low-order control bit can correspond to a MOSFET group, specifically the gate of the seventh MOSFET MP7 in the corresponding MOSFET group. A MOSFET group can correspond to two high-order control bits, such as... Figure 8 In the first MOSFET group, the gate of the sixth MOSFET MP6 corresponds to a high-order control bit CTTLH. <1> The gate of the ninth MOSFET MP9 corresponds to another high-order control bit, CTTLH. <0> Wait a minute. Here. Figure 8 for Figure 7 The diagram shows the specific structure of each logic control unit. Figure 7 The high-order control bits of a logic control unit may include Figure 8 The two high-order control bits shown are as follows: Figure 7 The CTTLH<1:0> in the middle includes Figure 8CTTLH in <1> and CTTLH <0> . Figure 7 The low-order control bits CTTLL<15:0> in the code include 16 bits of signal; please refer to [reference needed]. Figure 8 As shown, CTTLL<15:0> includes CTTLL <0> ,CTTLL <1> ..., CTTLL <15> .

[0053] Optionally, refer to Figure 9 As shown, the MOSFET group includes a sixth MOSFET MP6, a seventh MOSFET MP7, an eighth MOSFET MP8, and a ninth MOSFET MP9. The gate of the sixth MOSFET MP6 is connected to a high-order control bit, its source is connected to an output terminal S of the corresponding adder, and its drain is connected to the source of the seventh MOSFET MP7. The gate of the seventh MOSFET MP7 is connected to a low-order control bit, and its drain is connected to the source of the eighth MOSFET MP8 and the drain of the ninth MOSFET MP9. The gate of the eighth MOSFET MP8 is connected to the input signal IN, which is one output signal of the DAC (such as positive audio information INP or negative audio information INN), and its drain is connected to the other output terminal D of the corresponding adder. The gate of the ninth MOSFET MP9 is connected to another high-order control bit, and its source is connected to an output terminal S. The sixth MOSFET MP6, the seventh MOSFET MP7, and the ninth MOSFET MP9 together control the connection or disconnection between the output terminal S of the eighth MOSFET MP8 and the source terminal of the input MOSFET (such as the first MOSFET MP1 or the second MOSFET MP2) to complete the conduction or disconnection of the parallel operation and complete the addition and subtraction operation.

[0054] like Figure 8 As shown, in each MOSFET group, the sixth MOSFET MP6, the seventh MOSFET MP7, and the ninth MOSFET MP9 together control the connection or disconnection between the output terminal S of the eighth MOSFET MP8 and the source terminal of the input MOSFET (such as the first MOSFET MP1 or the second MOSFET MP2) to complete the conduction or disconnection of the parallel operation and complete the addition and subtraction operation.

[0055] Specifically, the logic for each adder to perform the corresponding addition / or subtraction operation includes: the adder receives a first control logic signal and a second control logic signal from the processor, both of which are coded signals; the first control logic signal and the second control logic signal are connected to the control logic unit inside the adder, controlling the eighth MOS transistor MP8 of the corresponding MOS transistor group to turn on, which is equivalent to the first MOS transistor MP1 and the second MOS transistor MP2 on the drive circuit being connected in parallel with the corresponding MOS transistors, which is equivalent to superimposing a signal and equivalently completing the corresponding addition / or subtraction operation.

[0056] In the above audio driving circuit, the processor 110 can extract the offset voltage deviation from the silent segment of the output audio and send the offset voltage deviation to the calibration module 200. The calibration module 200 uses the offset voltage deviation to calibrate the silent segment in the initial audio and sends the obtained calibration signal to the driving module 300, so that the driving module 300 uses the calibration signal to drive the audio. This can eliminate noise such as popping sounds in the silent segment of the initial audio and improve the listening experience in a quiet environment. The process of calibrating the silent segment of the initial audio using the offset voltage deviation can be superimposed on the corresponding analog circuit, which can simplify the calibration process and improve calibration efficiency. The entire audio driving process does not require sampling of VCM (common-mode voltage), which can simplify the corresponding circuit structure and reduce power consumption. The driving module 300 uses simple devices such as multiple MOSFETs and amplifiers for audio driving, which has a simple structure, high reliability, and good driving effect. The calibration module 200 uses multiple parallel logic control units to perform logic control on the MOSFETs of the driving module 300 to realize addition and / or subtraction operations. Based on the simplified circuit structure, it can simplify the corresponding calculation process and reduce the power consumption generated by the calculation process. As can be seen, the above-mentioned audio driver circuit can improve the audio driving effect from many aspects, simplify the structure and driving process of the audio driver circuit, thereby reducing the corresponding power consumption and improving the playback quality of the corresponding audio playback device.

[0057] This application provides an audio driving method in a first aspect, characterized in that it includes: Extract the offset voltage deviation in the silent section of the output audio; The initial audio signal is calibrated using the offset voltage deviation to obtain a calibration signal; The calibration signal is used for audio driving.

[0058] In one embodiment, extracting the offset voltage deviation in the silent segment of the output audio includes: The first acquisition signal and the second acquisition signal are extracted sequentially from the silent segment of the output audio; the first acquisition signal is based on the common-mode voltage with a positive offset voltage deviation superimposed, and the second acquisition signal is based on the common-mode voltage with a negative offset voltage deviation superimposed. The offset voltage deviation is determined based on the first acquisition signal and the second acquisition signal.

[0059] Specifically, determining the offset voltage deviation based on the first acquired signal and the second acquired signal includes: Extract the DC component of the first acquired signal to obtain the first DC signal; Extract the DC component of the second acquired signal to obtain the second DC signal; The offset voltage deviation is determined based on the first DC signal and the second DC signal.

[0060] The above-described audio driving method can be implemented using the audio driving circuit provided in any of the above embodiments, and has all the beneficial effects of the audio driving circuit provided in any of the above embodiments, which will not be elaborated here.

[0061] This application provides an audio driver chip in a third aspect, including the audio driver circuit provided in any of the above embodiments.

[0062] The audio driver chip described above uses the audio driver circuit provided in any of the above embodiments to drive audio, which has a good driving effect and low power consumption during the audio driving process.

[0063] A fourth aspect of this application provides an audio playback device, including the audio driver chip described in any of the above embodiments.

[0064] In one embodiment, the audio playback device further includes a playback component; the first input terminal of the playback component is connected to a first audio terminal to receive a positive output signal from the driver module, and the second input terminal is connected to a second audio terminal to receive a negative output signal from the driver module, so that the playback component can play the corresponding audio.

[0065] The aforementioned playback components may include components such as speakers and / or loudspeakers. Specifically, the aforementioned audio playback device may refer to... Figure 10 As shown, the speaker 510 includes a first input terminal and a second input terminal. The first input terminal of the speaker 510 is connected to the first audio terminal of the audio driver chip, and the second input terminal is connected to the second audio terminal of the audio driver chip.

[0066] The aforementioned audio playback device uses the audio driver chip described in any of the above embodiments for audio driving. In the initial audio, noise such as popping sounds in the silent section is effectively eliminated, resulting in a higher playback effect. Furthermore, the structure and driving process of the audio driver chip are simplified, thereby improving the reliability of the corresponding audio driver and reducing power consumption. This improves the reliability of the audio playback device and reduces its power consumption. Although this application has been shown and described with respect to one or more implementations, equivalent variations and modifications will occur to those skilled in the art based on a reading and understanding of this specification and the accompanying drawings. This application includes all such modifications and variations and is limited only by the scope of the appended claims. In particular, with respect to the various functions performed by the aforementioned components, the terminology used to describe such components is intended to correspond to any component (unless otherwise indicated) that performs the specified function of said component (e.g., is functionally equivalent to it), even if structurally not equivalent to the disclosed structure performing the functions in the exemplary implementations of this specification shown herein.

[0067] That is, the above description is only an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural changes made using the content of this application’s specification and drawings, such as the combination of technical features between different embodiments, or direct or indirect application in other related technical fields, are similarly included within the patent protection scope of this application.

[0068] Furthermore, for structural elements with the same or similar characteristics, this application may use the same or different reference numerals for identification. In addition, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0069] The above description has been provided to enable any person skilled in the art to implement and use this application. Various details have been set forth in the above description for purposes of explanation. It should be understood that those skilled in the art will recognize that this application can be implemented without using these specific details. In other embodiments, well-known structures and processes will not be described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed herein.

Claims

1. An audio driver circuit, characterized in that, The audio driver circuit includes a processor, a calibration module, and a driver module; The processor is connected between the driver module and the calibration module, and is used to extract the offset voltage deviation from the silent segment of the audio output by the driver module, and send the offset voltage deviation to the calibration module; the silent segment is a low-level audio segment in the digital signal; The calibration module is connected between the processor and the driver module, and is used to receive the initial audio, calibrate the initial audio using the offset voltage deviation, obtain a calibration signal, and send the calibration signal to the driver module; The input terminal of the driving module is connected to the calibration module, and is used to drive the audio using the calibration signal and output the driven audio. The calibration module includes a first adder and a second adder; the driving module includes a first MOSFET, a second MOSFET, a third MOSFET, a fourth MOSFET, a fifth MOSFET, a first amplifier, and a second amplifier; the gate of the first MOSFET is connected to one input terminal of the first adder, and its source is connected to one output terminal of the first adder, the source of the second MOSFET, and the drain of the third MOSFET, respectively; its drain is connected to the other output terminal of the first adder, the drain of the fourth MOSFET, and the first input terminal of the first amplifier, respectively; the gate of the second MOSFET is connected to one input terminal of the second adder, its source is connected to one output terminal of the second adder, and its drain is connected to the other output terminal of the second adder, the drain of the fifth MOSFET, and the second input terminal of the first amplifier, respectively; the gate of the third MOSFET is connected to an internal reference voltage, and its source is connected to an external power supply terminal; the gate of the fourth MOSFET is connected to the gate of the fifth MOSFET, and its source is grounded; the source of the fifth MOSFET is grounded; the first output terminal of the first amplifier is connected to the first input terminal of the second amplifier, and the second output terminal is connected to the second input terminal of the second amplifier; the first output terminal of the second amplifier is a first audio terminal, and the second output terminal is a second audio terminal.

2. The audio driving circuit according to claim 1, characterized in that, The audio driver circuit also includes an analog-to-digital converter, a first switching component, and a second switching component; The input terminal of the analog-to-digital converter is connected to the output terminal of the drive module through the first switch assembly and the second switch assembly, respectively, and the output terminal is connected to the input terminal of the processor. It is used to acquire a first acquisition signal when the first switch assembly is turned on and send the first acquisition signal to the processor, and acquire a second acquisition signal when the second switch assembly is turned on and send the second acquisition signal to the processor. The first acquired signal is based on the common-mode voltage with a positive offset voltage deviation superimposed on it, and the second acquired signal is based on the common-mode voltage with a negative offset voltage deviation superimposed on it. The processor is used to determine the offset voltage deviation based on the first acquisition signal and the second acquisition signal.

3. The audio driving circuit according to claim 2, characterized in that, The processor is used to extract the DC component of the first acquired signal to obtain a first DC signal, extract the DC component of the second acquired signal to obtain a second DC signal, and determine the offset voltage deviation based on the first DC signal and the second DC signal.

4. The audio driving circuit according to claim 3, characterized in that, The first DC signal includes: data1 = VCM + Vos, and the second DC signal includes: data2 = VCM - Vos; the offset voltage deviation includes: Vos = (data1 - data2) / 2; where data1 represents the first DC signal, data2 represents the second DC signal, VCM represents the common-mode voltage, and Vos represents the offset voltage deviation.

5. The audio driving circuit of claim 2, wherein, The driving module includes a first audio terminal for outputting a positive output signal and a second audio terminal for outputting a negative output signal; the first switching component includes a first sub-switch and a second sub-switch, and the second switching component includes a third sub-switch and a fourth sub-switch; The first input terminal of the analog-to-digital converter is connected to the second audio terminal via the first sub-switch and to the first audio terminal via the third sub-switch. The second input terminal is connected to the second audio terminal via the fourth sub-switch and to the first audio terminal via the second sub-switch.

6. The audio driving circuit according to claim 2, wherein The audio driver circuit also includes a digital-to-analog converter; The input terminal of the digital-to-analog converter is connected to the initial audio, the first output terminal is connected to the first input terminal of the first adder, and the second output terminal is connected to the first input terminal of the second adder; the second input terminal of the first adder is connected to the output terminal of the processor, and the output terminal is connected to the first input terminal of the driver module; the second input terminal of the second adder is connected to the output terminal of the processor, and the output terminal is connected to the second input terminal of the driver module.

7. The audio driving circuit according to claim 1, characterized in that, Each adder includes multiple logic control units connected in parallel. Each logic control unit includes two logic control terminals. Each logic control terminal is used to receive the encoded signal sent by the processor to control the channel of each MOS transistor in the driving module and calibrate the initial audio.

8. The audio driving circuit according to claim 7, characterized in that, The logic control unit includes multiple MOS transistor groups connected in parallel; each MOS transistor group is connected to two high-order control bits and one low-order control bit corresponding to the encoded signal.

9. The audio driving circuit according to claim 8, characterized in that, The MOSFET group includes a sixth MOSFET, a seventh MOSFET, an eighth MOSFET, and a ninth MOSFET; The gate of the sixth MOS transistor is connected to a high-level control bit, its source is connected to one output terminal of the corresponding adder, and its drain is connected to the source of the seventh MOS transistor; the gate of the seventh MOS transistor is connected to a low-level control bit, and its drain is connected to the source of the eighth MOS transistor and the drain of the ninth MOS transistor; the gate of the eighth MOS transistor is connected to the offset voltage deviation, and its drain is connected to the other output terminal of the corresponding adder; the gate of the ninth MOS transistor is connected to another high-level control bit, and its source is connected to one output terminal of the corresponding adder.

10. An audio driving method, characterized in that, The audio driving method is implemented using the audio driving circuit according to any one of claims 1 to 9, including: Extract the offset voltage deviation in the silent section of the output audio; The initial audio is calibrated using the offset voltage deviation to obtain the calibration signal; The calibration signal is used for audio driving.

11. The audio driving method according to claim 10, characterized in that, The extraction of offset voltage deviation in the silent segment of the output audio includes: The first acquisition signal and the second acquisition signal are extracted sequentially from the silent segment of the output audio; the first acquisition signal is based on the common-mode voltage with a positive offset voltage deviation superimposed, and the second acquisition signal is based on the common-mode voltage with a negative offset voltage deviation superimposed. The offset voltage deviation is determined based on the first acquisition signal and the second acquisition signal.

12. The audio driving method according to claim 11, characterized in that, Determining the offset voltage deviation based on the first acquired signal and the second acquired signal includes: Extract the DC component of the first acquired signal to obtain the first DC signal; Extract the DC component of the second acquired signal to obtain the second DC signal; The offset voltage deviation is determined based on the first DC signal and the second DC signal.

13. An audio driver chip, characterized in that, Includes the audio driving circuit according to any one of claims 1 to 9.

14. An audio playback device, characterized in that, Includes the audio driver chip as described in claim 13.

15. The audio playback device according to claim 14, characterized in that, The audio playback device further includes a playback component; the first input terminal of the playback component is connected to a first audio terminal, and the second input terminal is connected to a second audio terminal.

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