Memory and method of manufacturing the same

Abstract

The application provides a memory and a manufacturing method thereof, the manufacturing method comprising: providing a substrate; forming a plurality of parallel first isolation structures extending along a first direction and a plurality of parallel first grooves extending along a second direction on the surface of the substrate; the first direction is perpendicular to the second direction; the depth of the first groove is less than the thickness of the substrate; the first isolation structure and the first groove divide the substrate into a plurality of channel columns; forming a word line structure covering the inner wall of the first groove; forming a storage structure on the surface of the channel column; removing part of the word line structure at the bottom of the first groove from the back of the substrate to form two word lines separated from each other in the first groove.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a memory and a method for manufacturing the same. Background Technology

[0002] With the continuous development of science and technology, memory is widely used in various electronic devices. Random Access Memory (RAM) is a volatile memory and a commonly used semiconductor memory device in computers.

[0003] Random access memory (RAM) consists of multiple repeating memory cells. Each memory cell mainly consists of a transistor and a capacitor controlled by the transistor, and each memory cell is electrically connected to the others via word lines and bit lines. However, this type of RAM has problems such as large memory cell area, complex wiring, and difficult manufacturing process. Summary of the Invention

[0004] In view of this, embodiments of this application provide a memory and a method for manufacturing the same.

[0005] In a first aspect, embodiments of this application provide a method for manufacturing a memory, the method comprising:

[0006] Provide substrate;

[0007] A plurality of mutually parallel first isolation structures extending along a first direction and a plurality of mutually parallel first trenches extending along a second direction are formed on the surface of the substrate; the first direction is perpendicular to the second direction; the depth of the first trenches is less than the thickness of the substrate; the first isolation structures and the first trenches divide the substrate into a plurality of channel pillars;

[0008] Forming a character line structure covering the inner wall of the first trench;

[0009] A storage structure is formed on the surface of the channel column;

[0010] A portion of the word line structure at the bottom of the first trench is removed from the back side of the substrate to form two word lines that are separated from each other within the first trench.

[0011] In some embodiments, the above-described word line structure covering the inner wall of the first trench includes:

[0012] A gate oxide layer is formed covering the inner wall of the first trench;

[0013] Form a gate conductive layer covering the gate oxide layer;

[0014] An insulating material is filled between the gate conductive layers in the first trench to form a second isolation structure.

[0015] In some embodiments, removing a portion of the word line structure from the bottom of the first trench on the back side of the substrate to form two word lines separated from each other within the first trench includes:

[0016] Remove the portion of the substrate located below the word line structure until the word line structure is exposed from the back side of the substrate;

[0017] The word line structure at the bottom of the first trench is removed from the back side of the substrate to form two word lines that are separated from each other within the first trench.

[0018] In some embodiments, the method further includes:

[0019] The recess formed after removing part of the letter line structure at the bottom of the first trench is filled with insulating material.

[0020] In some embodiments, removing the portion of the substrate located below the word line structure until the word line structure is exposed from the back side of the substrate includes:

[0021] The back side of the substrate is thinned until the word line structure is exposed from the back side of the substrate.

[0022] In some embodiments, removing the portion of the substrate located below the word line structure until the word line structure is exposed from the back side of the substrate includes:

[0023] An opening is formed at a corresponding position at the bottom of the first trench on the back side of the substrate, and the bottom of the word line structure is exposed through the opening.

[0024] In some embodiments, the method further includes:

[0025] Multiple third isolation structures are formed along the second direction, running through the same straight line; the third isolation structures are used to divide the channel pillar into conductive channels for two transistors.

[0026] In some embodiments, the plurality of third isolation structures formed along the second direction and passing through the same straight line of the channel post include:

[0027] Multiple second grooves are formed along the second direction, penetrating the channel column on the same straight line;

[0028] The third isolation structure is formed in the second trench, wherein the third isolation structure has an air cavity.

[0029] In some embodiments, the method further includes:

[0030] The first end of the conductive channel is doped to form the source of a transistor;

[0031] The second end of the conductive channel is doped to form the drain of the transistor.

[0032] In some embodiments, forming a storage structure on the surface of the channel post includes:

[0033] A storage capacitor is formed on the source surface of the transistor.

[0034] In some embodiments, the above-described doping of the second end of the conductive channel to form the drain of the transistor includes:

[0035] The back side of the substrate is thinned;

[0036] The second end of the conductive channel is doped to form the drain of the transistor.

[0037] In some embodiments, the method further includes:

[0038] On the back side of the substrate, a bit line is formed that connects to the drain of the transistor.

[0039] In some embodiments, forming a bit line connecting the drain of the transistor on the back side of the substrate includes:

[0040] A bit line contact structure is formed on the surface of the drain electrode;

[0041] The bit line is formed on the bit line contact structure.

[0042] On the other hand, embodiments of this application also provide a memory, the memory comprising:

[0043] Substrate;

[0044] Located on the surface of the substrate, there are a plurality of mutually parallel first isolation structures extending along a first direction, and a plurality of mutually parallel first trenches extending along a second direction; the first direction is perpendicular to the second direction; the depth of the first trenches is less than the thickness of the substrate; the first isolation structures and the first trenches divide the substrate into a plurality of channel pillars;

[0045] A character line structure is located within the first groove; the character line structure includes two separate character lines located on the sidewall of the first groove.

[0046] Storage structure located on the surface of the channel post.

[0047] In some embodiments, the word line structure further includes:

[0048] A gate oxide layer is located between the sidewall of the first trench and the word line;

[0049] The second isolation structure is located between the two word lines in the first trench.

[0050] In some embodiments, the memory further includes:

[0051] Multiple third isolation structures running along the second direction and on the same straight line through the channel post; the third isolation structures divide the channel post into conductive channels for two transistors.

[0052] In some embodiments, the third isolation structure has an air cavity.

[0053] In some embodiments, the trench column includes:

[0054] The source of the transistor located at the first end of the conductive channel;

[0055] The drain of the transistor located at the second end of the conductive channel.

[0056] In some embodiments, the storage structure includes:

[0057] A storage capacitor is located on the surface of the source electrode and connected to the source electrode.

[0058] In some embodiments, the memory further includes:

[0059] Bit lines are located on the back side of the substrate and are connected to the drain.

[0060] In some embodiments, the memory further includes:

[0061] A bit line contact structure is located on the surface of the drain electrode, and the bit line contact connects the drain electrode and the bit line.

[0062] The memory manufacturing method provided in this application forms two separate word lines in a first trench and forms a memory structure on the surface of the trench pillars. In this way, on the one hand, by forming vertically aligned transistors, the area of ​​the memory cell is greatly reduced, and the structural layout of the memory is optimized; on the other hand, removing part of the word line structure from the back of the substrate makes it easier to completely separate the word lines on the two sidewalls of the first trench, reducing short-circuit problems and improving the reliability of the manufacturing process. Attached Figure Description

[0063] Figure 1A A schematic diagram of a transistor structure provided in an embodiment of this application;

[0064] Figure 1B A schematic diagram of a transistor structure provided in an embodiment of this application;

[0065] Figure 1C A schematic diagram of a storage unit provided in an embodiment of this application;

[0066] Figure 1D A schematic diagram of a storage cell array provided in an embodiment of this application;

[0067] Figure 2 A flowchart illustrating the steps of a method for manufacturing a memory according to an embodiment of this application;

[0068] Figures 3A to 3G A schematic diagram of the manufacturing process of a memory provided in an embodiment of this application;

[0069] Figures 4A to 4G This application provides a schematic diagram of a process for forming a word line structure.

[0070] Figure 5A and Figure 5B A schematic diagram of a process for forming a third isolation structure is provided in an embodiment of this application;

[0071] Figure 6A and Figure 6B A schematic diagram of a process for forming a third isolation structure and an air cavity is provided for an embodiment of this application;

[0072] Figure 7 A schematic diagram of the structure for forming the source and drain of a transistor is provided in an embodiment of this application;

[0073] Figure 8 This is a schematic diagram of a structure forming a storage structure provided in an embodiment of this application;

[0074] Figure 9A and Figure 9B A schematic diagram of a process for forming the drain of a transistor, provided for an embodiment of this application;

[0075] Figure 10A and Figure 10B A schematic diagram of a process for forming two mutually separated character lines is provided for an embodiment of this application;

[0076] Figure 11 A schematic diagram of a structure for forming a word line structure exposed from the back side of a substrate, provided for an embodiment of this application;

[0077] Figure 12 A schematic diagram of a structure for forming a word line structure exposed from the back side of a substrate, provided for an embodiment of this application;

[0078] Figure 13This is a schematic diagram of a structure provided in this application for filling an insulating material into a recess formed after removing part of the word line structure;

[0079] Figure 14 This is a schematic diagram of a structure for forming a bit line, provided in an embodiment of this application.

[0080] Figure 15 This is a schematic diagram of a structure for forming a bit line contact structure provided in an embodiment of this application;

[0081] Figure 16A and Figure 16B A schematic diagram of the structure of a memory provided in an embodiment of this application;

[0082] Figure 17 This application provides a schematic diagram of a word line structure in a memory.

[0083] Figure 18A and Figure 18B This is a schematic diagram of a third isolation structure in a memory provided in an embodiment of this application;

[0084] Figure 19 This is a schematic diagram of the structure of an air cavity in a memory provided in an embodiment of this application;

[0085] Figure 20 A schematic diagram of the source and drain of a transistor in a memory provided for an embodiment of this application;

[0086] Figures 21A to 21C This is a schematic diagram of the structure of a storage capacitor in a memory provided in an embodiment of this application;

[0087] Figure 22A and Figure 22B A schematic diagram of the arrangement of storage capacitors in a memory provided in an embodiment of this application;

[0088] Figure 23 This application provides a schematic diagram of the structure of a bit line in a memory.

[0089] Figure 24 This is a schematic diagram of a bit line contact structure in a memory provided in an embodiment of this application. Detailed Implementation

[0090] To facilitate understanding of this application, exemplary embodiments disclosed herein will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of this application are shown in the drawings, it should be understood that this application can be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of this application and to fully convey the scope of the disclosure of this application to those skilled in the art.

[0091] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In some embodiments, to avoid confusion with this application, some technical features well-known in the art are not described; that is, not all features of the actual embodiments may be described herein, nor well-known functions and structures may be described in detail.

[0092] Generally, terms can be understood at least in part from their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a" or "described" can also be understood to convey either a singular or a plural usage, depending at least in part on the context. Additionally, the use of "based on" can be understood to not necessarily convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, also depending at least in part on the context.

[0093] Unless otherwise defined, the terminology used herein is intended only to describe particular embodiments and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0094] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solution of this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0095] In some embodiments, the transistors of the memory include planar transistors and buried channel array transistors (BCATs). However, regardless of whether it is a planar transistor or a buried channel array transistor, in terms of structure, the source and drain are located on the horizontal sides of the gate.

[0096] like Figure 1A The diagram shown is a schematic of a planar transistor. Figure 1B This is a schematic diagram of a buried-channel transistor. It should be understood that the dimensional proportions of the structures in the diagram may differ from the actual structure in order to ensure clarity. The source 101 and drain 102 of the transistor are located on opposite sides of the gate 103. Thus, the source 101 and drain 102 occupy different positions on the horizontal plane, resulting in a larger horizontal area for both planar and buried-channel transistors. Furthermore, since the capacitor 104 and bit line 105 are on the same side of the transistor, they are both located on one side of the substrate during fabrication. The contact line of capacitor 104 needs to pass through bit line 105, increasing the overall fabrication complexity and placing extremely high demands on photolithography and alignment.

[0097] Figure 1C This is a schematic diagram of a storage cell in a random access memory. Figure 1D This is a schematic diagram of a memory cell array in a random access memory. Word lines control the switching on and off of transistors, bit lines are used to read and write to capacitors when the transistors are on, and one end of each capacitor is connected to a transistor, while the other end is grounded.

[0098] like Figure 2 As shown in the figure, this application embodiment provides a method for manufacturing a memory, the corresponding structure of which is as follows. Figures 3A to 3F As shown, the manufacturing method includes the following steps:

[0099] Step S10: Provide substrate 300;

[0100] Step S20: A plurality of mutually parallel first isolation structures 310 extending along a first direction and a plurality of mutually parallel first trenches 320 extending along a second direction are formed on the surface of the substrate 300; the first direction is perpendicular to the second direction; the depth of the first trenches 320 is less than the thickness of the substrate 300; the first isolation structures 310 and the first trenches 320 divide the substrate into a plurality of channel pillars 330.

[0101] Step S30: Form a character line structure 340 covering the inner wall of the first trench 320;

[0102] Step S40: Form a storage structure 350 on the surface of the channel post 330;

[0103] Step S50: Remove a portion of the word line structure 340 at the bottom of the first trench 320 from the back side of the substrate 300 to form two word lines 341 that are separated from each other within the first trench 320.

[0104] In this embodiment, the substrate 300 may be a semiconductor material such as silicon (Si) or germanium (Ge). In some embodiments, the substrate 300 may also be doped, or may include doped and undoped regions. The side of the substrate 300 used to form the first trench 320 may serve as the surface of the substrate 300, and the side opposite to the surface of the substrate 300 may serve as the back surface of the substrate 300.

[0105] like Figure 3A As shown, a plurality of first isolation structures 310 extending along a first direction are formed on the surface of the substrate 300. The first direction is parallel to the surface of the substrate 300 and coincides with the Y direction; as shown... Figure 3BAs shown, the thickness of the first isolation structure 310 in the Z direction is less than or equal to the thickness of the substrate 300. Optionally, a mask for the first isolation structure 310 is formed on the substrate 300 using photolithography, and then the substrate 300 is etched through the mask using etching to form corresponding isolation trenches for the first isolation structure 310. The first isolation structure 310 is then formed in the isolation trenches using deposition, and the surface of the substrate 300 is planarized using chemical mechanical polishing (CMP). The materials of the first isolation structure 310 include, but are not limited to, silicon dioxide (SiO2), spin-on dielectric (SOD), silicon nitride (Si3N4), and silicon oxynitride (SiON). It is worth noting that in this embodiment, the etching of the substrate is partial etching in the Z direction, and the etching process does not penetrate the substrate. Generally, etching processes can be divided into dry etching and wet etching. Dry etching can include ion milling etching, plasma etching, reactive ion etching, or laser ablation; wet etching uses solvents or solutions, such as acid or alkali solutions, for etching. Deposition processes include, but are not limited to, chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD).

[0106] like Figure 3C As shown, a plurality of mutually parallel first trenches 320 extending along a second direction are formed on the surface of the substrate 300. The second direction is parallel to the surface of the substrate 300, coincides with the X-direction, and is perpendicular to the first direction. Figure 3DAs shown, the depth of the first trench 320 in the Z direction is less than the thickness of the substrate 300. Optionally, a mask corresponding to the first trench 320 is formed on the substrate 300 using a photolithography process, and then the substrate 300 is etched through the mask using an etching process to form the first trench 320. The first trench 320 and the first isolation structure 310 divide the substrate 300 into multiple channel pillars 330. The length direction of the channel pillars 330 is consistent with the Z direction, so that the two ends of the channel pillars 330 close to the surface and back of the substrate 300 can respectively form the source and drain of the transistors in the memory, that is, the direction of the transistors in the memory is perpendicular to the surface of the substrate 300. As a result, the vertical transistors occupy a smaller area, so the density of memory cells per unit area is greater, and the different structures connected to the source and drain in the memory can be designed on two opposite sides of the substrate, thereby optimizing the structural layout of the memory.

[0107] like Figure 3E As shown, a word line structure 340 covering the inner wall of the first trench 320 is formed in the first trench 320. The word line structure 340 covers the inner wall of the first trench 320 and extends along the X direction. The word line structure 340 may include structures such as a gate oxide layer and a gate conductive layer. Optionally, a gate oxide layer is formed on the inner wall of the first trench through a thermal oxidation process, and then a gate conductive layer is formed on the gate oxide layer through a deposition process. The material of the gate conductive layer includes, but is not limited to, one or more of tungsten (W), titanium nitride (TiN), copper (Cu), and silver (Ag). Thus, by removing a portion of the word line structure 340 located at the bottom of the first trench 320 in a subsequent process, two separate word lines located on the sidewall of the first trench 320 can be formed, thereby forming two transistors corresponding to one channel pillar 330, further improving the memory cell density.

[0108] like Figure 3F As shown, a memory structure 350 is formed on the surface of the channel pillar 330. The direction of the channel pillar 330 is consistent with the Z-direction, so the source and drain of a transistor can be formed at both ends of the channel pillar 330, respectively, meaning the direction of the transistor in the memory is perpendicular to the substrate surface. The memory structure 350 can be formed on the surface of either end of the channel pillar 330 and connected to the source or drain of the transistor. The other end of the channel pillar 330 can be used to form bit lines or other structures. It is worth noting that, in this embodiment, the word lines on both sides of a channel pillar 330 can both be used to control the transistor corresponding to that channel pillar. A channel pillar 330 can also be used to form two corresponding transistors, each controlled by a word line in the first trench on both sides. Therefore, there can also be other isolation structures in the middle of a channel pillar 330, and one end of the channel pillar can form two sources or drains, and two corresponding memory structures 350. In a random access memory, the memory structure 350 can be a capacitor.

[0109] like Figure 3G As shown, a portion of the word line structure 340 located at the bottom of the first trench 320 is removed from the back side of the substrate 300, forming two separate word lines 341 within the first trench 320. (Reference) Figure 3E Because the etching process involves a certain angle during the formation of the first trench 320, the width of the first trench 320 gradually decreases downwards from the surface of the substrate 300, resulting in a thicker gate conductive layer deposited at the bottom of the first trench 320 in the word line structure 340. If a portion of the word line structure 340 at the bottom of the first trench 320 is removed from the front side of the substrate 300, the gate conductive layer at the bottom is difficult to completely disconnect, leading to a short circuit between the two word lines 341 on the sidewall of the first trench 320, causing the memory to malfunction. Therefore, in this embodiment, a portion of the word line structure 340 at the bottom of the first trench 320 is removed from the back side of the substrate 300, thereby forming two completely separated word lines 341 on the sidewall of the first trench 320. This avoids the short circuit problem caused by the residual gate conductive layer at the bottom of the first trench 320 and improves the reliability of the manufacturing process.

[0110] In some embodiments, such as Figures 4A to 4G As shown, the word line structure 340 forming the inner wall of the first groove 320 includes:

[0111] A gate oxide layer 321 is formed covering the inner wall of the first trench 320;

[0112] A gate conductive layer 322 is formed covering the gate oxide layer 321;

[0113] An insulating material is filled between the gate conductive layers 322 in the first trench 320 to form a second isolation structure 323.

[0114] In the embodiments of this application, such as Figure 4A As shown, a gate oxide layer 321 is formed covering the inner wall of the first trench 320. Optionally, a gate oxide layer 321 of a target thickness is formed on the inner wall of the first trench 320 by a thermal oxidation process. The thermal oxidation process can be in-situ steam generation (ISSG), rapid thermal oxidation (RTO), etc.

[0115] like Figure 4BAs shown, a gate conductive layer 322 is formed covering the gate oxide layer 321. Optionally, the gate conductive layer 322 is formed on the gate oxide layer 321 covering the inner wall of the first trench 320 by a deposition process. The gate conductive layer 322 is used to form two completely separated word lines located on the sidewall of the first trench 320. It is worth noting that, in order to prevent leakage at the end of the subsequently formed word lines near the surface of the substrate 300, it is necessary to remove a portion of the gate conductive layer 322 with a first height h1 near the surface of the substrate 300, that is, the height of the gate conductive layer 322 in the Z direction is less than the depth of the first trench 320.

[0116] like Figure 4C As shown, the insulating dielectric material can be filled into the first trench 320, whose inner wall is covered with a gate oxide layer 321 and a gate conductive layer 322, through processes such as spin-coating an insulating dielectric. Figure 4D As shown, a portion of the spin-coated insulating dielectric material with a first height h1 near the surface of the substrate 300 is removed through processes such as etching to form a protective layer 324. The protective layer 324 is used to protect the remaining portion of the gate conductive layer 322 when the portion with the first height h1 is removed in subsequent processes.

[0117] like Figure 4E As shown, a portion of the gate conductive layer 322 with a first height h1 near the surface of the substrate 300 can be removed using processes such as selective etching. Due to the presence of the protective layer 324, etching only removes the portion of the gate conductive layer 322 located above the protective layer 324, resulting in the remaining gate conductive layer 322 having a height in the Z direction that is less than the depth of the first trench 320. Figure 4F As shown, the protective layer 324 can be removed by processes such as selective etching.

[0118] like Figure 4G As shown, an insulating material can be filled between the gate conductive layers 322 in the first trench 320 through processes such as deposition to form a second isolation structure 323. The material of the second isolation structure 323 includes, but is not limited to, silicon dioxide, spin-coated insulating medium, silicon nitride, silicon oxynitride, etc. The second isolation structure 323 is used to isolate the two word lines on the sidewall of the first trench 320 to prevent short circuits.

[0119] In some embodiments, such as Figure 5A and Figure 5B As shown, the method further includes:

[0120] Multiple third isolation structures 360 are formed along the second direction, penetrating the channel post 330 on the same straight line; the third isolation structures 360 are used to divide the channel post 330 into conductive channels 331 of two transistors.

[0121] In the embodiments of this application, such as Figure 5A As shown, multiple third isolation structures 360 can be formed along the X-direction on the substrate 300 through processes such as etching and deposition, extending from the channel pillars 330 in a straight line. The materials of the third isolation structures 360 include, but are not limited to, silicon dioxide, spin-coated insulating dielectric, silicon nitride, and silicon oxynitride. The third isolation structures 360 are used to separate the channel pillars 330, thereby forming conductive channels 331 for two transistors, corresponding to word lines in the first trenches 320 on both sides of the channel pillars 330, further increasing the memory cell density. It is worth noting that, as... Figure 5B As shown, the thickness of the third isolation structure 360 ​​in the Z direction is greater than or equal to the depth of the first trench 320, so as to achieve a better isolation effect and prevent leakage between two adjacent conductive channels 331.

[0122] In some embodiments, such as Figure 6A and 6B As shown, the multiple third isolation structures 360 formed along the second direction and penetrating the same straight line of the channel column 330 include:

[0123] Multiple second grooves 361 are formed along the second direction, penetrating the same straight line through the channel column 330;

[0124] The third isolation structure 360 ​​is formed in the second trench 361, wherein the third isolation structure 360 ​​has an air gap 362.

[0125] In the embodiments of this application, such as Figure 6A As shown, a photolithography process can be used to form a mask corresponding to multiple second trenches 361 that run through the channel pillars 330 along the same straight line in the second direction on the substrate 300. Then, an etching process is used to etch the substrate 300 through the mask to form multiple second trenches 361. The second trenches 361 are used to form a third isolation structure 360, and the depth of the second trenches 361 in the Z direction is greater than or equal to the depth of the first trench 320.

[0126] like Figure 6B As shown, insulating material can be filled into the second trench 361 through processes such as deposition, and a third isolation structure 360 ​​with an air cavity 362 in the middle can be formed using processes such as etching. Optionally, the insulating material here includes, but is not limited to, silicon dioxide, spin-coated insulating dielectric, silicon nitride, silicon oxynitride, etc. The air cavity 362 can improve the dielectric properties of the third isolation structure 360, thereby improving the performance of the memory.

[0127] In some embodiments, such as Figure 7 As shown, the method further includes:

[0128] The first end of the conductive channel 331 is doped to form the source 332 of the transistor;

[0129] The second end of the conductive channel 331 is doped to form the drain 333 of the transistor.

[0130] In the embodiments of this application, such as Figure 7 As shown, the first and second ends of the conductive channel 331 can be doped using an ion implantation process to form the source 332 and drain 333 of the transistor. The first and second ends are the two opposite ends of the conductive channel 331 in the Z direction. It can be understood that the first end can be either the end of the conductive channel 331 closest to the surface of the substrate 300 or the end of the conductive channel 331 closest to the back surface of the substrate 300.

[0131] In some embodiments, such as Figure 8 As shown, the storage structure 350 formed on the surface of the channel post 330 includes:

[0132] A storage capacitor 351 is formed on the surface of the source electrode 332 of the transistor.

[0133] In the embodiments of this application, such as Figure 8 As shown, since the channel post 330 is divided into two conductive channels 331 by the third isolation structure 360, one end of one channel post 330 has two sources 332 or drains 333. A storage capacitor 351 is formed on the surface of the source 332 of the transistor, that is, two storage capacitors 351 corresponding to the source 332 of the two conductive channels 331 are formed on the surface of one channel post 330. It can be understood that the storage capacitor 351 can be formed on either the surface of the source 332 or the surface of the drain 333. One end of the storage capacitor 351 is connected to either the source 332 or the drain 333, and the other end is grounded.

[0134] In some embodiments, such as Figure 9A and 9B As shown, the above-described doping of the second end of the conductive channel 331 to form the drain 333 of the transistor includes:

[0135] The back side of the substrate 300 is thinned;

[0136] The second end of the conductive channel 331 is doped to form the drain 333 of the transistor.

[0137] In the embodiments of this application, such as Figure 9AAs shown, the back side of the substrate 300 can be thinned using processes such as chemical mechanical polishing. Because the depth of the first trench 320 in the Z direction is small, i.e., the length of the conductive channel 331 in the Z direction is small, when doping the second end of the conductive channel 331 from the back side of the substrate 300, ions cannot easily penetrate the thicker back side of the substrate 300 to form the corresponding source 332 or drain 333 at the second end. Therefore, it is necessary to thin the back side of the substrate 300 before doping the second end of the conductive channel 331. It can be understood that the second end here refers to the end of the conductive channel 331 closest to the back side of the substrate 300.

[0138] like Figure 9B As shown, the second end of the conductive channel 331 is doped using an ion implantation process to form the drain 333 of the transistor. Here, the second end refers to the end of the conductive channel 331 closest to the back surface of the substrate 300. It is understood that the source 332 of the transistor can also be formed at the end of the channel pillar 330 closest to the back surface of the substrate 300.

[0139] In some embodiments, such as Figure 10A and Figure 10B As shown, the word line structure 340, which involves removing a portion of the bottom of the first trench 320 from the back side of the substrate 300, forms two mutually separated word lines 341 within the first trench 320, including:

[0140] Remove the portion of the substrate 300 located below the word line structure 340 until the word line structure 340 is exposed from the back side of the substrate 300;

[0141] The word line structure 340 at the bottom of the first trench 320 is removed from the back side of the substrate 300 to form two word lines 341 that are separated from each other within the first trench 320.

[0142] In the embodiments of this application, such as Figure 10A As shown, the portion of substrate 300 located below word line structure 340 can be removed from the back side of substrate 300 using processes such as etching and chemical mechanical polishing. Because the etching process for forming the first trench 320 involves a certain angle, the width of the first trench 320 gradually decreases downwards from the surface of substrate 300, resulting in a thicker gate conductive layer 322 at the bottom of the word line structure 340. If the portion of word line structure 340 at the bottom of the first trench 320 is removed from the front side of substrate 300, the gate conductive layer 322 at the bottom is difficult to completely disconnect, leading to a short circuit between the two word lines 341 on the sidewall of the first trench 320, causing the memory to malfunction. Therefore, the portion of substrate 300 located below word line structure 340 can be removed from the back side of substrate 300 first to expose the word line structure 340.

[0143] like Figure 10B As shown, part of the word line structure 340 at the bottom of the first trench 320 can be removed from the back side of the substrate 300 by etching and other processes to form two word lines 341 that are separated from each other on the sidewall of the first trench 320. This avoids the short circuit problem caused by the gate conductive layer 322 at the bottom of the first trench 320 not being completely disconnected, and improves the reliability of the manufacturing process.

[0144] In some embodiments, such as Figure 11 As shown, the removal of the portion of the substrate 300 located below the word line structure 340 until the word line structure 340 is exposed from the back side of the substrate 300 includes:

[0145] The back side of the substrate 300 is thinned until the word line structure 340 is exposed from the back side of the substrate 300.

[0146] In the embodiments of this application, such as Figure 11 As shown, the back side of the substrate 300 can be thinned using a chemical mechanical polishing process, thereby exposing the gate conductive layer 322 in the word line structure 340 from the back side of the substrate 300. It is worth noting that the thinning here is to expose the gate conductive layer 322 from the back side of the substrate 300 so that a portion of the gate conductive layer 322 at the bottom of the first trench 320 can be removed in a subsequent process to form two separate word lines 341.

[0147] In some embodiments, such as Figure 12 As shown, the removal of the portion of the substrate 300 located below the word line structure 340 until the word line structure 340 is exposed from the back side of the substrate 300 includes:

[0148] An opening is formed at a corresponding position at the bottom of the first trench 320 on the back side of the substrate 300, and the bottom of the word line structure 340 is exposed through the opening.

[0149] In the embodiments of this application, such as Figure 12 As shown, the portion of the substrate 300 and gate oxide layer 321 located below the bottom of the first trench 320 can be removed by etching or other processes, forming an opening that exposes the bottom of the gate conductive layer 322 from the back side of the substrate 300, so that the portion of the gate conductive layer 322 at the bottom of the first trench 320 can be removed in subsequent processes, forming two word lines 341 that are separated from each other.

[0150] In some embodiments, such as Figure 13 As shown, the method further includes:

[0151] The recess formed after removing part of the word line structure 340 at the bottom of the first trench 320 is filled with insulating material.

[0152] In the embodiments of this application, such as Figure 13 As shown, after removing part of the word line structure 340 at the bottom of the first trench 320 through processes such as deposition, an insulating material is formed in the recess on the back side of the substrate 300 and filled with insulating material. This insulating material includes, but is not limited to, silicon dioxide, spin-coated insulating dielectric, silicon nitride, and silicon oxynitride, etc., to prevent leakage of the two word lines 341 in the first trench 320 at the bottom, thereby improving memory performance. It is worth noting that after filling the recess on the back side of the substrate 300 with insulating material, unevenness may occur on the back side of the substrate 300, which may affect the subsequent formation of other memory structures on the back side of the substrate 300. Therefore, the back side of the substrate 300 can be planarized.

[0153] In some embodiments, such as Figure 14 As shown, the method further includes:

[0154] On the back side of the substrate 300, a bit line 370 is formed that connects to the drain 333 of the transistor.

[0155] In the embodiments of this application, such as Figure 14 As shown, a bit line 370 is formed on the back side of the substrate 300, connecting the drain 333 of the transistor. The bit line 370 is made of a conductive material. When the word line 341 controls the conduction between the source 332 and the drain 333, the bit line 370 performs data reading and writing operations on the storage capacitor 351. It can be understood that the bit line 370 and the storage capacitor 351 are formed on two opposite surfaces of the substrate 300, thereby simplifying the internal circuit layout of the memory.

[0156] In some embodiments, such as Figure 15 As shown, on the back side of the substrate 300, a bit line 370 connecting the drain 333 of the transistor is formed, including:

[0157] A bit line contact structure 371 is formed on the surface of the drain electrode 333;

[0158] The bit line 370 is formed on the bit line contact structure 371.

[0159] In the embodiments of this application, such as Figure 15 As shown, a bit line contact structure 371 is formed on the surface of the drain 333, and a bit line 370 is formed on the bit line contact structure 371. The bit line contact structure 371 is made of conductive material and is used to connect the drain 333 and the bit line 370.

[0160] like Figure 16A and Figure 16B As shown, this application embodiment also provides a memory 40, the memory 40 including:

[0161] Substrate 400;

[0162] Located on the surface of the substrate 400, there are a plurality of mutually parallel first isolation structures 410 extending along a first direction and a plurality of mutually parallel first trenches 420 extending along a second direction; the first direction is perpendicular to the second direction; the depth of the first trenches 420 is less than the thickness of the substrate 400; the first isolation structures 410 and the first trenches 420 divide the substrate into a plurality of channel pillars 430.

[0163] The character line structure 440 is located within the first groove 420; the character line structure 440 includes two character lines 441 located on the sidewall of the first groove 420 and separated from each other;

[0164] Storage structure 450 located on the surface of the channel post 430.

[0165] In this embodiment, the substrate 400 may be a semiconductor material such as silicon (Si) or germanium (Ge). In some embodiments, the substrate 400 may also be doped, or may include doped and undoped regions. The side of the substrate 400 where the first trench 420 is located may be the surface of the substrate 400, and the side opposite to the surface of the substrate 400 may be the back surface of the substrate 400.

[0166] like Figure 16A As shown, the first isolation structure 410 is located on the surface of the substrate 400 and extends along a first direction. This first direction is parallel to the surface of the substrate 400 and coincides with the Y direction. The first thickness of the first isolation structure 410 in the Z direction is less than or equal to the thickness of the substrate 400. Figure 16A Storage structure 450 is not shown.

[0167] like Figure 16A As shown, the first trench 420 is located on the surface of the substrate 400 and extends along a second direction. This second direction is parallel to the surface of the substrate 400, aligned with the X-direction, and perpendicular to the first direction. Figure 16B As shown, the depth of the first trench 420 in the Z direction is less than the thickness of the substrate 400. The first trench 420 and the first isolation structure 410 divide the substrate 400 into multiple channel pillars 430. The length direction of the channel pillars 430 is consistent with the Z direction, so that the two ends of the channel pillars 430 close to the surface and back of the substrate 400 can respectively form the source and drain of the transistors in the memory, that is, the direction of the transistors in the memory is perpendicular to the substrate surface. Therefore, the vertical transistors occupy less area, so the density of memory cells per unit area is greater, and the different structures connected to the source and drain in the memory can be designed on two opposite sides of the substrate, thereby optimizing the structural layout of the memory.

[0168] like Figure 16A As shown, the character line structure 440 is located within the first groove 420 and extends along the X direction. (As indicated...) Figure 16B As shown, the word line structure 440 includes two word lines 441 located on the sidewalls of the first trench 420 and separated from each other. The word lines 441 are made of conductive materials, including but not limited to one or more of tungsten (W), titanium nitride (TiN), copper (Cu), and silver (Ag). Since the two separated word lines 441 are located on the two sidewalls of the first trench 420, each side of a channel post 430 in the Y direction can correspond to one word line 441, serving as a conductive channel in a transistor. That is, one channel post 430 can serve as a conductive channel in two transistors, further improving the memory cell density.

[0169] like Figure 16B As shown, the storage structure 450 is located on the surface of the channel post 430. It can be understood that the storage structure 450 can be located on the surface of either end of the channel post 430, connected to the source or drain of the transistor, while the other end of the channel post 430 can be connected to structures such as bit lines. It is worth noting that in this embodiment, one channel post 430 corresponds to the conductive channels of two transistors; therefore, one end of one channel post 430 can have two corresponding storage structures 450. In a random access memory, the storage structure 450 can be a capacitor.

[0170] In some embodiments, such as Figure 17 As shown, the word line structure 440 further includes:

[0171] Gate oxide layer 421 is located between the sidewall of the first trench 420 and the word line 441;

[0172] The second isolation structure 423 is located between the two word lines 441 in the first trench 420.

[0173] In this embodiment, the word line structure 440 includes: a word line 441, a gate oxide layer 421, and a second isolation structure 423. The word line 441 is located on two sidewalls of the first trench 420, and the top of the word line 441 in the Z direction is lower than the surface of the substrate 400 to prevent leakage at the end of the word line 441 near the surface of the substrate 400. The word line 441 is a conductive material, including but not limited to one or more of tungsten, titanium nitride, copper, and silver.

[0174] The gate oxide layer 421 is located between the sidewall of the first trench 420 and the word line 441. The gate oxide layer 421 can be formed by thermal oxidation of the sidewall of the first trench 420.

[0175] The second isolation structure 423 is located between the two word lines 441 in the first trench 420. The material of the second isolation structure 423 includes, but is not limited to, silicon dioxide, spin-coated insulating medium, silicon nitride, silicon oxynitride, etc. The second isolation structure 423 is used to isolate the two word lines 441 on the sidewall of the first trench 420 to prevent short circuits.

[0176] In some embodiments, such as Figure 18A and 18B As shown, the memory 40 further includes:

[0177] Multiple third isolation structures 460 running along the same straight line through the channel post 430 in the second direction; the third isolation structures 460 divide the channel post 430 into conductive channels 431 of two transistors.

[0178] In the embodiments of this application, such as Figure 18A As shown, the third isolation structure 460 extends along the X-direction through the channel pillar 430 on the same straight line, dividing the channel pillar 430 into two conductive channels 431 for the transistors. The material of the third isolation structure 460 includes, but is not limited to, silicon dioxide, spin-coated insulating dielectric, silicon nitride, and silicon oxynitride. Figure 18B As shown, the third isolation structure 460 is used to separate the conductive channels 431 of the two transistors, corresponding respectively to the word lines 441 in the first trenches 420 on both sides of the channel pillars 430. It is worth noting that, as... Figure 18B As shown, the thickness of the third isolation structure 460 in the Z direction is greater than or equal to the depth of the first trench 420, so as to achieve a better isolation effect and prevent leakage between two adjacent conductive channels 431.

[0179] In some embodiments, such as Figure 19 As shown, the third isolation structure 460 has an air cavity 462.

[0180] In this embodiment, the third isolation structure 460 has an air cavity 462, which can improve the dielectric properties of the third isolation structure 460 and thus improve the performance of the memory.

[0181] In some embodiments, such as Figure 20 As shown, the channel post 430 includes:

[0182] The source 432 of the transistor located at the first end of the conductive channel 431;

[0183] The drain 433 of the transistor is located at the second end of the conductive channel 431.

[0184] In this embodiment, the source 432 and drain 433 of the transistor are located at opposite ends of the conductive channel 431 in the Z direction. It can be understood that the first end can be the end of the conductive channel 431 near the surface of the substrate 400, or it can be the end of the conductive channel 431 near the back side of the substrate 400.

[0185] In some embodiments, such as Figure 20 As shown, the storage structure 450 includes:

[0186] Storage capacitor 451 is located on the surface of source electrode 432 and connected to source electrode 432.

[0187] In this embodiment, the storage capacitor 451 is located on the surface of the source 432 and connected to the source 432, and is used to store the written data. It is understood that the storage capacitor 451 can be located on either the surface of the source 432 or the surface of the drain 433. One end of the storage capacitor 451 is connected to either the source 432 or the drain 433, and the other end is grounded.

[0188] In some embodiments, such as Figures 21A to 21C As shown, the storage capacitor 451 includes, but is not limited to: cup-type capacitors, cylindrical capacitors, and pillar-type capacitors.

[0189] In the embodiments of this application, such as Figure 21A The diagram shows the structure of a cup-shaped capacitor, where the lower electrode 4511 is an upward-opening cup shape, and the upper electrode 4512 is located inside the lower electrode 4511.

[0190] like Figure 21B The diagram shows the structure of a cylindrical capacitor, where the lower electrode 4511 is a cup shape with an upward opening; the upper electrode 4512 surrounds the inner and outer sides of the lower electrode 4511.

[0191] like Figure 21C The diagram shows the structure of a cylindrical capacitor, where the lower electrode 4511 is cylindrical and the upper electrode 4512 surrounds the lower electrode 4511 and opens downwards.

[0192] Both the upper electrode 4512 and the lower electrode 4511 are conductive materials, including metals and metal nitride materials, such as one or more of tungsten, nickel, tantalum, tantalum nitride and titanium nitride; the capacitor dielectric layer 4513 is a high-k dielectric material, such as titanium oxide, zirconium oxide, hafnium oxide, etc.

[0193] In some embodiments, such as Figure 22A and Figure 22B As shown, the arrangement of the storage capacitor 451 on the surface of the substrate 400 includes, but is not limited to, a square arrangement and a hexagonal arrangement.

[0194] In the embodiments of this application, such as Figure 22A The diagram shows a square arrangement of storage capacitors 451 on the surface of substrate 400. The spacing between the storage capacitors 451 in the X and Y directions can be equal to the spacing between the conductive channels 431. The center of the storage capacitors 451 in the XY plane can be offset relative to the center of the conductive channels 431.

[0195] like Figure 22B The diagram shows a hexagonal arrangement of storage capacitors 451 on the surface of substrate 400. Adjacent rows of storage capacitors 451 can be staggered along the X direction.

[0196] In some embodiments, the cross-sectional shape of the storage capacitor 451 in the Z direction can be elliptical, and the axis of the elliptical cross-section of the storage capacitor 451 is not parallel to the X direction, so as to reduce the area occupied by the capacitor.

[0197] In some embodiments, such as Figure 23 As shown, the memory 40 further includes:

[0198] Bit line 470 is located on the back side of the substrate 400 and is connected to the drain 433.

[0199] In this embodiment, bit line 470 is located on the back side of substrate 400 and connected to drain 433. Bit line 470 is made of conductive material. When word line 441 controls the conduction between source 432 and drain 433, bit line 470 performs data read and write operations on storage capacitor 451. It is understood that bit line 470 and storage capacitor 451 are formed on two opposite surfaces of substrate 400, thereby simplifying the internal circuit layout of the memory.

[0200] In some embodiments, such as Figure 24 As shown, the memory 40 further includes:

[0201] Bit line contact structure 471 is located on the surface of the drain 433, and the bit line contact structure 471 connects the drain 433 and the bit line 470.

[0202] In this embodiment, the bit line contact structure 471 is located on the surface of the drain 433. The bit line contact structure 471 is made of conductive material and connects the bit line 470 and the drain 433.

[0203] It should be noted that the embodiments provided in this application can be applied to random access memory (RAM), dynamic random access memory (DRAM), ferroelectric random access memory (FRAM), phase change random access memory (PCRAM), magnetic random access memory (MRAM), etc.

[0204] It should be noted that the features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined to obtain new method or device embodiments without conflict.

[0205] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for manufacturing a memory, characterized in that, The method includes: Provide substrate; A plurality of mutually parallel first isolation structures extending along a first direction and a plurality of mutually parallel first trenches extending along a second direction are formed on the surface of the substrate; the first direction is perpendicular to the second direction; the depth of the first trenches is less than the thickness of the substrate; the first isolation structures and the first trenches divide the substrate into a plurality of channel pillars; Forming a character line structure covering the inner wall of the first trench; A storage structure is formed on the surface of the channel column; A portion of the word line structure at the bottom of the first trench is removed from the back side of the substrate to form two word lines that are separated from each other within the first trench.

2. The method according to claim 1, characterized in that, The formation of the word line structure covering the inner wall of the first trench includes: A gate oxide layer is formed covering the inner wall of the first trench; Form a gate conductive layer covering the gate oxide layer; An insulating material is filled between the gate conductive layers in the first trench to form a second isolation structure.

3. The method according to claim 1, characterized in that, The step of removing a portion of the word line structure from the bottom of the first trench on the back side of the substrate to form two word lines separated from each other within the first trench includes: Remove the portion of the substrate located below the word line structure until the word line structure is exposed from the back side of the substrate; The word line structure at the bottom of the first trench is removed from the back side of the substrate to form two word lines that are separated from each other within the first trench.

4. The method according to claim 3, characterized in that, The method further includes: The recess formed after removing part of the letter line structure at the bottom of the first trench is filled with insulating material.

5. The method according to claim 3, characterized in that, The step of removing the portion of the substrate located below the word line structure until the word line structure is exposed from the back side of the substrate includes: The back side of the substrate is thinned until the word line structure is exposed from the back side of the substrate.

6. The method according to claim 3, characterized in that, The step of removing the portion of the substrate located below the word line structure until the word line structure is exposed from the back side of the substrate includes: An opening is formed at a corresponding position at the bottom of the first trench on the back side of the substrate, and the bottom of the word line structure is exposed through the opening.

7. The method according to claim 1, characterized in that, The method further includes: Multiple third isolation structures are formed along the second direction, running through the same straight line; the third isolation structures are used to divide the channel pillar into conductive channels for two transistors.

8. The method according to claim 7, characterized in that, The multiple third isolation structures forming the channel pillars along the second direction and running on the same straight line include: Multiple second grooves are formed along the second direction, penetrating the channel column on the same straight line; The third isolation structure is formed in the second trench, wherein the third isolation structure has an air cavity.

9. The method according to claim 7, characterized in that, The method further includes: The first end of the conductive channel is doped to form the source of the transistor; The second end of the conductive channel is doped to form the drain of the transistor.

10. The method according to claim 9, characterized in that, The formation of a storage structure on the surface of the channel post includes: A storage capacitor is formed on the source surface of the transistor.

11. The method according to claim 9, characterized in that, The step of doping the second end of the conductive channel to form the drain of the transistor includes: The back side of the substrate is thinned; The second end of the conductive channel is doped to form the drain of the transistor.

12. The method according to claim 9, characterized in that, The method further includes: On the back side of the substrate, a bit line is formed that connects to the drain of the transistor.

13. The method according to claim 12, characterized in that, The step of forming a bit line connecting the drain of the transistor on the back side of the substrate includes: A bit line contact structure is formed on the surface of the drain electrode; The bit line is formed on the bit line contact structure.

14. A memory, characterized in that, The memory is manufactured using the memory manufacturing method described in any one of claims 1 to 13, and the memory comprises: Substrate; Located on the surface of the substrate, there are a plurality of mutually parallel first isolation structures extending along a first direction, and a plurality of mutually parallel first trenches extending along a second direction; the first direction is perpendicular to the second direction; the depth of the first trenches is less than the thickness of the substrate; the first isolation structures and the first trenches divide the substrate into a plurality of channel pillars; A character line structure is located within the first groove; the character line structure includes two separate character lines located on the sidewall of the first groove. Storage structure located on the surface of the channel post.

15. The memory according to claim 14, characterized in that, The word line structure also includes: A gate oxide layer is located between the sidewall of the first trench and the word line; The second isolation structure is located between the two word lines in the first trench.

16. The memory according to claim 14, characterized in that, The memory also includes: Multiple third isolation structures running along the second direction and on the same straight line through the channel post; the third isolation structures divide the channel post into conductive channels for two transistors.

17. The memory according to claim 16, characterized in that, The third isolation structure has an air cavity.

18. The memory according to claim 16, characterized in that, The trench column includes: The source of the transistor located at the first end of the conductive channel; The drain of the transistor located at the second end of the conductive channel.

19. The memory according to claim 18, characterized in that, The storage structure includes: A storage capacitor is located on the surface of the source electrode and connected to the source electrode.

20. The memory according to claim 18, characterized in that, The memory also includes: Bit lines are located on the back side of the substrate and are connected to the drain.

21. The memory according to claim 20, characterized in that, The memory also includes: A bit line contact structure is located on the surface of the drain electrode, and the bit line contact structure connects the drain electrode and the bit line.

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