A low power eFlash read acceleration system
By combining the adaptive prefetch control module and the cache module, the number of prefetched rows is dynamically adjusted, which solves the problems of slow eFlash read speed and low prefetch efficiency, and achieves low-power read acceleration effect.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- INST OF MICROELECTRONICS CHINESE ACAD OF SCI LTD
- Filing Date
- 2023-05-25
- Publication Date
- 2026-08-04
AI Technical Summary
In the existing technology, the eFlash read speed is low, which affects the CPU performance, and the data hit rate of the prefetch register is low, resulting in poor prefetch operation acceleration effect and introducing additional power consumption.
A low-power eFlash read acceleration system is adopted, including an AHB bus interface module, a prefetch control module, a cache module, and an eFlash memory. The adaptive prefetch control module dynamically detects the spatial locality of the program and dynamically adjusts the number of prefetched lines. The cache module is used to process jump instructions, reducing the number of invalid prefetches.
It improved instruction hit rate, reduced invalid prefetches, lowered power consumption, and reduced runtime through the cache module.
Smart Images
Figure CN116627335B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of memory control technology, and in particular to a low-power eFlash read acceleration system. Background Technology
[0002] As the program and data memory of a chip, the read speed of eFlash is crucial to its overall performance. Taking microcontroller units (MCUs) as an example, the operating frequency of high-performance MCUs can reach hundreds of megahertz, which is far higher than the read speed of mainstream eFlash, which is tens of megahertz. The low read speed of eFlash affects the CPU's instruction fetching speed and restricts the CPU's performance.
[0003] Based on the spatial and temporal locality of software programs, a common approach to accelerating eFlash is to add a prefetch module and a cache, using a high-bit-width eFlash. The prefetch operation involves reading the current instruction and then loading the next consecutive instruction line into the prefetch register when the CPU issues a fetch command. Subsequent CPU accesses of the prefetched instruction can directly retrieve it from the prefetch register without access latency. The cache is used to address missing jump instructions. The sequential prefetch described above only has a high hit rate when the program exhibits good spatial locality. When a jump instruction cannot be accurately prefetched, it is stored in the cache, allowing the next jump instruction to be retrieved from the cache. A high-bit-width eFlash can fetch multiple instructions at once, reducing access latency during instruction prefetching. Summary of the Invention
[0004] Based on the above analysis, the present invention aims to provide a low-power eFlash read acceleration system to solve the problems of low data hit rate in the prefetch register, poor prefetch operation acceleration effect, and additional power consumption in the prior art.
[0005] On one hand, embodiments of the present invention provide a low-power eFlash read acceleration system, which includes: an AHB bus interface module, a prefetch control module, a cache module, and an eFlash memory;
[0006] The AHB bus interface module is used to receive the request address from the external CPU and send it to the prefetch control module and the cache module.
[0007] The prefetch control module includes a buffer module. The buffer module and the cache module determine whether there is an instruction in their respective stored instructions that matches the request address based on the request address. If there is, the instruction is transmitted to the CPU through the AHB bus interface module.
[0008] When the instructions in both the buffer module and the cache module do not match the requested address, the AHB bus interface module sends an instruction missing signal to the prefetch control module. The prefetch control module outputs the updated prefetch row count based on the requested address and the address corresponding to the instruction in the buffer module. It then retrieves the requested address and the instruction for the subsequent prefetch row count from the eFlash memory based on the prefetch row count. The instruction corresponding to the requested address is sent to the CPU through the AHB interface module and stored in the cache module. At the same time, the instruction for the prefetch row count following the requested address is stored in the buffer module.
[0009] Furthermore, the prefetch control module also includes: prefetch control logic and an adaptive prefetch control module;
[0010] The prefetch control logic is connected to the AHB bus interface module and is used to send information to or receive information sent by the AHB bus interface module.
[0011] The adaptive prefetch control module is used to calculate the minimum difference between the requested address and the address corresponding to the instruction in the buffer module, and output the updated prefetch row count based on the minimum difference and the current prefetch row count of the adaptive prefetch control module.
[0012] Furthermore, the adaptive prefetch control module outputs the number of prefetched rows using a state machine approach, specifically:
[0013] When the current number of prefetched rows is 1, if the minimum address difference is less than or equal to 4, the updated number of prefetched rows will be 2. If the minimum address difference is greater than 4, the updated number of prefetched rows will remain unchanged.
[0014] When the current number of prefetched rows is 2, the updated number of prefetched rows will be 4 if the minimum address difference is less than or equal to 8, and the updated number of prefetched rows will be 1 if the minimum address difference is greater than 8.
[0015] When the current number of prefetched rows is 4, the updated number of prefetched rows is changed to 2.
[0016] Furthermore, the number of rows prefetched by the adaptive prefetch control module is 1 row, 2 rows, and 4 rows.
[0017] Furthermore, the calculation of the minimum difference between the request address and the address corresponding to the instruction in the buffer module specifically involves calculating the minimum difference between the tag portion of the request address and the tag portion of the address corresponding to the instruction in the buffer module.
[0018] Furthermore, the acceleration system also includes an eFlash controller. The eFlash controller receives the request address and prefetch row number input by the prefetch control module, generates the corresponding working timing input to the eFlash memory, waits for the read instruction, and returns the instruction to the eFlash controller. The eFlash controller then sends the corresponding instruction to the prefetch control logic or cache module.
[0019] Furthermore, when the tag portion of a certain instruction address in the buffer module matches the tag portion of the request address, the buffer module sends a hit message (1) to the AHB bus interface module through the prefetch control logic. When the tag portions of all instruction addresses in the buffer module do not match the tag portions of the request addresses, the buffer module sends a miss message (0) to the AHB bus interface module through the prefetch control logic.
[0020] When the tag portion of an instruction address in the cache module matches the tag portion of the request address, the cache module sends a hit message (1) to the AHB bus interface module. When the tag portions of all instruction addresses in the cache module do not match the tag portions of the request addresses, the cache module sends a miss message (0) to the AHB bus interface module.
[0021] Furthermore, the AHB bus interface module determines whether to send an instruction missing signal to the prefetch control logic based on the hit or miss signals sent by the buffer module and the cache module.
[0022] When the buffer module sends 1 to the AHB bus interface module, and the cache module sends 0 to the buffer module and then to the AHB bus interface module, the AHB bus interface module reads the instruction corresponding to the requested address from the buffer module.
[0023] When the buffer module sends 0 to the AHB bus interface module, and the cache module sends 1 to the buffer module and then to the AHB bus interface module, the AHB bus interface module reads the instruction corresponding to the requested address from the cache module.
[0024] When the buffer module sends 0 to the AHB bus interface module, and the cache module sends 0 to both the buffer module and the AHB bus interface module, the AHB bus interface module sends an instruction missing signal to the prefetch control logic.
[0025] Furthermore, the buffer module includes 4 rows of storage units, each row containing 128 bits, following a first-in-first-out (FIFO) principle.
[0026] Furthermore, the eFlash memory has a bit width of 128 bits, meaning that each line of eFlash contains 4 32-bit instructions.
[0027] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:
[0028] 1. This application uses an adaptive prefetch control module to dynamically detect the spatial locality of the program, dynamically adjust the number of prefetched lines, improve the instruction hit probability, and reduce the number of invalid prefetches, thereby reducing power consumption;
[0029] 2. This application uses a cache module, which is a high-speed cache 2-way set-associative structure, to process jump instructions. When the address accessed by the CPU is missing, the missing instruction line is read and returned to the CPU and stored in the cache module. When the CPU jumps to the address again, there is no waiting time and the corresponding instruction is directly retrieved from the cache module, reducing the running time.
[0030] In this invention, the above-described technical solutions can be combined with each other to achieve more preferred combinations. Other features and advantages of this invention will be set forth in the following description, and some advantages may become apparent from the description or be learned by practicing the invention. The objects and other advantages of this invention can be realized and obtained from what is particularly pointed out in the description and drawings. Attached Figure Description
[0031] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts.
[0032] Figure 1 A schematic diagram of the reading acceleration system is provided.
[0033] Figure 2 This is the state transition diagram for the adaptive prefetch control module. Detailed Implementation
[0034] Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which form part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not intended to limit the scope of the present invention.
[0035] One specific embodiment of the present invention discloses a low-power eFlash read acceleration system, such as... Figure 1 As shown. The acceleration system includes: an AHB bus interface module, a prefetch control module, a cache module, and an eFlash memory;
[0036] The AHB bus interface module is used to receive the request address from the external CPU and send it to the prefetch control module and the cache module.
[0037] The prefetch control module includes a buffer module. The buffer module and the cache module determine whether there is an instruction in their respective stored instructions that matches the request address based on the request address. If there is, the instruction is transmitted to the CPU through the AHB bus interface module.
[0038] When the instructions in both the buffer module and the cache module do not match the requested address, the AHB bus interface module sends an instruction missing signal to the prefetch control module. The prefetch control module outputs the updated prefetch row count based on the requested address and the address corresponding to the instruction in the buffer module. It then retrieves the requested address and the instruction for the subsequent prefetch row count from the eFlash memory based on the prefetch row count. The instruction corresponding to the requested address is sent to the CPU through the AHB interface module and stored in the cache module. At the same time, the instruction for the prefetch row count following the requested address is stored in the buffer module.
[0039] Specifically, the tag portion of the address corresponding to each instruction in the buffer module and cache module is compared with the tag portion in the CPU request address. When the tag portion of the address corresponding to a certain instruction in the buffer module or cache module is equal to the tag portion in the CPU request address, it means that the instruction in the buffer module or cache module matches the instruction in the CPU request address, i.e., a hit.
[0040] When the tag portion of the address corresponding to all instructions in the buffer module or cache module is not equal to the tag portion of the CPU request address, it means that the instructions in the buffer module and cache module do not match the instructions in the CPU request address, i.e., a miss.
[0041] Specifically, when an instruction is hit, the AHB bus interface module directly reads the instruction to the CPU, and the CPU's instruction read request process ends.
[0042] Specifically, the cache module adopts a 2-way set-associative structure and uses the Least Recently Used (LRU) replacement strategy. The cache module is mainly used to cache jump instructions. When the requested address accessed by the external CPU is not found, the missing instruction is read from the eFlash memory and returned to the external CPU through the prefetch control module and the AHB bus interface module. At the same time, the instruction is stored in the cache module. When the external CPU accesses the address again, the instruction at the corresponding address is retrieved directly from the cache module without waiting time.
[0043] Furthermore, the prefetch control module also includes: prefetch control logic and an adaptive prefetch control module;
[0044] The prefetch control logic is connected to the AHB bus interface module and is used to send information to or receive information sent by the AHB bus interface module.
[0045] The adaptive prefetch control module is used to calculate the minimum difference between the requested address and the address corresponding to the instruction in the buffer module, and output the updated prefetch row count based on the minimum difference and the current prefetch row count of the adaptive prefetch control module.
[0046] Specifically, when the requested address is not hit, the prefetch control module suspends instruction prefetching and retrieves it directly from the eFlash memory.
[0047] Specifically, the information sent by the prefetch control logic to the AHB bus interface module includes: buffer module instruction matching information 1, buffer module instruction mismatch information 0, cache module instruction matching information 1, and cache module instruction mismatch information 0.
[0048] The prefetch control logic receives information from the AHB bus interface module, including: an instruction missing signal.
[0049] Furthermore, the adaptive prefetch control module outputs the number of prefetched rows using a state machine approach, specifically:
[0050] When the current number of prefetched rows is 1, if the minimum address difference is less than or equal to 4, the updated number of prefetched rows will be 2. If the minimum address difference is greater than 4, the updated number of prefetched rows will remain unchanged.
[0051] When the current number of prefetched rows is 2, the updated number of prefetched rows will be 4 if the minimum address difference is less than or equal to 8, and the updated number of prefetched rows will be 1 if the minimum address difference is greater than 8.
[0052] When the current number of prefetched rows is 4, the updated number of prefetched rows is changed to 2.
[0053] Specifically, when the current number of prefetched lines is 1, if an instruction miss occurs and the minimum address difference is less than or equal to 4, the number of prefetched lines is updated to 2. At this time, the program space is relatively good, and the number of prefetched lines is increased, so choosing 2 lines is better. When an instruction miss occurs and the minimum address difference is greater than 4, it means that the current program space is relatively worse, and the number of prefetched lines should not be too many to avoid wasting resources. Therefore, the updated number of prefetched lines remains unchanged and is still 1 line.
[0054] When the current number of prefetched lines is 2, if an instruction miss occurs and the minimum address difference is less than or equal to 8, the number of prefetched lines is updated to 4. At this time, the program space is better, so increasing the number of prefetched lines and choosing 4 lines is better. If an instruction miss occurs and the minimum address difference is greater than 8, the number of prefetched lines is updated to 1. At this time, the program space is worse, so decreasing the number of prefetched lines and choosing 1 line is better, thus reducing the power consumption waste caused by the number of prefetched lines when encountering jump instructions.
[0055] When the current number of prefetched rows is 4, the number of prefetched rows will be updated to 2 whenever an instruction is missing, thus reducing the power consumption waste caused by encountering jump instructions.
[0056] Specifically, the instructions prefetched by the prefetch control module are stored in the buffer module. The better the program space, the larger the number of prefetch lines, and the higher the performance of external CPU instruction fetching. However, a large number of prefetch lines will cause power waste when encountering jump instructions. In this application, the number of prefetch lines of the prefetch control module will be adjusted according to the program space judgment of the adaptive prefetch control module to improve the prefetch efficiency.
[0057] Furthermore, the number of rows prefetched by the adaptive prefetch control module is 1 row, 2 rows, or 4 rows.
[0058] Specifically, the default number of rows prefetched by the adaptive prefetch control module is 2.
[0059] Furthermore, the eFlash memory has a bit width of 128 bits, meaning that each line of eFlash contains 4 32-bit instructions.
[0060] Specifically, prefetching two lines of instructions contains eight 32-bit instructions.
[0061] Furthermore, the calculation of the minimum difference between the request address and the address corresponding to the instruction in the buffer module specifically involves calculating the minimum difference between the tag portion of the request address and the tag portion of the address corresponding to the instruction in the buffer module.
[0062] Furthermore, the acceleration system also includes an eFlash controller. The eFlash controller receives the request address and prefetch row number input by the prefetch control module, generates the corresponding working timing input to the eFlash memory, waits for the read instruction, and returns the instruction to the eFlash controller. The eFlash controller then sends the corresponding instruction to the prefetch control logic or cache module.
[0063] Specifically, the acceleration system also includes an eFlash control register, which receives requests from an external CPU via the AHB bus interface to configure the operating state and power of the eFlash controller. The eFlash controller receives external read, write, and erase requests.
[0064] Furthermore, when the tag portion of a certain instruction address in the buffer module matches the tag portion of the request address, the buffer module sends a hit message (1) to the AHB bus interface module through the prefetch control logic. When the tag portions of all instruction addresses in the buffer module do not match the tag portions of the request addresses, the buffer module sends a miss message (0) to the AHB bus interface module through the prefetch control logic.
[0065] When the tag portion of an instruction address in the cache module matches the tag portion of the request address, the cache module sends a hit message (1) to the AHB bus interface module. When the tag portions of all instruction addresses in the cache module do not match the tag portions of the request addresses, the cache module sends a miss message (0) to the AHB bus interface module.
[0066] Furthermore, the AHB bus interface module determines whether to send an instruction missing signal to the prefetch control logic based on the hit or miss signals sent by the buffer module and the cache module.
[0067] When the buffer module sends 1 to the AHB bus interface module, and the cache module sends 0 to the buffer module and then to the AHB bus interface module, the AHB bus interface module reads the instruction corresponding to the requested address from the buffer module.
[0068] When the buffer module sends 0 to the AHB bus interface module, and the cache module sends 1 to the buffer module and then to the AHB bus interface module, the AHB bus interface module reads the instruction corresponding to the requested address from the cache module.
[0069] When the buffer module sends 0 to the AHB bus interface module, and the cache module sends 0 to both the buffer module and the AHB bus interface module, the AHB bus interface module sends an instruction missing signal to the prefetch control logic.
[0070] Furthermore, the buffer module includes 4 rows of storage units, each row containing 128 bits, following a first-in-first-out (FIFO) principle.
[0071] The prefetch control logic of the prefetch control module prefetches instructions based on the output of the adaptive prefetch control module. For example, when the adaptive prefetch control module outputs 2, it prefetches 2 lines. Traditional architectures use fixed prefetching, meaning the output of the prefetch control module is always 2. In this design, the possible values are 1, 2, and 4. That is, the adaptive prefetch control module in this application calculates the minimum difference between the requested address and the corresponding address of the instruction in the buffer. Based on this minimum difference and the current number of prefetched lines, it outputs an updated number of prefetched lines. This allows for real-time adjustment of the number of prefetched lines based on the spatial locality of program instructions, ensuring a higher hit rate for the requested address and thus improving read speed.
[0072] Compared with existing technologies, the low-power eFlash read acceleration system provided in this embodiment dynamically detects the spatial locality of the program through an adaptive prefetch control module, dynamically adjusts the number of prefetch lines, improves the instruction hit probability, and reduces the number of invalid prefetches, thereby reducing power consumption. This application uses a cache module, which is a high-speed cache 2-way set-associative structure, to process jump instructions. When the address accessed by the CPU is missing, the missing instruction line is read and returned to the CPU and stored in the cache module. When the CPU jumps to the address again, there is no waiting time and the corresponding instruction is directly retrieved from the cache module, reducing the running time.
[0073] Those skilled in the art will understand that all or part of the processes of the methods described in the above embodiments can be implemented by a computer program instructing related hardware, and the program can be stored in a computer-readable storage medium. The computer-readable storage medium may be a disk, optical disk, read-only memory, or random access memory, etc.
[0074] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.
Claims
1. A read acceleration system for low power eFlash, characterized by, The acceleration system includes: an AHB bus interface module, a prefetch control module, a cache module, and an eFlash memory; The AHB bus interface module is used to receive the request address from the external CPU and send it to the prefetch control module and the cache module. The prefetch control module includes a buffer module. The buffer module and the cache module determine whether there is an instruction in their respective stored instructions that matches the request address based on the request address. If there is, the instruction is transmitted to the CPU through the AHB bus interface module. When the instructions in both the buffer module and the cache module do not match the requested address, the AHB bus interface module sends an instruction missing signal to the prefetch control module. The prefetch control module outputs the updated prefetch row count based on the requested address and the address corresponding to the instruction in the buffer module. Based on the prefetch row count, the module retrieves the requested address and the instruction for the subsequent prefetch row count from the eFlash memory. The module then sends the instruction corresponding to the requested address to the CPU through the AHB interface module and stores it in the cache module. At the same time, the instruction for the prefetch row count following the requested address is stored in the buffer module. The prefetch control module further includes: prefetch control logic and an adaptive prefetch control module; The prefetch control logic is connected to the AHB bus interface module and is used to send information to or receive information sent by the AHB bus interface module. The adaptive prefetch control module is used to calculate the minimum difference between the requested address and the address corresponding to the instruction in the buffer module, and output the updated prefetch row count based on the minimum difference and the current prefetch row count of the adaptive prefetch control module. The adaptive prefetch control module outputs the number of prefetched rows using a state machine approach, specifically: When the current number of prefetched rows is 1, if the minimum address difference is less than or equal to 4, the updated number of prefetched rows is 2; if the minimum address difference is greater than 4, the updated number of prefetched rows remains unchanged. When the current number of prefetched rows is 2, the updated number of prefetched rows will be 4 if the minimum address difference is less than or equal to 8, and the updated number of prefetched rows will be 1 if the minimum address difference is greater than 8. When the current number of prefetched rows is 4, the updated number of prefetched rows is changed to 2.
2. The read acceleration system for low power eFlash of claim 1, wherein, The adaptive prefetch control module can prefetch 1, 2, or 4 rows.
3. The read acceleration system for low power eFlash of claim 1, wherein, The calculation of the minimum difference between the request address and the address corresponding to the instruction in the buffer module is specifically: the minimum difference between the tag part in the request address and the tag part in the address corresponding to the instruction in the buffer module.
4. The read acceleration system for low power eFlash of claim 1, wherein, The acceleration system also includes an eFlash controller. The eFlash controller receives the request address and the number of prefetch rows input by the prefetch control module, generates the corresponding working timing input to the eFlash memory, waits for the read instruction, and returns the instruction to the eFlash controller. The eFlash controller sends the corresponding instruction to the prefetch control logic or cache module.
5. The low-power eFlash read acceleration system according to claim 3, characterized in that, When the tag part of a certain instruction address in the buffer module matches the tag part of the request address, the buffer module sends a hit message (1) to the AHB bus interface module through the prefetch control logic. When the tag parts of all instruction addresses in the buffer module do not match the tag parts of the request addresses, the buffer module sends a miss message (0) to the AHB bus interface module through the prefetch control logic. When the tag portion of an instruction address in the cache module matches the tag portion of the request address, the cache module sends a hit message (1) to the AHB bus interface module. When the tag portions of all instruction addresses in the cache module do not match the tag portions of the request addresses, the cache module sends a miss message (0) to the AHB bus interface module.
6. The read acceleration system of low power eFlash of claim 5, wherein, The AHB bus interface module determines whether to send an instruction missing signal to the prefetch control logic based on the hit or miss signals sent by the buffer module and the cache module. When the buffer module sends 1 to the AHB bus interface module, and the cache module sends 0 to the buffer module and then to the AHB bus interface module, the AHB bus interface module reads the instruction corresponding to the requested address from the buffer module. When the buffer module sends 0 to the AHB bus interface module, and the cache module sends 1 to the buffer module and then to the AHB bus interface module, the AHB bus interface module reads the instruction corresponding to the requested address from the cache module. When the buffer module sends 0 to the AHB bus interface module, and the cache module sends 0 to both the buffer module and the AHB bus interface module, the AHB bus interface module sends an instruction missing signal to the prefetch control logic.
7. The read acceleration system of low power eFlash of claim 6, wherein, The buffer module includes 4 rows of storage units, each row containing 128 bits, following a first-in-first-out (FIFO) principle.
8. The read acceleration system for low power eFlash of claim 1, wherein, The eFlash memory has a bit width of 128 bits, meaning that each line of eFlash contains 4 32-bit instructions.