Arithmetic operation structure for risc-v vector fixed-point instructions

Abstract

The application discloses an arithmetic operation structure for RISC-V vector fixed-point instructions, which comprises a multiplication module for multiplying input data; a switching module for receiving and switching output data of the multiplication module, external input data and external switching signals; an addition module for receiving and adding the switched data output from the switching module; a selector comprising a first, a second, a third and a fourth selector; a selection module for receiving and selecting external signals and output data of the addition module; a rounding operation module for receiving and rounding output data of the first and second selectors and the addition module; a comparison module for receiving and comparing output data of the addition module and reduction or post output data; and a saturation operation module for receiving and saturating output data of the rounding operation module and external saturation effective signals.

Description

Technical Field

[0001] This invention relates to the field of data processing interface technology, and in particular to an arithmetic operation structure for RISC-V vector fixed-point instructions. Background Technology

[0002] The RISC-V vector instruction set is an extension of the open-source Reduced Instruction Set Computing (RISC-V) to support vector operations. Vector operations can be divided into fixed-point vector operations and floating-point vector operations. Fixed-point vector operations mainly include arithmetic operations, shift operations, and logical operations, supporting more than 100 instructions such as vector addition, subtraction, multiplication, division, multiplication-addition, averaging, saturated addition, rounding-saturated multiplication, maximum (minimum), and selection.

[0003] Traditional arithmetic units for RISC-V vector fixed-point arithmetic operations typically integrate multiple types of arithmetic units to support vector fixed-point arithmetic operations, such as multiply-adders, saturated adders, mean operators, multiplication and rounding saturated operators, comparators, selectors, etc. However, integrating a large number of arithmetic units puts a lot of pressure on the chip's area and power consumption, resulting in high power consumption. Summary of the Invention

[0004] To address some or all of the technical problems existing in the prior art, this invention provides an arithmetic operation structure for RISC-V vector fixed-point instructions, which has a small chip footprint and low power consumption.

[0005] The technical solution of the present invention is as follows:

[0006] An arithmetic operation structure for RISC-V vector fixed-point instructions includes:

[0007] The multiplication module is used to perform signed and / or unsigned multiplication operations on the input data;

[0008] A switching module, the input of which is connected to the first output of the multiplication module, is used to receive the data output by the multiplication module, externally input data, and external switching signals, and to perform switching output.

[0009] An addition module, wherein the input of the addition module is connected to the output of the switching module, is used to receive the switched data output from the switching module and perform signed and / or unsigned addition and subtraction operations on the received data;

[0010] The selector includes a first selector, a second selector, a third selector, and a fourth selector;

[0011] The input terminal of the first selector is connected to the second output terminal of the multiplication module and the first output terminal of the addition module, respectively, for receiving the multiplication operation result output by the multiplication module and the addition operation result and average result output by the addition module, and for selecting and outputting the input data;

[0012] The input terminal of the second selector is connected to the second output terminal of the addition module, and is used to receive the mantissa of the addition result and the mantissa of the multiplication result output by the addition module, and select and output the received mantissa;

[0013] The first input terminal of the third selector is used to receive external data and select and output the external data to the fourth selector.

[0014] A rounding operation module is used to receive data output from the first selector, the second selector, and the addition module, and to perform carry-in or round-out operations on the input data according to the rounding mode.

[0015] The comparison module is used to receive the data output by the addition module after reduction and the data output by the addition module, and to perform a comparison operation between signed and / or unsigned numbers on the received data;

[0016] The saturation operation module receives the data after carry or truncation from the rounding operation module and an external saturation valid signal, performs saturation operation on the received data, and transmits the result of the saturation operation, along with the data output from the comparison module and the third selector, to the input of the fourth selector. The fourth selector then selects the output for the next operation.

[0017] Furthermore, it also includes a selection module, the input of which is connected to the third output of the addition module, and the output of which is connected to the third selector; used to select the output data signal of the addition module and the external signal to be received, and to select the output to the third selector.

[0018] Furthermore, when processing data, the data output by the multiplication module and the addition module, as well as the data input to the third selector, are all pre-stored in registers.

[0019] Furthermore, during data processing in the switching module, when the valid signal in the input switching module is high, the two input signals are swapped and output; when the valid signal in the input switching module is low, the two input signals are not swapped and are output directly.

[0020] Furthermore, when the input data is processed in the addition module, the addition module is enabled when the addition valid signal is high. When the addition valid signal in the input addition module is high and the subtraction operation signal is low, the addition result of the output signal is the sum of the results output in the exchange module. When the addition valid signal in the input addition module is high and the subtraction operation signal is high, the addition result of the output signal is the difference between the results output in the exchange module.

[0021] Furthermore, the selection module is used to select and output the maximum and minimum values ​​of the input data.

[0022] Furthermore, in the rounding operation module, when processing the input data, the rounding operation module outputs the result after rounding the input data when the input rounding valid signal is high, and the rounding operation module outputs the original value of the input signal when the rounding valid signal is low.

[0023] Furthermore, in the saturation operation module, when the input saturation valid signal is high, the output result is the data after performing a saturation operation on the output result of the rounding operation module; when the input saturation valid signal is low, the result of the saturation operation module is the original value of the output result of the rounding operation module.

[0024] Furthermore, when performing arithmetic operations on vector fixed-point instructions, the multiplication module, the exchange module, the addition module, the selector, the selection module, the rounding operation module, the comparison module, and the saturation operation module perform pipelined calculations on the input signals and data through multiple levels.

[0025] Furthermore, the multiplication module and the registers corresponding to the output data of the multiplication module constitute the first pipelined computing layer and the second pipelined computing layer, the exchange module, the addition module, the first selector and the second selector constitute the third pipelined computing layer, the rounding operation module, the saturation operation module, the comparison module, the selection module, the third selector and the fourth selector constitute the fourth pipelined computing layer.

[0026] The main advantages of the technical solution of this invention are as follows:

[0027] This invention provides an arithmetic operation structure for RISC-V vector fixed-point instructions. Through a multiplication module, a swapping module, an addition module, a selection module, a selector, a rounding operation module, a comparison module, and a saturation operation module, it performs arithmetic operations, selection, and output of vector fixed-point instructions. Furthermore, it reuses functional modules within the arithmetic unit during arithmetic operations on vector fixed-point instructions, saving hardware resources and improving resource utilization. Simultaneously, a single arithmetic module can support multiple types of vector fixed-point arithmetic operations, effectively reducing the area and power consumption of the arithmetic unit and improving computational efficiency. Attached Figure Description

[0028] The accompanying drawings, which are included to provide a further understanding of embodiments of the invention and constitute a part of this invention, illustrate exemplary embodiments of the invention and, together with their description, serve to explain the invention and do not constitute an undue limitation thereof. In the drawings:

[0029] Figure 1 This is a schematic diagram of the overall structure of an arithmetic operation structure for RISC-V vector fixed-point instructions according to the present invention.

[0030] Figure 2 This is a schematic diagram of the overall structure of the pipelined arithmetic operation structure for RISC-V vector fixed-point instructions according to the present invention.

[0031] Explanation of reference numerals in the attached figures:

[0032] 1. Multiplication module; 2. Exchange module; 3. Addition module; 4. First selector; 5. Second selector; 6. Third selector; 7. Fourth selector; 8. Rounding operation module; 9. Comparison module; 10. Selection module; 11. Saturation operation module. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0034] The technical solutions provided by the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0035] As attached Figures 1-2 As shown, this embodiment of the invention provides an arithmetic operation structure for RISC-V vector fixed-point instructions, the structure comprising:

[0036] Multiplication module 1 is used to perform signed and / or unsigned multiplication operations on the input data;

[0037] The input terminal of the switching module 2 is connected to the first output terminal of the multiplication module 1. It is used to receive the data output by the multiplication module 1 and the external switching signal, and to perform the switching output.

[0038] Addition module 3, the input of addition module 3 is connected to the output of switching module 2, and is used to receive the switched data output from switching module 2, and perform signed and / or unsigned addition and subtraction operations on the received data;

[0039] The selectors include first selector 4, second selector 5, third selector 6 and fourth selector 7;

[0040] The input terminal of the first selector 4 is connected to the second output terminal of the multiplication module 1 and the first output terminal of the addition module 3 respectively. It is used to receive the multiplication operation result output by the multiplication module 1 and the addition operation result and the average value result output by the addition module 3, and select the output of the input data.

[0041] The input of the second selector 5 is connected to the second output of the adder module 3. It is used to receive the mantissa of the addition result and the mantissa of the multiplication result output by the adder module 3, and select and output the received mantissa.

[0042] The first input of the third selector 6 is used to receive external data and select the external data to output to the fourth selector 7.

[0043] The rounding operation module 8 is used to receive the data output from the first selector 4, the second selector 5 and the addition module 3, and to perform carry-in or round-out operations on the input data in the rounding operation module 8 according to the preset rounding mode in the rounding module.

[0044] Comparison module 9 is used to receive the data output by addition module 3 after reduction or addition and the data output by addition module 3, and to perform a comparison operation between signed and / or unsigned numbers on the received data.

[0045] The saturation operation module 11 is used to receive the data after carry or discard operation output by the rounding operation module 8 and the external saturation valid signal, and to perform saturation operation operation on the received data. The saturation operation output result is then transmitted to the input terminal of the fourth selector 7 along with the data output by the comparison module 9 and the third selector 6. The fourth selector 7 selects the output for the next step of the operation.

[0046] Specifically, it should be noted that the above selector is a multiplexer, meaning that the selector can simultaneously perform multiplexed input and output of multiple data.

[0047] Specifically, the arithmetic operation structure for RISC-V vector fixed-point instructions of the present invention further includes a selection module 10. The input terminal of the selection module 10 is connected to the third output terminal of the addition module 3, and the output terminal is connected to the third selector 6. It is used to select the output data signal of the addition module 3 and the external signal to be output to the third selector 6.

[0048] Specifically, taking an operand with a bit width of N as an example, the multiplication module 1 of the present invention will be explained.

[0049] It should be noted that the specific meaning represented by the encoding in the control signal of the multiplication module 1 with operands of bit width N is an illustrative example. If the encoding of the control signal is changed, its essence remains the same.

[0050] Specifically, the multiplication module 1 in the arithmetic operation unit of the arithmetic operation structure for RISC-V vector fixed-point instructions of this invention differs from the traditional multiplication module (which only supports multiplication operations). The multiplication module 1 of this invention implements a multiplication operation function with bypass capability, that is, performing c × a operation or bypassing 'a' to the output. Taking an operand with a bit width of N as an example, the multiplication module 1 of this invention supports signed number multiplication (N-bit signed number multiplied by N-bit signed number), unsigned number multiplication (N-bit unsigned number multiplied by N-bit unsigned number), and mixed signed and unsigned number multiplication (N-bit signed number multiplied by N-bit unsigned number).

[0051] Specifically, since multiplying two operands with a bit width of N results in a data value with a bit width of 2N, the multiplication result is represented by two signals: Multiplication Module Output 1 and Multiplication Module Output 2. When the multiplication valid signal is high, the multiplication operation is performed with the corresponding sign based on the control signal multiplication sign selection signal. Multiplication Module Output 1 represents the high N bits of the c×a multiplication operation, and Multiplication Module Output 2 represents the low N bits of the c×a multiplication operation. When the multiplication valid signal is low, no multiplication operation is performed, and Multiplication Module Output 2 represents operand a.

[0052] Specifically, the input and output signals of multiplication module 1 and their sources and destinations are shown in Table 1 below:

[0053] Table 1: Input / output signals and their sources and destinations for multiplication module 1

[0054]

[0055] Specifically, when processing data, the data output by multiplication module 1 and addition module 3, as well as the data input to the third selector 6, are all pre-stored in registers.

[0056] Specifically, such as Figure 2 As shown, externally input data can also be pre-stored in multiple registers. Furthermore, as needed, the data or data signals to be processed can be pre-stored in registers before and after processing by each module. When needed, these registers can be retrieved. For example, the input operands in the third selector 6 and the operands in the input switching module 2 can both be pre-stored in registers. It should be noted that this includes, but is not limited to, storing processed data in registers in the addition module 3 and multiplication module 1 as listed above. The selection of registers is determined according to the needs of each module.

[0057] Specifically, when data processing is performed in the switching module 2, when the valid signal in the input switching module 2 is high, the two input signals are swapped and output; when the valid signal in the input switching module 2 is low, the two input signals are not swapped and are output directly.

[0058] Specifically, taking an operand with a bit width of N as an example, the switching module 2 of the present invention will be explained.

[0059] It should be noted that the specific meaning represented by the encoding in the control signal of the exchange module 2 with operands of bit width N is an illustrative example. If the control signal encoding is changed, its essence remains the same.

[0060] Specifically, the switching module 2 in the arithmetic operation structure for RISC-V vector fixed-point instructions of this invention can realize the function of switching input signals. When the valid switching signal is high, the two input signals are swapped, i.e., the switching module output result 1 is the operand b, and the switching module output result 2 is the multiplication module output result 2. When the valid switching signal is low, the two input signals are not swapped, and are directly output, i.e., the switching module output result 1 is the multiplication module output result 2, and the switching module output result 2 is the operand b. This function can control the order of the arithmetic forms of the multiplication module output result 2 and the operand b.

[0061] Specifically, the input and output signals of the switching module 2 and their sources and destinations are shown in Table 2 below:

[0062] Table 2: Input / output signals and their sources and destinations for switching module 2

[0063]

[0064] Specifically, when the input data is processed in the addition module 3, the addition module 3 is enabled when the addition valid signal is high. When the addition valid signal in the input addition module 3 is high and the subtraction operation signal is low, the addition result of the output signal is the sum of the results output in the exchange module 2. When the addition valid signal in the input addition module 3 is high and the subtraction operation signal is high, the addition result of the output signal is the difference between the results output in the exchange module 2.

[0065] Specifically, taking an operand with a bit width of N as an example, the addition module 3 of the present invention will be explained.

[0066] It should be noted that the specific meaning represented by the encoding in the control signal of the addition module 3 with operands of bit width N is an illustrative example. If the control signal encoding is changed, its essence remains the same.

[0067] Specifically, the addition module 3 in the arithmetic operation structure for RISC-V vector fixed-point instructions of this invention implements addition, subtraction, and averaging operations on two input data signals, and generates the corresponding results and mantissas. Taking an operand with a bit width of N as an example, the addition module 3 of this invention supports signed number addition (N-bit signed number plus N-bit signed number); unsigned number addition (N-bit unsigned number plus N-bit unsigned number); signed number subtraction (N-bit signed number minus N-bit signed number); and unsigned number subtraction (N-bit unsigned number minus N-bit unsigned number).

[0068] Specifically, when the addition valid signal is high, the addition module 3 is enabled. The subtraction operation signal can select to perform addition or subtraction operations on two input signal data (e.g., exchange module output result 1 and exchange module output result 2). When the addition valid signal is high and the subtraction operation signal is low, the output signal addition result is the sum of exchange module output result 1 and exchange module output result 2; when the addition valid signal is high and the subtraction operation signal is high, the output signal addition result is the subtraction of exchange module output result 1 and exchange module output result 2. The average value is half of the above addition or subtraction operation result. The mantissa of the multiplication result is the same as the addition result and is used for subsequent rounding and size comparison operations. The mantissa of the addition result is composed of the least significant bit of the addition result signal padded with N-1 zeros. The subtraction result sign signal is the sign of the result of subtracting the output result 2 from the output result 1 of the exchange module when the subtraction function of the addition module 3 is enabled. Whether it is a signed number subtraction or an unsigned number subtraction, the subtraction result sign signal is 1 when the minuend is less than the subtrahend, and 0 when the minuend is greater than or equal to the subtrahend.

[0069] Specifically, the saturation flag signal 1 is the result of judging whether the addition result signal is saturated.

[0070] Specifically, saturation operation means that when the result of an operation is greater than an upper limit or less than a lower limit, the result is equal to the upper or lower limit. Here, we provide an encoding method for the saturation flag signal 1: when the high bit of saturation flag signal 1 is 0, it indicates that the addition result signal is not saturated; when saturation flag signal 1 is 100, it indicates that the addition result signal is a signed number and positively saturated; when saturation flag signal 1 is 101, it indicates that the addition result signal is a signed number and negatively saturated; when saturation flag signal 1 is 110, it indicates that the addition result signal is an unsigned number and the maximum value is saturated; when saturation flag signal 1 is 111, it indicates that the addition result signal is an unsigned number and the minimum value is saturated.

[0071] Specifically, the input and output signals of the adder module 3 and their sources and destinations are shown in Table 3 below:

[0072] Table 3: Input / output signals and their sources and destinations for adder module 3

[0073]

[0074]

[0075] Specifically, the selection module 10 is used to select and output the maximum and minimum values ​​of the input data.

[0076] Specifically, taking an operand with a bit width of N as an example, the selection module 10 of the present invention will be explained.

[0077] It should be noted that the specific meaning represented by the encoding in the control signal of the selection module 10 with an operand of bit width N is an illustrative example. If the control signal encoding is changed, its essence remains the same.

[0078] Specifically, the selection module 10 in the arithmetic operation structure for RISC-V vector fixed-point instructions of this invention implements the functions of selecting maximum and minimum values ​​and selection. Taking an operand with a bit width of N as an example, the selection module 10 of this invention supports selecting the maximum value, that is, when the selection valid signal is low, a selection signal for the maximum value of the N-bit operand a and N-bit operand b is generated according to the sign signal of the subtraction result; and selecting the minimum value, that is, when the selection valid signal is low, a selection signal for the minimum value of the N-bit operand a and N-bit operand b is generated according to the sign signal of the subtraction result. The selection function is as follows: when the selection valid signal is high and the selection flag signal is 1, a selection signal for the N-bit operand a is generated; when the selection valid signal is high and the selection flag signal is 0, a selection signal for the N-bit operand b is generated. The selection module 10 is connected to a multiplexer 3, which controls the output of the selection module to either operand a or operand b.

[0079] Specifically, the input and output signals and their sources and destinations of the selection module 10 are shown in Table 4 below;

[0080] Table 4: Input / output signals and their sources and destinations for module 10

[0081]

[0082]

[0083] Specifically, taking an operand with a bit width of N as an example, the comparison module 9 of the present invention will be explained.

[0084] It should be noted that the specific meaning represented by the encoding in the control signal of the comparison module 9 with operands of bit width N is an illustrative example. If the control signal encoding is changed, its essence remains the same.

[0085] Specifically, the comparison module 9 in the arithmetic operation structure for RISC-V vector fixed-point instructions of the present invention is used to implement the comparison operation for two data signals. According to the comparison selection signal, it determines whether the two numbers satisfy the relationship of greater than, less than, equal to, greater than or equal to, less than or equal to, and not equal to. According to the comparison sign selection signal, it determines whether it is a comparison of two signed numbers or two unsigned numbers. Taking an operand with a bit width of N as an example, the comparison module 9 in this invention supports: signed number greater than operation, i.e., determining whether the output result 1 of the N-bit signed number exchange module is greater than the output result 2 of the N-bit signed number exchange module; unsigned number greater than operation, i.e., determining whether the output result 1 of the N-bit unsigned number exchange module is greater than the output result 2 of the N-bit unsigned number exchange module; signed number less than operation, i.e., determining whether the output result 1 of the N-bit signed number exchange module is less than the output result 2 of the N-bit signed number exchange module; unsigned number less than operation, i.e., determining whether the output result 1 of the N-bit unsigned number exchange module is less than the output result 2 of the N-bit unsigned number exchange module; and equal to operation, i.e., determining whether the output result 1 of the N-bit exchange module is equal to the output result of the N-bit exchange module. Result 2; Inequality operation, i.e., determining whether the output result 1 of the N-bit switching module is not equal to the output result 2 of the N-bit switching module; Signed number greater than or equal to operation, i.e., determining whether the output result 1 of the N-bit signed number switching module is greater than or equal to the output result 2 of the N-bit signed number switching module; Unsigned number greater than or equal to operation, i.e., determining whether the output result 1 of the N-bit unsigned number switching module is greater than or equal to the output result 2 of the N-bit unsigned number switching module; Signed number less than or equal to operation, i.e., determining whether the output result 1 of the N-bit signed number switching module is less than or equal to the output result 2 of the N-bit signed number switching module; Unsigned number less than or equal to operation, i.e., determining whether the output result 1 of the N-bit unsigned number switching module is less than or equal to the output result 2 of the N-bit unsigned number switching module. The greater than and less than operations are determined by the sign signal of the subtraction result. The equality and inequality operations are determined by a non-zero marker signal, which is obtained by reducing or performing an OR operation on the mantissa signal of the multiplication result. A high non-zero marker signal indicates that the two operands are unequal, while a low non-zero marker signal indicates that the two operands are equal. The greater than or equal to and less than or equal to operations are determined by the sign signal of the subtraction result and the non-zero marker signal. A low non-zero marker signal indicates that the relationship between the two operands is greater than or equal to, or less than or equal to. The comparison result has a 1-bit width. If the inequality is true, the comparison result is 1; if the inequality is false, the comparison result is 0. The output signal of the comparison module extends the 1-bit comparison result by padding the high-order bits with N-1 zeros to N bits.

[0086] Specifically, the input and output signals of the comparison module 9 and their sources and destinations are shown in Table 5 below;

[0087] Table 5: Input / output signals and their sources and destinations for Comparison Module 9

[0088]

[0089] Specifically, in the rounding operation module 8, when processing the input data, the rounding operation module outputs the result after rounding the input data when the input rounding valid signal is high, and the rounding operation module outputs the original value of the input signal when the rounding valid signal is low.

[0090] Specifically, taking an operand with a bit width of N as an example, the rounding operation module 8 of the present invention is explained;

[0091] It should be noted that the specific meaning represented by the encoding in the control signal of the rounding operation module 8 with an operand of bit width N is an illustrative example. If the control signal encoding is changed, its essence remains the same.

[0092] Specifically, the rounding operation in the arithmetic operation structure for RISC-V vector fixed-point instructions of this invention is an operation that carries over or discards the mantissa of the operand according to the rounding mode. Specifically, the carry and discard are determined according to the rounding mode (not described in detail in this invention), and can be selectively set in the rounding mode selection signal. Taking an operand with a bit width of N as an example, the rounding operation module 8 in the arithmetic operation structure for RISC-V vector fixed-point instructions of this invention can perform rounding processing on the input data signal and the multiplication-addition selection output result. When the rounding valid signal is high, the output result of the rounding operation module is the result after rounding the input data; when the rounding valid signal is low, the output result of the rounding operation module is the original value of the input signal, without any processing. The rounding mode to be used can be selected according to the control signal rounding mode selection signal. When the rounding valid signal is high, the saturation flag signal 2 indicates the saturation status of the output result of the rounding operation module; when the rounding valid signal is low, the saturation flag signal 2 is the value of the saturation flag 1, and the value is not updated.

[0093] Specifically, the input and output signals and their sources and destinations of the rounding operation module 8 are shown in Table 6 below.

[0094] Table 6: Input / output signals and their sources and destinations for rounding operation module 8

[0095]

[0096]

[0097] Specifically, in the saturation operation module 11, when the input saturation valid signal is high, the output result is the data after the rounding operation module 8 has undergone saturation operation; when the input saturation valid signal is low, the result of the saturation operation module is the original value of the output result of the rounding operation module.

[0098] Specifically, taking an operand with a bit width of N as an example, the saturation operation module 11 of the present invention will be explained;

[0099] It should be noted that the specific meaning represented by the encoding in the control signal of the saturation operation module 11 with an operand of bit width N is an illustrative example. If the control signal encoding is changed, its essence remains the same.

[0100] Specifically, in the saturation operation module 11 of the arithmetic operation structure for RISC-V vector fixed-point instructions of this invention, the saturation operation is such that if the result of the operation is greater than an upper limit or less than a lower limit, the result is equal to the upper or lower limit. Typically, when the operands are signed numbers, the upper limit is the largest representable positive number, and the lower limit is the smallest representable negative number. When the operands are unsigned numbers, the upper limit is the largest representable number, and the lower limit is 0.

[0101] Specifically, the saturation operation module 11 in the arithmetic operation structure for RISC-V vector fixed-point instructions of the present invention can perform saturation processing on the input data signal. When the saturation valid signal is high, the output result of the rounding operation module is subjected to corresponding saturation operation according to the saturation state represented by the saturation marker signal 2. When the saturation valid signal is low, the result of the saturation operation module is the original value of the output result of the rounding operation module, and no saturation operation processing is performed.

[0102] Specifically, the input and output signals of the saturation module and their sources and destinations are shown in Table 7 below;

[0103] Table 7: Input / output signals and their sources and destinations for the saturation module

[0104]

[0105] Specifically, the control signals and their meanings in the arithmetic operation structure for RISC-V vector fixed-point instructions of the present invention are shown in Table 8 below:

[0106] Table 8: Control signals and their meanings in an arithmetic operation structure for RISC-V vector fixed-point instructions.

[0107]

[0108]

[0109] Specifically, such as Figure 1As shown, the connection and data transmission method of each module of the arithmetic operation structure for RISC-V vector fixed-point instructions of the present invention is as follows:

[0110] Specifically, the multiplication module 1, addition module 3, exchange module 2, comparison module 9, selection module 10, rounding operation module 8, and saturation operation module 11 provide arithmetic functions, process input data and perform calculations, and the selector is mainly used to select the corresponding data as the output signal according to different values ​​of the control signal.

[0111] Specifically, the arithmetic operation structure for RISC-V vector fixed-point instructions in this invention has a data signal and a control signal as input signals. The data signal includes operand a, operand b, and operand c, and the bit widths of operand a, operand b, and operand c are usually equal, assumed to be N, and in general, assumed to be powers of 2, such as 8, 16, 32, 64, etc. The output signal is the output result signal, and the bit width is the same as the input data signal, which is N.

[0112] Specifically, the input signals operand a, operand c, multiplication valid signal, and multiplication sign selection signal serve as the input signals for multiplication module 1. Multiplication module 1 outputs two signals: multiplication module output result 1 and multiplication module output result 2. Multiplication module output result 1 serves as one of the input signals for multiplexer 1, and multiplication module output result 2 serves as one of the input signals for switching module 2, connecting multiplication module 1 with switching module 2 and multiplexer 1.

[0113] Specifically, the input signal operand b, the multiplication module output result 2 from multiplication module 1, and the exchange valid signal are used as the input signals of exchange module 2. The output signals of exchange module 2 are exchange module output result 1 and exchange module output result 2. The output signals of exchange module 2, exchange module output result 1 and exchange module output result 2, serve as two of the input signals of addition module 3, connecting exchange module 2 and addition module 3 together.

[0114] Specifically, the output results 1 and 2 from the switching module 2, along with the control signals addition sign selection signal, addition valid signal, and subtraction operation signal, serve as the input signals for the addition module 3. The output signals of the addition module 3 include saturation flag signal 1, average result, addition result, mantissa of addition result, mantissa of multiplication result, and subtraction result sign signal. The average result and addition result from the output signals of the addition module 3 serve as two input signals to the first selector 4, connecting the addition module 3 to the first selector 4. The saturation flag signal 1 from the output signals of the addition module 3 serves as one input signal to the rounding operation module 8, connecting the addition module 3 to the rounding operation module 8. The mantissa of the addition result and the mantissa of the multiplication result from the output signals of the addition module 3 serve as two input signals to the second selector 5, connecting the addition module 3 to the second selector 5. The mantissa of the addition result is formed by padding N-1 zeros in the least significant bit of the addition result signal. The mantissa of the multiplication result output by adder module 3 is reduced or calculated to obtain a non-zero marker signal. This non-zero marker signal serves as one of the input signals to compareer module 9, connecting adder module 3 and compareer module 9 together. The sign signal of the subtraction result output by adder module 3 serves as one of the input signals to compareer module 9 and selector module 10, connecting adder module 3 and compareer module 9, and adder module 3 and selector module 10 together.

[0115] Specifically, the multiplication module output result 1 from multiplication module 1, the average result and addition result from addition module 3, and the control signal multiply-add selection signal are used as input signals for the first selector 4. The output signal of the first selector 4 is the multiply-add selection output result. The multiply-add selection output result of the first selector 4 is used as one of the input signals of the rounding operation module 8, connecting the first selector 4 and the rounding operation module 8 together.

[0116] Specifically, the mantissa of the addition result, the mantissa of the multiplication result, and the control signal multiplication validity signal from the addition module 3 are used as input signals to the second selector 5. The output signal is the mantissa selection result, which is used as one of the input signals to the rounding operation module 8, connecting the second selector 5 and the rounding operation module 8 together.

[0117] Specifically, the multiply-accumulate selection output from the first selector 4, the saturation flag signal 1 from the adder module 3, the mantissa selection result from the second selector 5, and the control signals rounding valid signal and rounding mode selection signal serve as input signals to the rounding operation module 8. The output signals include the rounding operation module output result and the saturation flag signal 2. The rounding operation module 8 output result and the saturation flag signal 2 serve as two of the input signals to the saturation operation module 11, connecting the rounding operation module 8 and the saturation operation module 11 together.

[0118] Specifically, the rounding operation module output from rounding operation module 8, the saturation flag signal 2, and the saturation valid control signal are used as input signals to saturation operation module 11. The output signal is the output of saturation operation module 11, which is used as one of the input signals to the fourth selector 7, connecting saturation operation module 11 to multiplexer 4.

[0119] Specifically, the subtraction result sign signal from the addition module 3 and the control signal comparison selection signal are used as input signals to the comparison module 9. The output signal is the output result of the comparison module, which is used as one of the input signals of the fourth selector 7, connecting the comparison module 9 and the fourth selector 7 together.

[0120] Specifically, the subtraction result sign signal from the addition module 3, along with the maximum / minimum value selection signal, the selection valid signal, and the selection flag signal, serve as the input signals to the selection module 10. The output signal serves as the input control signal to the multiplexer 3, connecting the selection module 10 to the third selector 6.

[0121] In this invention, the arithmetic operation unit of an arithmetic operation structure for RISC-V vector fixed-point instructions uses operands a and b, along with a control signal from selection module 10, as input signals for a third selector 6. The output signal is the output result of the selection module, which serves as one of the input signals for a fourth selector 7, connecting the third selector 6 and the fourth selector 7 together.

[0122] Specifically, the output results from the saturation operation module 11, the comparison module 9, the selection module 6, and the control signal multiply-accumulate output selection signal are used as the input signals of the fourth selector 7. The output signal is the output result signal, which serves as the output signal of the arithmetic operation structure for RISC-V vector fixed-point instructions of this invention.

[0123] In some optional implementations of this embodiment, taking an operand with a bit width of N as an example, the workflow of an arithmetic operation structure for RISC-V vector fixed-point instructions of the present invention for data and signal processing of fixed-point vectors is as follows:

[0124] In multiplication module 1, operands a and c enter multiplication module 1. The control signal multiplication validity signal determines whether to perform a multiplication operation. If a multiplication operation is to be performed, the control signal multiplication sign selection signal is used to perform a multiplication operation of the corresponding sign type. Otherwise, the low-order bit of the multiplication is multiplication module output result 2, which is operand a.

[0125] In exchange module 2, operand b and the multiplication module output result 2 enter exchange module 2. The exchange module determines whether to swap these two operands based on the control signal and the valid exchange signal. This function controls the order of the arithmetic form of the multiplication module output result 2 and operand b.

[0126] In addition module 3, this module implements addition, subtraction, and averaging operations on two input data signals. Its functional expressions are c×a+b, c×ab, bc×a, a+b, ab, ba, (a+b) / 2, (ab) / 2, and (ba) / 2. The output results 1 and 2 from the exchange module enter addition module 3. The addition validity control signal determines whether to perform addition on the input operands. If addition is required, the subtraction operation signal determines whether to perform subtraction. During addition or subtraction, the addition sign selection control signal also determines whether to perform signed addition or subtraction. The output signal addition result is the result of addition or subtraction; the average result is half of the addition result; the mantissa of the addition result is composed of the least significant bit of the addition result signal with low-order zero padding; the mantissa of the multiplication result is the same as the addition result, and after reduction or ORing, a non-zero signal is obtained; the subtraction result sign signal is the sign of the subtraction result when the subtraction function of addition module 3 is enabled, whether it is signed subtraction or unsigned subtraction, the subtraction result sign signal is 1 when the minuend is less than the subtrahend, and 0 when the minuend is greater than or equal to the subtrahend; the saturation mark signal 1 is the result of judging whether the addition result signal is saturated. The so-called saturation operation means that when the operation result is greater than an upper limit or less than a lower limit, the result is equal to the upper limit or lower limit. This document provides an encoding method for the saturation flag signal 1. When the high bit of the saturation flag signal 1 is 0, it indicates that the addition result signal is not saturated; when the saturation flag signal 1 is 100, it indicates that the addition result signal is a signed number and positively saturated; when the saturation flag signal 1 is 101, it indicates that the addition result signal is a signed number and negatively saturated; when the saturation flag signal 1 is 110, it indicates that the addition result signal is an unsigned number and the maximum value is saturated; and when the saturation flag signal 1 is 111, it indicates that the addition result signal is an unsigned number and the minimum value is saturated.

[0127] In the first selector 4, the multiplication module output result 1, the average result, and the addition result are input to the first selector 4. Based on the control signal multiply-accumulate selection signal, the selector chooses which input signal to output as the value of the multiply-accumulate selection output result. The multiply-accumulate selection output result signal serves as the input signal for the rounding operation module 8.

[0128] In the second selector 5, the mantissa of the addition result is padded with 0s at the least significant bit and then combined with the mantissa of the multiplication result before entering the second selector 5. When the control signal for multiplication is high, the mantissa selection result is the mantissa of the multiplication result; when the control signal for multiplication is low, the mantissa selection result is the mantissa of the addition result. The mantissa selection result serves as the input signal for the rounding operation module 8.

[0129] In rounding operation module 8, the output result of the multiplication-addition selection is rounded. When the rounding valid signal is high, the output result of the rounding operation module is the result after rounding the input data; when the rounding valid signal is low, the output result of the rounding operation module is the original value of the input signal, without any processing. The rounding mode can be selected according to the control signal rounding mode selection signal. When the rounding valid signal is high, saturation flag signal 2 indicates the saturation status of the output result of the rounding operation module; when the rounding valid signal is low, saturation flag signal 2 is the value of saturation flag 1, and the value is not updated.

[0130] In the saturation operation module 11, the output result of the rounding operation module and the saturation flag signal enter the saturation operation module 11. When the saturation valid signal is high, the output result of the saturation operation module is the result of the rounding operation module output result with saturation operation processing; when the saturation valid signal is low, the output result of the saturation operation module is the rounding operation module output result, without saturation operation processing. The output result of the saturation operation module serves as the input signal of the fourth selector 7.

[0131] In selection module 10, the subtraction result sign signal, maximum / minimum value selection signal, selection valid signal, and selection flag signal enter selection module 10. When the selection valid signal is low, the maximum value of N-bit operand a and N-bit operand b is output; the minimum value is selected, i.e., when the selection valid signal is low, the minimum value of N-bit operand a and N-bit operand b is output; the function is selected, i.e., when the selection valid signal is high and the selection flag signal is 1, N-bit operand a is output; when the selection valid signal is high and the selection flag signal is 0, N-bit operand b is output. The control signal, operand a, and operand b output by selection module 10 enter the third selector 6, and the output result of selection module 10 selects the output operands a and b according to the control signal output by selection module 10.

[0132] In comparison module 9, this module performs comparison operations on two data signals. Based on the comparison selection signal, it determines whether the two signed or unsigned numbers satisfy the relationships of greater than, less than, equal to, not equal to, greater than or equal to, or less than or equal to. The comparison sign selection signal determines whether it's a comparison of two signed or unsigned numbers. Since the comparison operation uses the subtraction function of the adder, the comparison sign selection signal should be consistent with the addition sign selection signal. The comparison selection signal determines the type of comparison operation performed on the operands. When the comparison type is to determine whether they are equal or not equal, it uses the non-zero flag signal. A non-zero flag of 1 indicates that the two operands are not equal, and a non-zero flag of 0 indicates that the two operands are equal. When the comparison type is to determine whether they are greater than, less than, greater than or equal to, or less than or equal to, it uses a combination of the non-zero flag signal and the subtraction result sign signal. The comparison result has a bit width of 1 bit; a comparison result of 1 indicates that the inequality is true, and a comparison result of 0 indicates that the inequality is false. The output signal comparison module 9 outputs a result signal that extends the 1-bit comparison result by padding the high-order bits with 0, that is, padding the comparison result with N-1 zeros to N bits.

[0133] In the fourth selector 7, the output results of the saturation operation module, the comparison module, and the selection module are input to the fourth selector 7. Based on the control signal multiply-accumulate output selection signal, the output selector chooses which input signal to use as the value of the output result signal. The output result signal serves as the output signal of the arithmetic operation unit of the RISC-V vector fixed-point computation instruction of this invention.

[0134] It should be noted that the specific meaning represented by the encoding of the control signals in the above workflow is an example. If the encoding of the control signals is changed, the essence remains the same.

[0135] Specifically, based on the arithmetic operation structure for RISC-V vector fixed-point instructions according to the present invention, the specific data operation table for performing vector fixed-point instruction arithmetic operations is shown in Table 9 below;

[0136] Table 9: An Arithmetic Operation Structure for RISC-V Vector Fixed-Point Instructions Specific Data Operations for Vector Fixed-Point Instruction Arithmetic Operations

[0137]

[0138]

[0139]

[0140] It should be noted that the arithmetic operation structure for RISC-V vector fixed-point instructions in this invention requires preprocessing of the input data when performing arithmetic operations on vector fixed-point instructions. This preprocessing includes decoding, filtering, or classifying the input data to ensure that the format and type of the input data correspond to the input type and format of the corresponding module. This allows the input data or signals to correspond with the processing module and perform functional operations such as data processing, conversion, and output. When performing operations on the data, a single module can receive multiple preset types or preset formats of data. By reusing multiple modules during data operations, hardware resources are saved and resource utilization is improved. At the same time, a single operation module can support multiple types of vector fixed-point arithmetic operations, effectively reducing the area and power consumption of the operation components, thereby improving operational efficiency.

[0141] Specifically, such as Figure 2 As shown, the multiplication module 1, exchange module 2, addition module 3, selector, rounding operation module 8, selection module 10, comparison module 9 and saturation operation module 11 in the arithmetic operation structure for RISC-V vector fixed-point instructions of the present invention perform pipelined calculations on the input signals and data through multiple levels when performing arithmetic operations on vector fixed-point instructions.

[0142] Specifically, such as Figure 2 As shown, in the arithmetic operation structure for RISC-V vector fixed-point instructions of the present invention, the multiplication module 1 and the registers corresponding to the output data of the multiplication module 1 constitute the first pipelined computation layer and the second pipelined computation layer, the exchange module 2, the addition module 3, the first selector 4 and the second selector 5 constitute the third pipelined computation layer, the rounding operation module 8, the saturation operation module 11, the comparison module 9, the selection module 10, the third selector 6 and the fourth selector 7 constitute the fourth pipelined computation layer.

[0143] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Additionally, the terms "front," "back," "left," "right," "upper," and "lower" in this document refer to the placement shown in the accompanying drawings.

[0144] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An arithmetic operation structure for RISC-V vector fixed-point instructions, characterized in that, include: A multiplication module, which is used to perform signed and / or unsigned multiplication operations on the input data; A switching module, the input of which is connected to the first output of the multiplication module, is used to receive the data output by the multiplication module, externally input data, and external switching signals, and to perform switching output. An addition module, wherein the input of the addition module is connected to the output of the switching module, is used to receive the switched data output from the switching module and perform signed and / or unsigned addition and subtraction operations on the received switched data; The selector includes a first selector, a second selector, a third selector, and a fourth selector; The input terminal of the first selector is connected to the second output terminal of the multiplication module and the first output terminal of the addition module, respectively, for receiving the multiplication operation result output by the multiplication module and the addition operation result and average value result output by the addition module, and for selecting and outputting the input data; The input terminal of the second selector is connected to the second output terminal of the addition module, and is used to receive the mantissa of the addition result and the mantissa of the multiplication result output by the addition module, and select and output the received mantissa; The first input terminal of the third selector is used to receive external data and select and output the external data to the fourth selector. A rounding operation module is used to receive data output from the first selector, the second selector, and the addition module, and to perform rounding or rounding on the input data according to the rounding mode. The comparison module is used to receive the data output by the addition module after reduction and the data output by the addition module, and to perform a comparison operation between signed and / or unsigned numbers on the received data; The saturation operation module receives the data after carry or truncation operation output by the rounding operation module and the external saturation valid signal data, performs saturation operation on the received data, and transmits the saturation operation output along with the data output by the comparison module and the third selector to the input of the fourth selector, which then selects and outputs the result.

2. The arithmetic operation structure for RISC-V vector fixed-point instructions according to claim 1, characterized in that, It also includes a selection module, the input of which is connected to the third output of the addition module and the output of which is connected to the third selector. The selection module is used to select the output data signal of the addition module and the external signal to be received, and to select the output to the third selector.

3. The arithmetic operation structure for RISC-V vector fixed-point instructions according to claim 1, characterized in that, When processing data, the data output by the multiplication module and the addition module, as well as the data input to the third selector, are all pre-stored in registers.

4. The arithmetic operation structure for RISC-V vector fixed-point instructions according to claim 1, characterized in that, When data processing is performed in the switching module, if the valid signal in the input switching module is high, the two input signals are swapped and output; if the valid signal in the input switching module is low, the two input signals are not swapped and are output directly.

5. The arithmetic operation structure for RISC-V vector fixed-point instructions according to claim 1, characterized in that, When the input data is processed in the addition module, the addition module is enabled when the addition valid signal is high. When the addition valid signal in the input addition module is high and the subtraction operation signal is low, the output signal addition result is the sum of the results output in the exchange module. When the addition valid signal in the input addition module is high and the subtraction operation signal is high, the output signal addition result is the difference between the results output in the exchange module.

6. The arithmetic operation structure for RISC-V vector fixed-point instructions according to claim 1, characterized in that, The selection module is used to select and output the maximum and minimum values ​​of the input data.

7. The arithmetic operation structure for RISC-V vector fixed-point instructions according to claim 1, characterized in that, In the rounding operation module, when processing the input data, the output result of the rounding operation module is the result of the input data rounding operation when the input rounding valid signal is high, and the output result of the rounding operation module is the original value of the input signal when the rounding valid signal is low.

8. The arithmetic operation structure for RISC-V vector fixed-point instructions according to claim 1, characterized in that, In the saturation operation module, when the input saturation valid signal is high, the output result is the data after performing a saturation operation on the output result of the rounding operation module; when the input saturation valid signal is low, the result of the saturation operation module is the original value of the output result of the rounding operation module.

9. The arithmetic operation structure for RISC-V vector fixed-point instructions according to claim 1, characterized in that, When performing arithmetic operations on vector fixed-point instructions, the multiplication module, the exchange module, the addition module, the selector, the rounding operation module, the selection module, the comparison module, and the saturation operation module perform pipelined computation on the input signals and data through multiple pipelined computation layers.

10. An arithmetic operation structure for RISC-V vector fixed-point instructions according to claim 9, characterized in that, The multiplication module and the corresponding registers of the output data of the multiplication module constitute the first pipelined computing layer and the second pipelined computing layer. The exchange module, the addition module, the first selector and the second selector constitute the third pipelined computing layer. The rounding operation module, the saturation operation module, the comparison module, the selection module, the third selector and the fourth selector constitute the fourth pipelined computing layer.

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