Task scheduling unit, wafer-level chip, computing device and task scheduling method

Abstract

Embodiments of the present application provide a task scheduling unit, a wafer-level chip, a computing device and a task scheduling method. The task scheduling unit comprises: a progress detection subunit, configured to acquire first progress information of a first chip where the task scheduling unit is located, the first progress information being used to indicate a task execution progress of the first chip; a sending subunit, configured to send the first progress information to a second chip, the first chip and the second chip being located on a same wafer, and the task execution progress of the first chip being less than that of the second chip; and a transfer subunit, configured to receive first request information sent by the second chip in response to the first progress information, and transfer at least part of tasks executed by the first chip to the second chip for execution according to the first request information, the first request information being generated by the second chip according to the first progress information and the task execution progress of the second chip. The present scheme can improve the utilization rate of chips on a wafer-level chip, thereby improving the operation efficiency.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a task scheduling unit, a wafer-level chip, a computing device, and a task scheduling method. Background Technology

[0002] A wafer-level chip consists of a Network On Chip (NoC) and multiple chips on the wafer. The NoC connects the chips together, enabling reliable communication between them. During the manufacturing process of wafer-level chips, defects in the wafer surface and integration processes can lead to defects in some chips on the wafer. Defective chips have lower computing power than normal chips.

[0003] Currently, wafer-level chip manufacturers identify defective chips on the wafer during wafer-level chip testing and disable these defective chips, using only those without defects on the wafer-level chip.

[0004] However, disabling defective chips at the wafer level and using only defect-free chips will result in low chip utilization at the wafer level, leading to lower computational efficiency. Summary of the Invention

[0005] In view of this, embodiments of this application provide a task scheduling unit, a wafer-level chip, a computing device, and a task scheduling method to at least solve or alleviate the above-mentioned problems.

[0006] According to a first aspect of the embodiments of this application, a task scheduling unit is provided, comprising: a progress detection subunit, configured to acquire first progress information of a first chip on which the task scheduling unit is located, the first progress information being used to indicate the task execution progress of the first chip; a sending subunit, configured to send the first progress information to a second chip, the first chip and the second chip being located on the same wafer, the task execution progress of the first chip being less than the task execution progress of the second chip; and a transfer subunit, configured to receive a first request information sent by the second chip in response to the first progress information, and transfer at least part of the task executed by the first chip to the second chip for execution according to the first request information, the first request information being generated by the second chip according to the first progress information and the task execution progress of the second chip.

[0007] According to a second aspect of the embodiments of this application, a task scheduling method is provided, comprising: acquiring first progress information of a first chip, wherein the first progress information is used to indicate the task execution progress of the first chip; sending the first progress information to a second chip, wherein the first chip and the second chip are located on the same wafer, and the task execution progress of the first chip is less than the task execution progress of the second chip; receiving first request information sent by the second chip in response to the first progress information, wherein the first request information is generated by the second chip based on the first progress information and the task execution progress of the second chip; and transferring at least part of the tasks executed by the first chip to the second chip for execution based on the first request information.

[0008] According to a third aspect of the embodiments of this application, a chip is provided, including the task scheduling unit described in the first aspect above.

[0009] According to a fourth aspect of the embodiments of this application, a wafer-level chip is provided, including a plurality of chips according to the third aspect described above, wherein the plurality of chips communicate with each other via an on-chip network.

[0010] According to a fifth aspect of the embodiments of this application, a computing device is provided, comprising: a wafer-level chip as described in the fourth aspect above.

[0011] As can be seen from the above technical solution, the progress detection subunit can detect the task execution progress of the first chip, and the sending subunit sends the first progress information that can indicate the task execution progress to the second chip, and receives the first request information sent by the second chip. Thus, according to the first request information, some tasks executed by the first chip can be transferred to the second chip for execution. The computing efficiency of the first chip is lower than that of the second chip. This realizes the scheduling of some tasks of the chip with lower computing efficiency to the chip with higher computing efficiency. Since the chip with lower computing efficiency is enabled, the chip with lower computing efficiency is the chip with defects in the wafer-level chip. Compared with disabling the chip with defects in the wafer-level chip, the utilization rate of the chips on the wafer-level chip is improved, and the overall computing speed of the wafer-level chip is not reduced due to the enablement of the chip with defects. Therefore, the computing efficiency of the wafer-level chip is improved. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0013] Figure 1This is a schematic diagram of a computing device according to an embodiment of this application;

[0014] Figure 2 This is a schematic diagram of a wafer-level chip according to an embodiment of this application;

[0015] Figure 3 This is a schematic diagram of a chip according to one embodiment of this application;

[0016] Figure 4 This is a schematic diagram of a task scheduling unit according to an embodiment of this application;

[0017] Figure 5 This is an example diagram of chip information interaction according to an embodiment of this application;

[0018] Figure 6 This is an example diagram of chip information interaction according to another embodiment of this application;

[0019] Figure 7 This is a flowchart of a task scheduling method according to an embodiment of this application;

[0020] Figure 8 This is a flowchart of a task scheduling method according to another embodiment of this application. Detailed Implementation

[0021] The present application is described below based on embodiments, but it is not limited to these embodiments. In the detailed description of the present application below, certain specific details are described in detail. Those skilled in the art can fully understand the present application without these details. To avoid obscuring the essence of the present application, well-known methods, processes, and flows are not described in detail. Furthermore, the accompanying drawings are not necessarily drawn to scale.

[0022] First, some nouns or terms that appear in the description of the embodiments of this application shall be interpreted as follows.

[0023] Network on Chip (NoC): Network on Chip (NoC) is a new communication method for System on Chip (SoC). NoC connects multiple chips on a single chip, enabling reliable communication between them. The topologies that can be formed by the chips in a NoC include 2D / 3D mesh networks, torus networks, and ring networks.

[0024] Wafer-scale chip: A wafer-scale chip is an assembly of multiple chips formed on the same wafer. The chips in a wafer-scale chip communicate with each other through an on-chip network. Due to the short distance between the chips, wafer-scale chips have stronger data processing capabilities and speed.

[0025] Progress information: Progress information is used to indicate the chip's task execution progress. After the system's control unit assigns tasks to the chip, it can detect the chip's task status to determine the chip's task execution progress. The chip's task execution progress can be the number of completed tasks, the percentage of completed tasks out of the total number of tasks, etc.

[0026] Computing device

[0027] Figure 1 This is a schematic diagram of a computing device according to an embodiment of this application. Figure 1 As shown, the computing device 300 may include a plurality of processors 301. As an example, such as... Figure 1 As shown, computing device 300 may include processor 0, processor 1, processor 2 and processor 3, but it should be understood that the number of processors 301 is not limited thereto.

[0028] like Figure 1 As shown, the computing device 300 may also include a memory 302. The memory 302 in the computing device 300 may be a main memory (or simply main memory or RAM), used to store instruction information and / or data information represented by data signals, such as data provided by the memory access processor 301 (e.g., the result of an operation), and may also be used to realize data exchange between the processor 301 and the external storage device 307 (or auxiliary memory or external memory).

[0029] In some situations, the processor 301 may need to access memory 302 to retrieve or modify data in memory 302. Since access to memory 302 is relatively slow, to alleviate the speed difference between the processor 301 and memory 302, the computing device 300 also includes a cache memory 304 coupled to the bus 303. The cache memory 304 is used to cache program data or message data that may be repeatedly accessed in memory 302. The cache memory 304 can be implemented using a storage device of the type Static Random-Access Memory (SRAM). The cache memory 304 can be a multi-level structure, such as a three-level cache structure with a Level 1 cache (L1 cache), a Level 2 cache (L2 cache), and a Level 3 cache (L3 cache), or a cache structure with more than three levels or other types of cache structures. In some embodiments, a portion of the cache memory 304 (e.g., the Level 1 cache, or the Level 1 cache and the Level 2 cache) can be integrated inside the processor 301 or integrated with the processor 301 in the same on-chip system.

[0030] Information exchange between memory 302 and cache memory 304 is typically organized in blocks. In some embodiments, cache memory 304 and memory 302 may be divided into data blocks of the same spatial size, and these data blocks can serve as units for data exchange between cache memory 304 and memory 302 (including one or more data of a preset length). For clarity, the data blocks in cache memory 304 are referred to as cache blocks (or cache lines), and different cache blocks have different cache block addresses; the data blocks in memory 302 are referred to as memory blocks, and different memory blocks have different memory block addresses. Cache block addresses include, for example, physical address tags used to locate the data blocks.

[0031] Due to space and resource limitations, cache memory 304 cannot cache all the contents of memory 302; that is, the storage capacity of cache memory 304 is usually smaller than that of memory 302, and the addresses of individual cache blocks provided by cache memory 304 cannot correspond to all the memory block addresses provided by memory 302. When processor 301 needs to access memory, it first accesses cache memory 304 via bus 303 to determine whether the content to be accessed is already stored in cache memory 304. If it is, cache memory 304 is hit, and processor 301 directly retrieves the content to be accessed from cache memory 304. If the content to be accessed by processor 301 is not in cache memory 304, processor 301 needs to access memory 302 via bus 303 to find the corresponding information in memory 302. Because the access speed of cache memory 304 is very fast, when cache memory 304 is hit, the efficiency of processor 301 can be significantly improved, thereby improving the performance and efficiency of the entire computing device 300.

[0032] like Figure 1 As shown, processor 301, cache memory 304, and memory 302 are packaged in a system-on-chip (SoC) 305. Designers can configure the SoC architecture to ensure secure communication between the various components in the computing device 300. Processor 301 may be a wafer-level chip, and system-on-chip 305 may include one or more wafer-level chips; this application does not limit this.

[0033] The computing device 300 may also include hardware devices such as a display device (not shown), an audio device (not shown), and an input / output device 306. The input / output device 306 may be, for example, a text, audio, and video input / output device. As an example, Figure 1Input / output devices 0, 1, 2, and 3 are shown, but it should be understood that the number of input / output devices is not limited thereto. Storage devices include, for example, hard disks, optical disks, and flash memory, which are coupled to bus 303 via corresponding interfaces for information access. Display devices are coupled to bus 303 via corresponding graphics cards for displaying information according to display signals provided by bus 303. The computing device 300 typically also includes communication devices (not shown), thus enabling communication with networks or other devices in various ways. Communication devices may include, for example, one or more communication modules. As an example, a communication device may include a wireless communication module suitable for a specific wireless communication protocol. For instance, a communication device may include a WLAN module for implementing Wi-Fi communication conforming to the IEEE 802.11 standard; a communication device may also include a WWAN module for implementing wireless wide-area communication conforming to cellular or other wireless wide-area protocols; a communication device may also include a Bluetooth module or other communication modules using other protocols, or other custom-type communication modules; a communication device may also be a port for serial data transmission.

[0034] It should be understood that Figure 1 The computing device 300 shown is an exemplary structure, and the structure may vary depending on the motherboard, operating system, and instruction set architecture of different computer systems.

[0035] wafer-level chips

[0036] Figure 2 This is a schematic diagram of a wafer-level chip according to an embodiment of this application. The wafer-level chip 100 includes a wafer 10 and a plurality of chips 20 disposed on the wafer 10. The chips 20 communicate with each other through an on-chip network. The chips 20 may be processors (CPU), graphics processing units (GPUs), infrastructure processing units (IPUs), etc. Chips 20 may include one or more processor cores, and different processor cores communicate with each other through an on-chip network. Chips 20 may include one or more processing elements (PEs), and each processing element (PE) is a logic core of the processor. One logic core can run one thread. Each processing element (PE) includes multiple arithmetic units, such as an arithmetic logic unit (ALU), a floating point unit (FPU), a matrix multiplication unit, etc., and the arithmetic units communicate with each other through an on-chip network.

[0037] A wafer-level chip 100 is a chip assembly comprising multiple chips 20 fabricated from a silicon wafer. The chips 20 can communicate with each other via an on-chip network. During the wafer-level chip manufacturing process, defects on the wafer surface, integration processes, and other factors can lead to defects or malfunctions in some chips. Defective chips have lower computing power than normal chips. Different chips can have different defects; for example, some defective chips may have lower speeds for addition operations but normal speeds for multiplication operations, while others may have lower speeds for multiplication operations but normal speeds for addition operations. For ease of description, in the following description, chips with defects on the wafer-level chip are defined as defective chips.

[0038] To fully utilize the computing power of wafer-level chips (WLS), defective chips on the WLS can be used for task processing. However, due to the lower processing speed of defective chips, they take longer to complete the assigned tasks than normal chips, given the same number of tasks. In this embodiment, to ensure timely task processing, the defective chip can detect its task execution progress and send progress information indicating the progress to the normal chip. Upon receiving the progress information, the normal chip can determine the task execution progress of the defective chip and, based on its own and the defective chip's progress, send a request to the defective chip to transfer some of the tasks assigned to the defective chip to the normal chip. The defective chip can respond to the received request and transfer some tasks to the normal chip, thereby fully utilizing the computing power of the WLS when it is operating at full capacity and improving its task processing capabilities.

[0039] chip

[0040] Figure 3 This is a schematic diagram of a chip according to one embodiment of this application, as shown below. Figure 3As shown, chip 20 includes a task execution unit 21 and a task scheduling unit 22, which are connected via a bus. It can execute tasks assigned to the chip, such as computational tasks, read / write tasks, etc. The task scheduling unit 22 can detect the task execution progress during the execution of tasks by the task execution unit and send progress information indicating the task execution progress to other chips located on the same wafer. It can also receive request information sent by other chips, and thus, based on the request information, transfer some tasks executed by the task execution unit to task execution units in other chips. This realizes the task scheduling function of the task scheduling unit 22, which can schedule some tasks from chips with lower computational efficiency to chips with higher computational efficiency. Therefore, chips with lower computational efficiency can be enabled. Chips with lower computational efficiency are those with defects in the wafer-level chip. Compared to disabling defective chips in the wafer-level chip, this improves the utilization rate of chips on the wafer-level chip, allowing full utilization of the wafer-level chip's computing power when it is operating at full load, thereby improving the wafer-level chip's task processing capability.

[0041] This application embodiment mainly focuses on the task scheduling process performed by the task scheduling unit 22. The task scheduling process performed by the task scheduling unit will be described in detail later.

[0042] Task scheduling unit

[0043] Based on the chip 20 in the wafer-level chip 100 described above, this application embodiment provides a task scheduling unit 22, which is disposed in the chip 20. The task scheduling unit 22 will be described in detail below through several embodiments.

[0044] Figure 4 This is a schematic diagram of a task scheduling unit according to an embodiment of this application. Figure 4 As shown, the task scheduling unit 22 includes:

[0045] The progress detection subunit 221 can obtain first progress information of the first chip where the task scheduling unit 22 is located. The first progress information is used to indicate the task execution progress of the first chip. The sending subunit 222 can send the first progress information to the second chip. The first chip and the second chip are located on the same wafer, and the task execution progress of the first chip is less than that of the second chip. The transfer subunit 223 can receive a first request information sent by the second chip in response to the first progress information, and transfer at least part of the task executed by the first chip to the second chip for execution according to the first request information. The first request information is generated by the second chip based on the first progress information and the task execution progress of the second chip.

[0046] After receiving a task, the wafer-level chip 100 will distribute the task to multiple chips on the wafer-level chip 100 for processing through the controller on the wafer-level chip 100. The progress detection subunit 221 can detect the first progress information of the first chip where the task scheduling unit 22 is located to obtain the task execution progress of the first chip. The first progress information can be the percentage of task completion, the number of command executions, etc. For example, if the first chip is allocated 1,000 tasks and 200 tasks have been completed, the first progress information can be 20%, thus indicating that the task execution progress of the first chip is 20%, etc. Or, if the first chip is allocated 1,000 tasks, and these 1,000 tasks include 2,000 commands, and the first chip has executed 1,000 commands, then the 1,000 commands that have been executed are determined as the task execution progress of the first chip, etc.

[0047] The task execution progress of a chip can determine its task execution efficiency. When two chips are processing corresponding tasks, by comparing their task execution progress, the difference in computing speed between the two chips can be determined, thereby identifying the chip with the slower computing speed, i.e., the defective chip.

[0048] After obtaining the first progress information, the sending subunit 222 sends the first progress information to the second chip on the same wafer. The task execution progress of the second chip is greater than that of the first chip, that is, the first chip is a defective chip, which causes the computing speed of the first chip to be lower than that of the second chip. The task execution progress of the second chip is detected by the progress detection subunit set on the second chip. The sending subunit 222 on the first chip can send the first progress information to the second chip through the on-chip network. The specific information transmission method is not limited in this embodiment.

[0049] After receiving the first progress information sent by the sending subunit 222, the second chip sends a first request information to the first chip according to the task execution progress of the first chip and the task execution progress of the second chip indicated by the first progress information. The first request information indicates the number of tasks to be transferred. At this time, the transfer subunit 223 set on the first chip receives the first request information sent by the second chip and transfers at least part of the tasks executed by the first chip to the second chip for execution according to the number of tasks to be transferred according to the first request information.

[0050] In this embodiment, the progress detection subunit 221 can detect the task execution progress of the first chip, and the sending subunit 222 sends the first progress information that can indicate the task execution progress to the second chip and receives the first request information sent by the second chip. Thus, according to the first request information, some tasks executed by the first chip can be transferred to the second chip for execution. The computing efficiency of the first chip is lower than that of the second chip. This realizes the scheduling of some tasks of the chip with lower computing efficiency to the chip with higher computing efficiency. Since the chip with lower computing efficiency is enabled, the chip with lower computing efficiency is the chip with defects in the wafer-level chip. Compared with disabling the chip with defects in the wafer-level chip, the utilization rate of the chips on the wafer-level chip is improved, and the overall computing speed of the wafer-level chip is not reduced due to enabling the chip with defects. Therefore, the computing efficiency of the wafer-level chip is improved.

[0051] In one possible implementation, the progress detection subunit 221 can detect the number of times the operation loop in the first chip is completed and determine the number of completions as the first progress information. The operation loop includes at least one operation instruction.

[0052] The progress detection subunit 221 can obtain the task execution progress in the first chip by counting. The progress detection subunit 221 detects the number of operation loops in the first chip. An operation loop includes at least one operation instruction. For example, if an operation loop is a numerical calculation, it includes multiple addition, subtraction, multiplication, and division operations. The progress detection subunit 221 counts based on the number of times the operation loop is completed and determines the count value as the first progress information.

[0053] Correspondingly, at this time, the progress detection subunit in the second chip detects the task execution progress of the second chip in the same way. That is, the progress detection subunit in the second chip records the task execution progress of the second chip by counting. After the second chip receives the first progress information sent by the first chip, the second chip sends the first request information to the first chip according to the count indicated by the first progress information and the count of the progress detection subunit in the second chip.

[0054] The progress detection subunit 221 can detect the number of times the operation loop is completed through hardware or software. In one example, the progress detection subunit 221 can use the OpenMP language to implicitly declare a local variable named progress_counter for each thread in the chip and associate the variable with the operation loop count to detect and record the task execution progress.

[0055] In this embodiment of the application, the progress detection subunit 221 detects the number of times the operation loop in the first chip is completed and determines the number of completions as the first progress information. This enables the detection of the task execution progress of the first chip and allows the task execution progress of the first chip to be represented by a specific value. This facilitates the second chip to send the first request information based on the task execution progress of the first chip and the task execution progress of the second chip, thereby improving the efficiency of data interaction between the first chip and the second chip and thus improving the efficiency of task transfer.

[0056] In one possible implementation, the transfer subunit 223 can send first transfer information to the second chip, so that the second chip can perform the task transferred from the first chip to the second chip according to the first transfer information.

[0057] When the transfer subunit 223 of the first chip receives the first request information sent by the second chip, it transfers at least part of the task executed by the first chip to the second chip for execution through the first transfer information. The first transfer information may include at least one of the task information to be transferred and the data storage address of the task to be transferred. For example, if the task to be transferred is a computing task, the first transfer information may include the task information; if the task to be transferred is a read / write task, the first transfer information may include the task information and the data storage address of the task, so as to perform reading and writing of data.

[0058] It should be noted that after the first chip sends the first transfer information, it deletes the corresponding task to prevent the first and second chips from executing the same task. After receiving the first transfer information, the second chip parses it to obtain the task transferred out by the first chip, and then executes the task transferred out by the first chip according to the first transfer information, thereby achieving task transfer.

[0059] In this embodiment, the transfer subunit 223 transfers at least part of the tasks executed by the first chip to the second chip by sending first transfer information to the second chip. This realizes the transfer of some tasks from the chip with low computing efficiency to the chip with high computing efficiency, shortens the task completion time, improves the overall computing efficiency of the wafer-level chip 100, and improves the efficiency of task transfer by transferring tasks through transfer information without transferring task data.

[0060] In one possible implementation, the transfer subunit 223 can determine the tasks to be transferred to the second chip based on the number of tasks requested to be transferred from the first request information and the number of tasks to be executed on the first chip, and transfer the tasks to be transferred to the second chip for execution, wherein the number of tasks to be transferred is less than the number of tasks to be executed.

[0061] After receiving the first request information, the transfer subunit 223 parses the first request information to determine the number of tasks requested for transfer. Then, the transfer subunit 223 obtains the number of tasks to be executed in the first chip, determines the tasks to be transferred based on the number of tasks to be executed and the number of tasks requested for transfer, and transfers the tasks to be transferred to the second chip for execution. Since the tasks to be transferred are at least some of the tasks in the first chip, the number of tasks to be transferred is less than the number of tasks to be executed in the first chip.

[0062] The number of tasks to be transferred can be less than or equal to the number of tasks requested to be transferred by the first request information. Since the number of tasks requested to be transferred by the first request information can be greater than the number of tasks to be executed by the first chip, the determined number of tasks to be transferred can be less than the number of tasks requested to be transferred by the first request information. Also, when the difference between the number of tasks to be executed by the first chip and the number of tasks requested to be transferred is small, the number of tasks to be transferred can be less than the number of tasks requested to be transferred by the first request information.

[0063] The number of tasks to be transferred can also be greater than the number of tasks requested to be transferred in the first request information. When the number of tasks requested to be transferred in the first request information is small, and the number of tasks to be executed in the first chip is large, the number of tasks to be transferred can be greater than the number of tasks requested to be transferred in the first request information. For example, if there are 1,000 tasks to be executed, and the number of tasks requested to be transferred in the first transfer request information is 100, then according to the task execution progress of the first chip and the task execution progress of the second chip, 200 tasks can be transferred to the second chip for execution.

[0064] It should be noted that the above-mentioned task transfer process can be implemented by sending transfer information to the second chip in the aforementioned embodiments, or it can be implemented in other ways, such as by reallocating tasks through the controller. This application embodiment does not limit this.

[0065] In this embodiment, based on the number of tasks requested for transfer and the number of tasks to be executed on the first chip, the tasks to be transferred to the second chip are determined, and the tasks to be transferred are transferred to the second chip for execution. This achieves the determination of tasks to be transferred and the transfer of tasks. Since the tasks to be transferred are determined based on the number of tasks requested for transfer and the number of tasks to be executed, that is, based on the number of tasks that the second chip can process, the first chip determines the number of tasks to be transferred. Therefore, at least some of the tasks to be executed on the first chip can be transferred to the second chip for execution without affecting the second chip's original task execution, thereby shortening the task completion time and improving the computing efficiency of the wafer-level chip 100 where the first chip and the second chip are located.

[0066] In one possible implementation, the transfer subunit 223 can receive second progress information sent by the third chip, where the first chip and the third chip are located on the same wafer. The sending subunit 222 can determine the task execution progress of the third chip based on the second progress information, and when the task execution progress of the third chip and the task execution progress of the first chip meet the task transfer conditions, it sends a second request message to the third chip to request that at least part of the task executed by the third chip be transferred to the first chip for execution.

[0067] The transfer subunit 223 receives second progress information sent by a third chip located on the same wafer. The second progress information is used to indicate the task execution progress of the third chip. After receiving the second progress information, the transfer subunit 223 transmits the second progress information to the sending subunit 222. After receiving the second progress information sent by the transfer subunit 223, the sending subunit 222 parses the second progress information, determines the task execution progress of the third chip, and compares it with the task execution progress of the first chip where the sending subunit 222 is located. When the comparison result meets the task transfer condition, the sending subunit 222 sends a second request information to the third chip, thereby transferring at least part of the task executed by the third chip to the first chip for execution.

[0068] It should be noted that when the task execution progress of the third chip determined by the sending subunit 222 is lower than the task execution progress of the first chip where the sending subunit 222 is located, the second request information is not sent to the third chip. Therefore, the third chip does not receive the second request information and continues to process its pending tasks without transferring the tasks. Only when the task execution progress of the third chip determined by the sending subunit 222 is higher than the task execution progress of the first chip where the sending subunit 222 is located, and the task transfer conditions are met, will the second request information be sent to the third chip, transferring at least part of the tasks executed by the third chip to the first chip for execution.

[0069] In this embodiment, the transfer subunit 223 receives the second progress information of the third chip, thereby sending a second request message to the third chip according to the task execution progress of the third chip and the task execution progress of the first chip. This allows some tasks of the chip with lower computing efficiency to be transferred to the chip with higher computing efficiency for processing. Therefore, defective chips can be utilized without disabling them, improving the utilization rate of chips on the wafer-level chip 100, thereby improving the computing efficiency of the wafer-level chip 100 where the first chip and the third chip are located.

[0070] In one possible implementation, the transfer subunit 223 can receive second transfer information sent by the third chip in response to the second request information, and perform the task of transferring from the third chip to the first chip according to the second transfer information.

[0071] When the task execution progress of the third chip and the task execution progress of the first chip meet the task transfer conditions, the first chip sends a second request message to the third chip. After receiving the second request message, the third chip generates second transfer information in response to the second request message. The second transfer information can indicate the task to be transferred from the third chip to the first chip. At this time, the transfer subunit 223 in the first chip receives the second transfer information and processes the task transferred out by the third chip according to the second transfer information. The task execution progress of the third chip is greater than the task execution progress of the first chip.

[0072] In one example, Figure 5 The process of information exchange between chips is shown, such as Figure 5 As shown, chip 1 is assigned tasks 0 to 1000, and chip 2 is assigned tasks 1000 to 2000. Chip 1 has completed 100 tasks, and chip 2 has completed 20 tasks. Chip 1 sends progress information 1 to chip 2, indicating the number of tasks completed. After receiving progress information 1, chip 2 compares it with its own number of completed tasks. Since chip 2's number of completed tasks (20) is less than chip 1's, chip 2 does not send a request message to chip 1. Chip 2 then sends progress information 2 to chip 1, indicating its own number of completed tasks. Upon receiving progress information 2, chip 1, based on its own number of completed tasks (100) and chip 2's number of completed tasks (20), sends request information 1 to chip 2, requesting the transfer of 500 tasks. In response to request information 1, chip 2 sends transfer information 1 to chip 1, transferring tasks 1500 to 2000 to chip 1 for execution. Chip 1 can execute tasks 1500 to 2000 based on transfer information 1.

[0073] It should be understood that after chip 2 transfers tasks 1500 to 2000 to chip 1 for execution, chip 2 only needs to execute the remaining tasks 1000 to 1500, and does not need to execute tasks 1500 to 2000, in order to prevent duplicate execution of tasks.

[0074] In this embodiment, the transfer subunit 223 receives the second transfer information sent by the third chip in response to the second request information, and executes the task transferred from the third chip to the first chip according to the second transfer information. This can realize the transfer of some tasks of the chip with low computing efficiency to the chip with high computing efficiency for processing. Therefore, defective chips can be utilized without disabling them, which improves the utilization rate of chips on the wafer-level chip 100, thereby improving the computing efficiency of the wafer-level chip 100 where the first chip and the third chip are located.

[0075] In one possible implementation, the task transfer conditions include: the difference between the task execution progress of the first chip and the task execution progress of the third chip is greater than an execution progress threshold; and / or, the difference between the predicted time for the third chip to execute the remaining tasks and the predicted time for the first chip to execute the remaining tasks is greater than a time threshold.

[0076] When the task execution progress of the third chip and the task execution progress of the first chip meet the task transfer conditions, a second request message is sent to the third chip. The task transfer conditions may include the difference between the task execution progress of the first chip and the task execution progress of the third chip being greater than an execution progress threshold. This execution progress threshold is a preset threshold, such as a progress percentage difference of 20% or a task progress count difference of 20, etc. In one example, the preset execution progress threshold is 30. Figure 3 As shown, the task progress count difference between the first chip and the third chip is 80, which is greater than the preset execution progress threshold. At this time, the first chip sends a second request message to the third chip, namely request500 in the figure.

[0077] The task transfer condition may also include that the difference between the predicted time of the third chip to execute the remaining tasks and the predicted time of the first chip to execute the remaining tasks is greater than a time threshold. Since each chip is assigned different tasks, the number of tasks may also be different, and the computing efficiency of each chip is somewhat different, each chip can predict the time required to execute the remaining tasks based on its remaining tasks, completed tasks, and the time spent completing the tasks. When the difference between the predicted time of the first chip and the predicted time of the third chip is greater than a preset time threshold, the first chip sends a second request message to the third chip.

[0078] It should be understood that due to performance differences between different chips, even chips without defects will perform differently when processing the same task. For example, the first chip might take 100 seconds to process 1000 tasks, while the third chip might take 105 seconds. Alternatively, the first chip might have completed 50 tasks, while the third chip might have completed 48. In these two examples, although the third chip's task execution progress is slower than the first chip's, the difference is small enough that the tasks from the third chip will not be transferred to the first chip. Therefore, a threshold needs to be set to filter out chips with significantly different progress for task transfer.

[0079] In this embodiment, the task transfer conditions include the difference in task execution progress being greater than an execution progress threshold, and / or the difference in the predicted time for executing the remaining tasks being greater than a time threshold. This allows chips with significantly different task execution progress to be selected, enabling task transfer between chips with significantly different task progress. This avoids the situation where task transfer between chips with small progress differences consumes bandwidth and reduces computational efficiency. Furthermore, task transfer between chips with significantly different task execution progress allows the use of defective chips for computation without disabling them, improving the utilization rate of chips on the wafer-level chip 100, thereby improving the computational efficiency of the wafer-level chip 100 where the first and third chips are located.

[0080] In one possible implementation, the transmitting subunit 222 can broadcast the information to be transmitted to a target chip located on the same wafer as the first chip, and / or attach the information to be transmitted to the interaction data between the first chip and the target chip.

[0081] The transmitting subunit 222 can broadcast information to be transmitted to other chips on the same wafer. The information to be transmitted may include any information sent by the first chip in any of the above embodiments, such as first progress information, second request information, etc. Taking the first progress information as an example, the first chip broadcasts the first progress information. At this time, other chips located on the same wafer can receive the broadcast of the first progress information and determine whether to send a request information to the first chip to request the first chip to transfer the task based on the task execution progress of the first chip indicated by the first progress information and their own task execution progress.

[0082] It should be noted that when the first chip sends the information to be sent via broadcast, multiple chips located on the same wafer may receive the broadcast information. Therefore, the first chip may receive multiple request information sent by multiple chips located on the same wafer. At this time, the first chip can allocate the task to multiple chips for execution based on the multiple request information. The specific allocation method will not be described in this application.

[0083] The transmitting subunit 222 can also attach the information to be sent to the communication data with the target chip. In this case, the first chip and the target chip are connected via NoC and communicate via NoC. After the communication data with the information to be sent is sent to the target chip via NoC, the target chip can attach the request information to the communication data during the next data interaction to send the request information to the first chip.

[0084] Optionally, when attaching the information to be sent to the interaction data between the first chip and the target chip for information exchange, a timed broadcast can be set to send the information to be sent in the form of a broadcast at regular intervals.

[0085] Since data interaction is not real-time, it may take a long time for a one-way data interaction to occur. At this time, the first chip attaches the information to be sent to the interaction data and communicates with the target chip. The first chip will not receive the information returned by the target chip until the next data interaction between the target chip and the first chip. Therefore, the timeliness of information interaction is poor.

[0086] Therefore, a timed broadcast function is set up, which sends the information to be sent in the chip through broadcast at fixed intervals. At this time, the message can be replied to in time, without having to wait for the next data interaction to receive the reply message, thus improving the timeliness of information exchange between the first chip and the target chip.

[0087] In this embodiment, the first chip broadcasts the information to be sent to the target chip, thereby enabling information interaction between chips. This allows chips with lower task execution efficiency to communicate with chips with higher task execution efficiency, thus enabling task transfer between chips. Furthermore, the first chip can attach the information to be sent to the interaction data with the target chip to exchange information through data interaction. Since the data interaction is only required between the first chip and the target chip, the information interaction does not consume new bandwidth, thereby improving the task processing efficiency of the chip and thus increasing the computing efficiency of the wafer-level chip 100.

[0088] In one possible implementation, the transfer subunit 223 may receive information broadcast by a source chip located on the same wafer as the first chip, and / or parse the information sent by the source chip to the first chip from the interaction data sent by the source chip to the first chip.

[0089] The transfer subunit 223 can receive information broadcast by the source chip. This information may include any information received by the first chip in any of the above embodiments, such as second progress information, first request information, etc. It can also parse the interaction data to obtain information added by the source chip in the interaction data, thereby enabling information interaction with the source chip.

[0090] In this embodiment, the first chip receives information broadcast by the source chip, thereby enabling information exchange between chips. This allows chips with lower task execution efficiency to communicate with chips with higher task execution efficiency and perform task transfer between chips. Furthermore, the first chip can parse the interaction data to obtain the information added by the source chip to the interaction data. This enables information exchange and task transfer between defective and normal chips, allowing the defective chip to participate in the computation, thus improving the computational efficiency of the wafer-level chip 100.

[0091] In one possible implementation, the chip with low computational efficiency can be predetermined, and only the chip with low computational efficiency can send its own task execution progress. Normal chips do not send their own task execution progress. After receiving the task execution progress, only the normal chips can send request information, and the chip with low computational efficiency will not send request information, so as to transfer at least part of the task of the chip with low task execution efficiency to the chip with high computational efficiency for execution.

[0092] Since the chip compares the task execution progress it receives with its own task execution progress, it only sends a request message when the task execution progress is lower than its own and the task transfer conditions are met. Therefore, defective chips on the same wafer can be identified during chip testing, and only the defective chips can send out their own task execution progress, thereby reducing information interaction.

[0093] In one example, Figure 6 This illustrates the information exchange process between the defective chip and the normal chip, such as... Figure 6 As shown, chip 3 is assigned tasks 0 to 1000, and chip 4 is assigned tasks 1000 to 2000. Chip 3 has completed 100 tasks, and chip 4 has completed 20 tasks. Since chip 4 is pre-determined to be a defective chip, only chip 4 sends progress information 3 to chip 3. Upon receiving progress information 3, chip 3, based on its own completed tasks (100) and chip 4's completed tasks (20), sends request information 2 to chip 3, requesting the transfer of 500 tasks. In response to request information 2, chip 4 sends transfer information 2 to chip 3, transferring tasks 1500 to 2000 to chip 3 for execution. Chip 3 can then execute tasks 1500 to 2000 according to transfer information 2.

[0094] In this embodiment, by pre-determining the defective chip and only having the defective chip send out the task execution progress, the information interaction between the normal chip and the defective chip can be reduced, thereby allowing more bandwidth to be used for task execution and shortening the task execution time, thus improving the computing efficiency of the wafer-level chip 100.

[0095] Task scheduling methods

[0096] Based on the task scheduling unit 22 described above, this application provides a task scheduling method, which can be executed by the task scheduling unit 22 in any of the above embodiments.

[0097] Figure 7 This is a flowchart of a task scheduling method according to an embodiment of this application. Figure 7 As shown, the task scheduling method includes the following steps:

[0098] Step 701: Obtain the first progress information of the first chip.

[0099] The first progress information is detected by the progress detection subunit located on the first chip, and the first progress information is used to indicate the task execution progress of the first chip.

[0100] Step 702: Send the first progress information to the second chip.

[0101] The first chip and the second chip are located on the same wafer, and the task execution progress of the first chip is less than that of the second chip.

[0102] Step 703: Receive the first request information sent by the second chip in response to the first progress information.

[0103] The first request information is generated by the second chip based on the first progress information and the task execution progress of the second chip.

[0104] Step 704: Transfer at least part of the task executed by the first chip to the second chip for execution according to the first request information.

[0105] In this embodiment, the task execution progress is obtained, first progress information indicating the task execution progress is sent to the second chip, and first request information sent by the second chip is received. Based on the first request information, some tasks executed by the first chip can be transferred to the second chip for execution. This achieves the scheduling of some tasks from chips with lower computational efficiency to chips with higher computational efficiency. Since chips with lower computational efficiency are enabled (i.e., chips with defects in the wafer-level chip), compared to disabling defective chips in the wafer-level chip, the utilization rate of chips on the wafer-level chip is improved, and the overall computational speed of the wafer-level chip is not reduced due to enabling defective chips, thus improving the computational efficiency of the wafer-level chip.

[0106] Figure 8 This is a flowchart of a task scheduling method according to another embodiment of this application, such as... Figure 8 As shown, the task scheduling method includes the following steps:

[0107] Step 801: Receive the second progress information sent by the third chip.

[0108] The first chip and the third chip are located on the same wafer.

[0109] Step 802: Determine the task execution progress of the third chip based on the second progress information.

[0110] Step 803: When the task execution progress of the third chip and the task execution progress of the first chip meet the task transfer conditions, send a second request message to the third chip to request that at least part of the task executed by the third chip be transferred to the first chip for execution.

[0111] In this embodiment, the second progress information of the third chip is received. Based on the task execution progress of the third chip and the task execution progress of the first chip, a second request information is sent to the third chip. This allows some tasks of the chip with lower computing efficiency to be transferred to the chip with higher computing efficiency. Therefore, the defective chip can be used for computation without disabling it, which improves the utilization rate of the chips on the wafer-level chip and thus improves the computing efficiency of the wafer-level chips where the first chip and the third chip are located.

[0112] It should be noted that the task scheduling method in this application is a specific application of the task scheduling unit in the foregoing embodiments. For the specific task scheduling method, please refer to the description in the foregoing task scheduling unit embodiments, which will not be repeated here.

[0113] It should be noted that the user-related information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to sample data used for training the model, data used for analysis, stored data, displayed data, etc.) involved in the embodiments of this application are all information and data authorized by the user or fully authorized by all parties. Furthermore, the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and corresponding operation entry points are provided for users to choose to authorize or refuse.

[0114] It should be noted that, depending on the implementation needs, the various components / steps described in the embodiments of this application can be broken down into more components / steps, or two or more components / steps or parts of the operation of components / steps can be combined into new components / steps to achieve the purpose of the embodiments of this application.

[0115] The methods described in the embodiments of this application can be implemented in hardware, firmware, or as software or computer code that can be stored in a recording medium (such as a CD-ROM, RAM, floppy disk, hard disk, or magneto-optical disk), or as computer code downloaded over a network that is originally stored in a remote recording medium or a non-transitory machine-readable medium and will be stored in a local recording medium. Thus, the methods described herein can be processed by software stored on a recording medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware (such as an ASIC or FPGA). It is understood that the computer, processor, microprocessor controller, or programmable hardware includes storage components (e.g., RAM, ROM, flash memory, etc.) capable of storing or receiving software or computer code that, when accessed and executed by the computer, processor, or hardware, implements the methods described herein. Furthermore, when a general-purpose computer accesses code used to implement the methods shown herein, the execution of the code transforms the general-purpose computer into a dedicated computer for executing the methods shown herein.

[0116] Those skilled in the art will recognize that the units and method steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this application.

[0117] The above embodiments are only used to illustrate the embodiments of this application, and are not intended to limit the embodiments of this application. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of this application. Therefore, all equivalent technical solutions also fall within the scope of the embodiments of this application, and the patent protection scope of the embodiments of this application should be defined by the claims.

Claims

1. A task scheduling unit, comprising: A progress detection subunit is used to obtain first progress information of the first chip where the task scheduling unit is located. The first progress information is used to indicate the task execution progress of the first chip. A sending subunit is used to send the first progress information to the second chip. The first chip and the second chip are located on the same wafer. The first chip is a defective chip. The task execution progress of the first chip is less than that of the second chip. The transfer subunit is configured to receive a first request information sent by the second chip in response to the first progress information, and transfer at least part of the task executed by the first chip to the second chip for execution according to the first request information. The first request information is generated by the second chip according to the first progress information and the task execution progress of the second chip.

2. The task scheduling unit according to claim 1, wherein, The progress detection subunit is used to detect the number of times the operation loop in the first chip is completed, and to determine the number of completions as the first progress information. The operation loop includes at least one operation instruction.

3. The task scheduling unit according to claim 1, wherein, The transfer subunit is used to send first transfer information to the second chip, so that the second chip can perform a task transferred from the first chip to the second chip according to the first transfer information.

4. The task scheduling unit according to claim 1, wherein, The transfer subunit is used to determine the tasks to be transferred to the second chip based on the number of tasks requested to be transferred in the first request information and the number of tasks to be executed in the first chip, and to transfer the tasks to be transferred to the second chip for execution, wherein the number of tasks to be transferred is less than the number of tasks to be executed.

5. The task scheduling unit according to claim 1, wherein, The transfer subunit is used to receive second progress information sent by the third chip, wherein the first chip and the third chip are located on the same wafer. The sending subunit is configured to determine the task execution progress of the third chip based on the second progress information, and when the task execution progress of the third chip and the task execution progress of the first chip meet the task transfer conditions, send a second request message to the third chip to request that at least part of the task executed by the third chip be transferred to the first chip for execution.

6. The task scheduling unit according to claim 5, wherein, The transfer subunit is configured to receive second transfer information sent by the third chip in response to the second request information, and to perform a task to transfer from the third chip to the first chip according to the second transfer information.

7. The task scheduling unit according to claim 5, wherein, The task transfer conditions include: The difference between the task execution progress of the first chip and the task execution progress of the third chip is greater than the execution progress threshold. And / or, The difference between the predicted time for the third chip to execute the remaining tasks and the predicted time for the first chip to execute the remaining tasks is greater than a time threshold.

8. The task scheduling unit according to any one of claims 1-7, wherein, The transmitting subunit is used to transmit the information to be transmitted to a target chip located on the same wafer as the first chip via broadcast, and / or to attach the information to be transmitted to the interaction data between the first chip and the target chip.

9. The task scheduling unit according to any one of claims 1-7, wherein, The transfer subunit is used to receive information sent by a source chip located on the same wafer as the first chip via broadcast, and / or to parse the information sent by the source chip to the first chip from the interaction data sent by the source chip to the first chip.

10. A task scheduling method, comprising: Obtain first progress information of the first chip, wherein the first progress information is used to indicate the task execution progress of the first chip; The first progress information is sent to the second chip, wherein the first chip and the second chip are located on the same wafer, the first chip is a defective chip, and the task execution progress of the first chip is less than that of the second chip. The second chip receives a first request message sent in response to the first progress information, wherein the first request message is generated by the second chip based on the first progress information and the task execution progress of the second chip. Based on the first request information, at least part of the task performed by the first chip is transferred to the second chip for execution.

11. The method according to claim 10, further comprising: Receive second progress information sent by a third chip, wherein the first chip and the third chip are located on the same wafer; The task execution progress of the third chip is determined based on the second progress information; When the task execution progress of the third chip and the task execution progress of the first chip meet the task transfer conditions, a second request message is sent to the third chip to request that at least part of the task executed by the third chip be transferred to the first chip for execution.

12. A chip comprising a task scheduling unit according to any one of claims 1-9.

13. A wafer-level chip comprising a plurality of chips according to claim 12, wherein the plurality of chips communicate with each other via an on-chip network.

14. A computing device comprising a wafer-level chip according to claim 13.

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