Computing storage systems and methods

Abstract

The application discloses a memory structure and a corresponding computing storage system. The problem of mutual influence between a storage circuit and a required analog computing circuit in the prior art is solved. The implementation manner is that an independent computing port is added in a storage bit, so that the decoupling of the memory analog computing and the storage function is realized. The application realizes the decoupling of a subsystem in a storage, digital and analog mixed signal circuit system, can reduce the design difficulty, improve the reliability, usability and efficiency of the system, and can be applied to a large-scale analog computing system of integration of storage and computing.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuits, and more specifically, relates to the architecture and operation of integrated circuit computing chips. Background Technology

[0002] With the development of the Internet of Things (IoT) and cloud computing, the complexity of computing tasks is increasing daily, putting greater pressure on computing chips. The main performance indicators of computing chips can be divided into power consumption and computing power. Whether in energy-constrained scenarios such as IoT or energy-intensive scenarios such as cloud computing, power consumption is crucial. Therefore, how to further reduce chip power consumption while providing a given computing power is an important research direction for computing chips.

[0003] The power consumption of computing chips mainly comes from two parts of operations: data read / write and data computation. For specific computations, such as inference and training computations involved in deep neural networks, a large number of data read / write operations occur. The target memory for data read / write can be divided into on-chip memory and off-chip memory. Since on-chip memory widely uses static random access memory (SRAM), its density is relatively low, and therefore its storage capacity is often small. When encountering a large number of data read / write operations, it is necessary to access off-chip memory. Examining data read / write operations, the charging and discharging of parasitic capacitances around interconnects is the main source of energy consumption. Off-chip memory accesses data through interconnects and pins with larger spacing, resulting in much higher energy consumption than on-chip memory. To address this phenomenon, deploying data in on-chip memory as much as possible and further reducing data access to on-chip memory are important strategies for optimizing the energy efficiency of computing chips.

[0004] In-memory computing architecture is one specific implementation of this. This architecture constructs high-density computing units based on memristors, allowing computational data to be partially embedded within these units, thus reducing data access operations. Simultaneously, due to its analog computing approach, it exhibits robustness to stored data, enabling larger-scale on-chip storage. A typical computation method involves inputting a voltage vector V to one side of a memristor array with conductance matrix G via a digital-to-analog converter (DAC), and measuring the output current vector I on the orthogonal other side to perform a matrix-vector multiplication calculation of I = GV. In the context of neural network inference, G corresponds to the network weights and is updated less frequently, while V corresponds to the feature map of the data and is updated more frequently.

[0005] In the current development of in-memory computing chips, the memory circuitry needs to be jointly designed with the mixed-signal circuitry required for computation, which significantly increases the difficulty and uncertainty of the design process. Due to potential mismatches between the memory and computation circuits, the original memory circuitry may need to be redesigned, thus increasing design costs. Furthermore, the joint design of the two also compresses the design space, making independent optimization of each subsystem impossible. Summary of the Invention

[0006] The purpose of this invention is to solve the above-mentioned problems and to propose a computing storage system and method.

[0007] The objective of this invention is achieved through the following technical solution:

[0008] Firstly, a computing and storage system is provided.

[0009] The computing and storage system includes a memory array, peripheral storage circuitry, and peripheral computing circuitry.

[0010] The memory array contains two independent sets of port combinations, denoted as port combination M and port combination C;

[0011] The required read / write input / output for storage is performed through port combination M, which is completed by the peripheral storage circuit.

[0012] The inputs and outputs required for the calculation are performed through port combination C and are completed by the peripheral computing circuit.

[0013] Furthermore,

[0014] The port combination M includes a bit selection port and two data input / output ports;

[0015] The interconnects corresponding to the two data input / output ports are parallel to each other.

[0016] Furthermore,

[0017] The port combination C includes a bit selection port and two data input / output ports;

[0018] The interconnects corresponding to the two data input / output ports are perpendicular to each other.

[0019] Furthermore,

[0020] The port combination M and port combination C share a bit selection port.

[0021] Furthermore,

[0022] The storage bit consists of two transistors A and B and a resistive storage cell D;

[0023] The source of transistor A, the source of transistor B, and one end of the resistive memory cell D are short-circuited.

[0024] The port combination M consists of the ports corresponding to the drain and gate of transistor A and the unshort-circuited terminal of transistor D.

[0025] The port combination C consists of the ports corresponding to the drain and gate of transistor B and the unshort-circuited terminal of D.

[0026] Furthermore,

[0027] The resistive storage unit is one or more of magnetoresistive memory, resistive variable memory, phase change memory, and ferroelectric memory.

[0028] Furthermore,

[0029] The memory port combination structure is compatible with different memory technologies.

[0030] Furthermore,

[0031] The memory includes one or more of the following: magnetoresistive memory, resistive random access memory, phase change memory, ferroelectric memory, static random access memory, dynamic random access memory, floating gate memory, and charge trapping memory.

[0032] In a second aspect, a computing method for a computing storage system as described in the first aspect is provided, comprising:

[0033] Step 1: Select port combination C;

[0034] Step 2: Set the output port potential in the port combination C to be the same as the zero potential of the input port in the port combination C;

[0035] Step 3: Apply an excitation signal to the input port of the port combination C;

[0036] Step four: Sample the signal at the output port of the port combination C;

[0037] Step 5: Map the signal sample values ​​to the calculated values ​​according to the correspondence between the calculated values ​​and the signal sample values;

[0038] The order of operations is as follows: Step 1 is performed first, Step 3 is performed before Step 4, Step 2 is performed before Step 4, and Step 4 is performed before Step 5.

[0039] Furthermore,

[0040] The excitation signal applied to the input port in the port combination C is a current signal;

[0041] The signal sampling performed at the output port in the port combination C is current sampling.

[0042] Furthermore,

[0043] The sampling signal is a differential signal of two complementary memory bits.

[0044] The beneficial effects of this invention are: it enables the decoupling of the ports corresponding to storage operations and the ports corresponding to computation operations during the computation process, thereby allowing the peripheral storage circuits and peripheral computation circuits to be designed independently. In this form, the original memory circuits can be reused to the maximum extent, and the storage and computation subsystems can be optimized independently during the design process.

[0045] Those skilled in the art will recognize the additional features and advantages when reading the following detailed description and looking at the accompanying drawings. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0047] Figure 1 This demonstrates a typical in-memory computing implementation method;

[0048] Figure 2 This shows a 2T1R resistive memory bit and its ports and connections;

[0049] Figure 3 A 2x4 analog computing storage system with differential output is shown;

[0050] Figure 4 A complementary bit combination for a resistive memory based on 2T1R is shown.

[0051] Figure 5 A complementary bit combination based on static random access memory is shown;

[0052] Figure 6 A complementary bit combination based on a charge memory is shown;

[0053] Figure 7 A complementary bit combination based on dynamic random access memory is shown;

[0054] Figure 8 A storage bit for a shared bit selection port is shown;

[0055] Figure 9The storage bits of another shared bit selection port are shown. Detailed Implementation

[0056] In the following detailed description, reference is made to the accompanying drawings, which form part of this invention, wherein specific embodiments in which the invention may be practiced are illustrated by way of illustration. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the invention. For example, features shown or described for one embodiment may be used or combined with other embodiments to produce yet another embodiment. It is intended that the invention include these modifications and variations. Embodiments are described using specific language (which should not be construed as limiting the scope of the appended claims). The drawings are not drawn to scale and are for illustrative purposes only.

[0057] The technical problem that this invention aims to solve is: how to overcome the problem of high coupling between storage circuits and computing circuits in the design of in-memory computing chips.

[0058] refer to Figure 1 As shown, the current mainstream in-memory calculation method is to input the voltage vector V through a voltage-to-analog converter (DAC) on one side of the memristor array with a conductance value of matrix G, and then measure the output current vector I on the other orthogonal side to achieve matrix-vector multiplication calculation of I = GV.

[0059] In the development of in-memory computing chips, existing mature memory technologies are typically adopted for feasibility reasons. Targeted modifications are then made to adapt them to the needs of analog computing. Simultaneously, to reduce development costs and technical risks, existing, proven memory circuits need to be reused as much as possible. However, in this process, since both memory and computing circuits require complete input / output ports, port conflicts and other coupling issues arise. This problem reduces the reusability of memory circuits.

[0060] To address this problem, this invention creatively proposes a bit structure that separates storage and computation ports, enabling maximum reuse of existing storage circuitry. Figure 2 For example, the original memory structure is a single-transistor and single-resistor memory (1T-1R), corresponding to interconnects 212 and 213, transistor 201, and resistive memory 203 in the diagram. In this original structure, for considerations such as the centralization of data lines in digital circuits, the interconnects 212 and 213 corresponding to the input and output are traditionally arranged in parallel so that the data input and output and their corresponding read / write analog circuits can be in the same location. However, this structure and Figure 1The input and output lines required for the calculations shown are arranged vertically to the left. To overcome this problem and reduce the impact on the original storage circuit, this invention adopts a 2T1R structure, that is, adding interconnects 221, 222 and transistor 202, so that the computing circuit is connected to an independent port combination. Specifically, interconnects 211, 212, and 213 form port combination M. During storage operations, transistor 202 is turned off by setting 221 to 0, thereby achieving isolation from 221 and 222. Interconnects 221, 222, and 213 form port combination C. During computing operations, transistor 201 is turned off by setting 211 to 0, thereby achieving isolation from 211 and 212. By using this scheme, the original storage ports are retained, thereby realizing the required computing functions in the in-memory computing circuit with minimal modification to the traditional storage circuit.

[0061] The following description further provides some embodiments of a computing storage system that conforms to the requirements of this application.

[0062] refer to Figure 3 As shown, in this embodiment, a computational storage system with an input width of 2, a storage output width of 4, and a computation output width of 2 is provided. The system includes a memory array 320, peripheral storage circuitry, and peripheral computation circuitry. The input current digital-to-analog converters 301 and 302, and the output current analog-to-digital converters 331 and 332 belong to the peripheral computation circuitry. The read / write circuits 341, 342, 343, and 344 belong to the peripheral storage current. The system also includes control circuitry, such as storage-computation control circuits 303 and 304, and a storage-computation switching circuit 305. The port combination M consists of bit selection lines 355 and 356, and data input / output ports 361, 362, 363, 364, 365, 366, 367, and 368. In storage mode, when operating on memory bits 311, the following operations can be performed step-by-step:

[0063] Step 1: Select port 355 in port combination M and disable port 356;

[0064] Step 2: By using the storage and computing switching circuit 305, connect 361 and 362 to the read and write circuit 341, and apply an excitation signal to read or write data.

[0065] During the calculation, two complementary columns are used for differential sampling. Taking 311 and 312 as an example, they form a complementary storage unit. Port combination C consists of bit gate lines 351 and 353, and input / output ports 352 and 354. In calculation mode, the following operations can be performed step-by-step:

[0066] Step 1: Select ports 351 and 353 in port combination C;

[0067] Step 2: Using the storage calculation switching circuit 305, connect 362 and 364 to the current analog-to-digital converter 331, and connect 366 and 368 to the current analog-to-digital converter 332.

[0068] Step 3: Set the potential of 352 to be the same as the zero potential of the input ports of 362, 364, 366, and 368;

[0069] Step four: Apply excitation signals to the current digital-to-analog converters 301 and 302;

[0070] Step 5: Sampling of the signal is performed in the current analog-to-digital converters 331 and 332;

[0071] Step six: Map the signal sample values ​​to the calculated values ​​according to the correspondence between the calculated values ​​and the signal sample values.

[0072] In at least one embodiment, the memory may be based on single-transistor-single-resistance (1T-1R) memory technology. Magnetoresistive memories, phase-change memories, and resistive switching memories all fall into this category. Figure 4 It shows Figure 2 The complementary form of the single storage bit.

[0073] In at least one embodiment, the memory may be a static random access memory (SRAM). For example... Figure 5 As shown, static random access memory (SRAM) uses latches as its information storage medium, resulting in complementary ends to its data. Therefore, within a group, the same storage medium 511 can be used, connecting its complementary ends to memory bits. Taking the left-hand memory bit as an example, interconnects 511, 512, and 523 form port combination M. During storage operations, isolation from 521 and 522 is achieved by setting 521 to 0. Interconnects 521, 522, and 523 form port combination C. During computation operations, isolation from 511 and 512 is achieved by setting 511 to 0.

[0074] In at least one embodiment, the memory can be a ferroelectric memory, a floating-gate memory, or a charge-trapping memory. For example... Figure 6As shown, storage bits 601 and 602 form a pair of complementary bits. Within 601, interconnects 611, 612, 613, and 614 constitute port combination M, which achieves isolation from 621 and 622 by setting 621 to 0 during storage operations; interconnects 621, 622, 613, and 614 constitute port combination C, which achieves isolation from 611 and 612 by setting 611 to 0 during computation operations. Optionally, port combination C may include 614. Specifically, by placing the storage medium, such as 631, in a normally open state using methods such as overerase, port combination C may contain only 621, 622, and 613.

[0075] In at least one embodiment, the memory may be a dynamic random access memory (DRAM). For example... Figure 7 As shown, storage bits 701 and 702 form a complementary pair of bits. Within 701, interconnects 711, 712, and 713 constitute port combination M, achieving isolation from 721 and 722 by setting 721 to 0 during storage operations; interconnects 721, 722, and 713 constitute port combination C, achieving isolation from 711 and 712 by setting 711 to 0 during computation operations. Dynamic random access memory uses capacitors as the information storage medium. In this embodiment, the potential of the capacitors is used to control the conduction of the transistors. For example, capacitor 731 is charged to a high potential while capacitor 732 is at a low potential, or vice versa, capacitor 732 is charged to a high potential while capacitor 731 is at a low potential. This allows encoding two conduction states.

[0076] In at least one embodiment, the port combination M and the port combination C share a bit selection port. For example... Figure 8 As shown, since storage mode and computation mode are not triggered simultaneously in actual operation, they can be complementaryly selected through the same signal line. Specifically, NMOS can be used for storage operation selection and PMOS for computation operation selection, or PMOS for storage operation selection and NMOS for computation operation selection. In computation mode, for memory cells where a certain storage bit requires neither storage nor computation operation, the corresponding signal line (SIG) 813 can be turned off. In storage mode, for memory cells where a certain storage bit requires neither storage nor computation operation, the corresponding source line (SL) 811 can be turned off. Furthermore, for column selection, bit line (BL) 812 can be turned off.

[0077] In at least one embodiment, the port combination M and the port combination C share a bit selection port. For example... Figure 9As shown, since storage mode and compute mode are not triggered simultaneously in actual operation, they can be selected by multiplexing 921 on the same signal line. NMOS or PMOS can be used for selection. In compute mode, unused source line (SL) 921 is turned off or left floating. In storage mode, unused signal line (SIG) 923 is turned off or left floating. Furthermore, bit line (BL) 922 can be turned off for column selection.

[0078] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on its differences from other embodiments. In particular, the apparatus embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0079] The above description is merely a preferred embodiment of the present invention. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make many possible variations and modifications to the technical solutions of the present invention using the methods and techniques disclosed above, or modify them into equivalent embodiments with equivalent changes, without departing from the scope of the technical solutions of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall still fall within the protection scope of the technical solutions of the present invention.

Claims

1. A computing storage system, characterized in that, The computing and storage system includes a memory array, peripheral storage circuitry, and peripheral computing circuitry. The memory array contains two independent sets of port combinations, denoted as port combination M and port combination C; The required read / write input / output for storage is performed through port combination M, which is completed by the peripheral storage circuit. The inputs and outputs required for the calculation are performed through port combination C and are completed by the peripheral computing circuit. The storage bit consists of two transistors A and B and a resistive storage cell D; wherein the source of transistor A, the source of transistor B and one end of the resistive storage cell D are shorted; the port combination M consists of the drain and gate of transistor A and the port corresponding to the unshort-circuited end of D; the port combination C consists of the drain and gate of transistor B and the port corresponding to the unshort-circuited end of D. The port combination M includes a bit selection port and two data input / output ports, with the interconnects corresponding to the two data input / output ports being parallel to each other; the port combination C includes a bit selection port and two data input / output ports, with the interconnects corresponding to the two data input / output ports being perpendicular to each other.

2. The computing storage system according to claim 1, characterized in that, The port combination M and port combination C share a bit selection port.

3. The computing storage system according to claim 1, characterized in that, The resistive storage unit is one or more of magnetoresistive memory, resistive variable memory, phase change memory, and ferroelectric memory.

4. The computing storage system according to claim 1, characterized in that, The memory port combination structure is compatible with different memory technologies.

5. The computing storage system according to claim 1, characterized in that, The memory includes one or more of the following: magnetoresistive memory, resistive random access memory, phase change memory, ferroelectric memory, static random access memory, dynamic random access memory, floating gate memory, and charge trapping memory.

6. A computation method for a computing storage system according to any one of claims 1-5, characterized in that, include: Step 1: Select port combination C; Step 2: Set the output port potential in the port combination C to be the same as the zero potential of the input port in the port combination C; Step 3: Apply an excitation signal to the input port of the port combination C; Step four: Sample the signal at the output port of the port combination C; Step 5: Map the signal sample values ​​to the calculated values ​​according to the correspondence between the calculated values ​​and the signal sample values; The order of operations is as follows: Step 1 is performed first, Step 3 is performed before Step 4, Step 2 is performed before Step 4, and Step 4 is performed before Step 5.

7. The calculation method according to claim 6, characterized in that, The excitation signal applied to the input port in the port combination C is a current signal; the signal sampling performed at the output port in the port combination C is current sampling.

8. The calculation method according to claim 6, characterized in that, The sampling signal is a differential signal of two complementary memory bits.

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