FPGA verification methods, apparatus, equipment, and media for ADC chips

Abstract

This invention relates to the field of verification testing, and more particularly to an FPGA verification method, apparatus, device, and medium for ADC chips. The method includes: constructing a central processing unit (CPU), an ADC controller, an ADC verification module, an interface monitoring module, and memory within an FPGA; acquiring sampling data from the ADC chip using the ADC verification module; acquiring sampling data from the ADC verification module using the ADC controller; sampling interface timing data between the ADC controller and the ADC verification module using the interface monitoring module; acquiring sampling data from the ADC controller using the CPU and writing it to memory to generate a first file, and acquiring interface timing data and writing it to memory to generate a second file; running analysis software on a host computer and using the analysis software to acquire the first and second files from memory and perform analysis to determine whether the ADC controller sampling is correct. This invention improves FPGA verification efficiency.

Description

Technical Field

[0001] This invention relates to the field of verification testing, and more particularly to an FPGA verification method, apparatus, device, and medium for ADC chips. Background Technology

[0002] The analog-to-digital converter (ADC) in the Baseboard Management Controller (BMC) is used by the BMC to acquire voltage signals from the server motherboard. This enables real-time monitoring of critical power supplies and assists the server management system in ensuring server security.

[0003] During the FPGA verification phase of chip design, because the ADC intellectual property core (IP) is an externally purchased analog hard core, it is impossible to perform FPGA verification of the complete ADC module; only the peripheral digital control program can be verified. During verification, it is necessary to check whether the verified program is working correctly. This is done by capturing internal signals and observing whether the signal waveforms conform to the design specifications. Additionally, the software is used to check whether the sampled data is correct. When long-term testing occurs, if errors occur, it is necessary to reproduce the errors and find the cause of the problem, which requires a significant amount of time to locate the issue. Summary of the Invention

[0004] In view of this, it is necessary to provide an FPGA verification method, apparatus, device and medium for ADC chips to address the above technical problems.

[0005] According to a first aspect of the present invention, an FPGA verification method for an ADC chip is provided, the method comprising:

[0006] The central processing unit, ADC controller, ADC verification module, interface monitoring module, and memory are built in the FPGA;

[0007] The ADC verification module is used to acquire sampling data from the ADC chip;

[0008] The ADC controller is used to acquire sampling data from the ADC verification module;

[0009] The interface monitoring module is used to sample the interface timing data between the ADC controller and the ADC verification module.

[0010] The central processing unit acquires the sampling data from the ADC controller and writes it into memory to generate a first file, and acquires the interface timing data from the interface monitoring module and writes it into memory to generate a second file;

[0011] The analysis software is run on the host computer, and the analysis software is used to retrieve the first file and the second file from the memory and perform analysis to determine whether the sampling of the ADC controller is correct.

[0012] In some embodiments, the method further includes:

[0013] The data generated internally by the ADC verification module through a software algorithm is used as the sampling data.

[0014] In some embodiments, the step of using the analysis software to retrieve a first file and a second file from the memory and performing analysis to determine whether the ADC controller sampling is correct includes:

[0015] The interface timing data in the second file is compared with the ADC interface specification to determine whether the interface access between the ADC verification module and the ADC controller is correct.

[0016] If the interface access between the ADC verification module and the ADC controller is correct, the sampled data is extracted from the interface timing data in the second file, and the extracted sampled data is compared with the sampled data in the first file.

[0017] If the extracted sampled data is the same as the sampled data in the first file, it is confirmed that the sampling from the ADC controller is correct.

[0018] In some embodiments, the step of using the analysis software to retrieve the first file and the second file from the memory and performing analysis to determine whether the ADC controller sampling is correct further includes:

[0019] If the sampled data is generated internally by the ADC verification module using a software algorithm, then the software algorithm is ported to the analysis software.

[0020] The analysis software uses the software algorithm to generate data and determines whether the generated data is the same as the sampled data in the first file.

[0021] If the generated data is the same as the sampled data in the first file, it is confirmed that the sampling from the ADC controller is correct.

[0022] In some embodiments, comparing the interface timing data in the second file with the ADC interface specification to determine whether the interface access between the ADC verification module and the ADC controller is correct includes:

[0023] The ADC digital interface timing diagram describing the operation of the ADC controller can be recovered based on the interface timing data in the second file.

[0024] The relative time difference between all digital interface signals is calculated based on the ADC digital interface timing diagram to obtain the signal timing in actual operation.

[0025] Compare the signal timing in the actual work with the requirements in the ADC interface specification;

[0026] If the signal timing in actual operation conforms to the requirements of the ADC interface specification, then the interface access between the ADC verification module and the ADC controller is confirmed to be correct.

[0027] If the signal timing in actual operation violates the requirements of the ADC interface specification, it is confirmed that the interface access between the ADC verification module and the ADC controller is incorrect, and a timing diagram of the violation is drawn and output.

[0028] In some embodiments, the ADC chip is an analog-to-digital converter in a substrate management controller.

[0029] In some embodiments, the analog-to-digital converter is used to acquire voltage signals on the server motherboard.

[0030] According to a second aspect of the present invention, an FPGA verification apparatus for an ADC chip is provided, the apparatus comprising:

[0031] The building unit is configured to build a central processing unit, ADC controller, ADC verification module, interface monitoring module and memory in the FPGA;

[0032] The first acquisition unit is configured to acquire sampling data from the ADC chip using the ADC verification module.

[0033] The second acquisition unit is configured to acquire sampled data from the ADC verification module using the ADC controller.

[0034] A sampling unit is configured to use the interface monitoring module to sample the interface timing data between the ADC controller and the ADC verification module.

[0035] The writing unit is configured to use the central processing unit to obtain the sampling data from the ADC controller and write it into memory to generate a first file, and to obtain the interface timing data from the interface monitoring module and write it into memory to generate a second file;

[0036] The analysis unit is configured to run analysis software in a host computer, and use the analysis software to retrieve a first file and a second file from the memory and perform analysis to determine whether the sampling by the ADC controller is correct.

[0037] According to a third aspect of the present invention, a computer device is also provided, the computer device comprising:

[0038] At least one processor; and

[0039] The memory stores a computer program that can run on the processor, which executes the aforementioned FPGA verification method for the ADC chip when executing the program.

[0040] According to a fourth aspect of the present invention, a computer-readable storage medium is also provided, which stores a computer program that, when executed by a processor, performs the aforementioned FPGA verification method for an ADC chip.

[0041] The above-mentioned FPGA verification method for ADC chips continuously samples internal signals and saves them as timing files by adding a monitoring module inside the FPGA. The timing files are then analyzed by dedicated software to help designers determine whether the ADC controller is working properly. The method can also quickly locate the location and status of problems, helping designers troubleshoot issues and improve the efficiency of FPGA verification.

[0042] In addition, the present invention also provides an FPGA verification device for ADC chips, a computer device, and a computer-readable storage medium, which can achieve the above-mentioned technical effects, and will not be described in detail here. Attached Figure Description

[0043] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.

[0044] Figure 1 A flowchart illustrating an FPGA verification method for an ADC chip, as provided in one embodiment of the present invention;

[0045] Figure 2 This is a schematic diagram of the BMC system composition structure provided in one embodiment of the present invention;

[0046] Figure 3 This is a schematic diagram of the FPGA verification system composition structure provided in one embodiment of the present invention;

[0047] Figure 4 This is a timing diagram of an ADC digital interface provided in one embodiment of the present invention;

[0048] Figure 5 This is a timing description of an ADC digital interface provided in one embodiment of the present invention;

[0049] Figure 6 A schematic diagram of an FPGA verification device for an ADC chip is provided for another embodiment of the present invention;

[0050] Figure 7 This is an internal structural diagram of a computer device according to another embodiment of the present invention. Detailed Implementation

[0051] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to specific examples and the accompanying drawings.

[0052] It should be noted that all uses of "first" and "second" in the embodiments of the present invention are for the purpose of distinguishing two entities or parameters with the same name but different names. It is clear that "first" and "second" are only for the convenience of expression and should not be construed as limiting the embodiments of the present invention. Subsequent embodiments will not explain this in detail.

[0053] In one embodiment, please refer to Figure 1 As shown, the present invention provides an FPGA verification method 100 for ADC chips. Specifically, the method includes the following steps:

[0054] Step 101: Build a central processing unit, ADC controller, ADC verification module, interface monitoring module and memory in the FPGA;

[0055] Step 102: Use the ADC verification module to obtain sampling data from the ADC chip;

[0056] Step 103: Obtain sampling data from the ADC verification module using the ADC controller;

[0057] Step 104: Use the interface monitoring module to sample the interface timing data between the ADC controller and the ADC verification module;

[0058] Step 105: The central processing unit obtains the sampling data from the ADC controller and writes it into memory to generate a first file, and obtains the interface timing data from the interface monitoring module and writes it into memory to generate a second file;

[0059] Step 106: Run the analysis software in the host computer, and use the analysis software to obtain the first file and the second file from the memory and perform analysis to determine whether the sampling of the ADC controller is correct.

[0060] The above-mentioned FPGA verification method for ADC chips continuously samples internal signals and saves them as timing files by adding a monitoring module inside the FPGA. The timing files are then analyzed by dedicated software to help designers determine whether the ADC controller is working properly. The method can also quickly locate the location and status of problems, helping designers troubleshoot issues and improve the efficiency of FPGA verification.

[0061] In some embodiments, the method further includes:

[0062] The data generated internally by the ADC verification module through a software algorithm is used as the sampling data.

[0063] In some embodiments, step 106, which involves using the analysis software to retrieve the first file and the second file from the memory and analyzing them to determine whether the ADC controller sampling is correct, includes:

[0064] The interface timing data in the second file is compared with the ADC interface specification to determine whether the interface access between the ADC verification module and the ADC controller is correct.

[0065] If the interface access between the ADC verification module and the ADC controller is correct, the sampled data is extracted from the interface timing data in the second file, and the extracted sampled data is compared with the sampled data in the first file.

[0066] If the extracted sampled data is the same as the sampled data in the first file, it is confirmed that the sampling from the ADC controller is correct.

[0067] In some embodiments, the preceding step 106, which involves using the analysis software to retrieve a first file and a second file from the memory and performing analysis to determine whether the ADC controller sampling is correct, further includes:

[0068] If the sampled data is generated internally by the ADC verification module using a software algorithm, then the software algorithm is ported to the analysis software.

[0069] The analysis software uses the software algorithm to generate data and determines whether the generated data is the same as the sampled data in the first file.

[0070] If the generated data is the same as the sampled data in the first file, it is confirmed that the sampling from the ADC controller is correct.

[0071] In some embodiments, the step of comparing the interface timing data in the second file with the ADC interface specification to determine whether the interface access between the ADC verification module and the ADC controller is correct includes:

[0072] The ADC digital interface timing diagram describing the operation of the ADC controller can be recovered based on the interface timing data in the second file.

[0073] The relative time difference between all digital interface signals is calculated based on the ADC digital interface timing diagram to obtain the signal timing in actual operation.

[0074] Compare the signal timing in the actual work with the requirements in the ADC interface specification;

[0075] If the signal timing in actual operation conforms to the requirements of the ADC interface specification, then the interface access between the ADC verification module and the ADC controller is confirmed to be correct.

[0076] If the signal timing in actual operation violates the requirements of the ADC interface specification, it is confirmed that the interface access between the ADC verification module and the ADC controller is incorrect, and a timing diagram of the violation is drawn and output.

[0077] In some embodiments, the ADC chip is an analog-to-digital converter in a substrate management controller.

[0078] In some embodiments, the analog-to-digital converter is used to acquire voltage signals on the server motherboard.

[0079] In another embodiment, to facilitate understanding of the present invention, this embodiment takes the verification of a commercial ADC chip in an existing BMC chip as an example. Addressing the difficulty in locating problems during FPGA verification of commercial ADC chips in BMC chips, this invention proposes an FPGA verification method for ADC chips. The method's implementation principle is as follows: An internal monitoring module continuously samples internal signals and saves them as timing files. Dedicated software analyzes the timing files to help designers determine whether the commercial ADC chip is working properly and quickly locate the position and state of problems, thus assisting designers in troubleshooting and improving the efficiency of FPGA verification. The verification implementation process of a commercial ADC chip in a BMC chip will be described in detail below:

[0080] Please combine Figure 2 As shown, a BMC chip system comprises at least a CPU, memory, network interface, ADC controller, and a commercial ADC chip; please refer to... Figure 3As shown, the FPGA verification system comprises at least a CPU, memory, network interface, ADC controller, ADC verification module, interface monitoring module, and a commercial ADC chip. The ADC controller is the module being verified, while the others are auxiliary verification modules. The ADC verification module simulates the data interface of the ADC hard-core IP. The ADC verification module uses data from two sources: one is actual sampled data from an external ADC chip, in which case the ADC verification module needs to control the operation of the external ADC chip; the other is simulated data generated internally by the ADC verification module, which can generate different types of data according to configuration, such as single-level, sine wave, sawtooth wave, pseudo-random number, etc. The interface monitoring module samples the interaction signals between the ADC controller and the ADC verification module, continuously records all signal changes during operation, and sends the sampling results to the CPU to be saved to a file.

[0081] The verification of the ADC controller requires the cooperation of both hardware and software. The specific process is as follows:

[0082] Step one: The system software configures the ADC controller's operating parameters according to user requirements, such as sampling channels and sampling frequency. It also configures the ADC verification module's operating parameters, such as data source selection, data type, and operating frequency. Finally, it configures the interface monitoring module's operating parameters, such as sampling frequency and sampling length.

[0083] Step two: The system software sends a start command, and each module begins to work.

[0084] Step 3: The system software accesses the ADC control module via the bus, acquires the sampled data, and writes the data to a file.

[0085] Step four: The interface monitoring module sends the sampled interface timing data to the CPU. After receiving the data, the system software writes the content into the interface timing file.

[0086] Step 5: After working for a period of time, the system software sends a stop command, and each module stops working.

[0087] Step Six: Run the analysis software on the host computer and use it to analyze the saved ADC sampling data and ADC interface timing data. By comparing the ADC sampling data sections in the two files, verify whether the sampling results are correct. By comparing the ADC interface timing and the ADC interface specification, determine whether the interface access is correct. When a problem is found, indicate the location of the problem and display the timing waveform.

[0088] It should be noted that when the ADC verification module is configured to generate simulated data internally, since all data is generated by the program, the data content at any given time can be clearly known. When analyzing whether the sampling results are correct, not only can the ADC sampling data of two files be compared, but also the data sequence generated by the program can be compared to achieve a more rigorous verification.

[0089] The data analysis in step six can be implemented as follows:

[0090] Accessing the ADC digital interface requires meeting timing requirements; otherwise, it will not function correctly, and the obtained data will be unusable. For example... Figure 4 The figure shows a timing diagram of the digital interface of an ADC. Figure 5 This section describes the timing of the ADC interface.

[0091] The files saved as described in the system workflow above are ADC sampling data and ADC interface timing data. The ADC sampling data originates from the ADC controller module, and these values ​​represent the normal sampling data used by the ADC. The ADC interface timing data originates from the interface monitoring module. The interface monitoring module uses a high-speed clock to sample the digital interface signals. When the system starts operating, the internal timer of the interface monitoring module begins, sampling the ADC's digital interface signals. When the ADC's digital interface signals change, the time and signal value are recorded. The sampling results are continuously sent to the CPU for storage.

[0092] The analysis software compares the ADC interface timing with the ADC interface specification to determine if the interface access is correct. During this process, the analysis software can reconstruct an ADC digital interface timing diagram for the ADC controller's operation based on the contents of the ADC interface timing data file. It can also calculate the relative time differences between all digital interface signals, i.e., the actual time relationships during system operation, corresponding to all time relationship data in Table 1. The analysis software compares the time relationships between signals during operation with the requirements in the ADC interface specification to determine if the signal timing in actual operation meets the specification requirements, thereby determining if the ADC controller is operating correctly. When errors occur, the software can identify the errors and draw the timing diagram at the time of the error.

[0093] The analysis software analyzes the saved ADC sampling data and ADC interface timing data, verifying the correctness of the sampling results by comparing the ADC sampling data portions of the two files. This process requires extracting the ADC sampling data from the ADC interface timing data and comparing it with the separately saved ADC sampling data (from the ADC controller). This verifies whether any errors occurred during the transmission of the ADC sampling data.

[0094] When the ADC verification module is configured to internally generate simulated data, the data content at any given moment is clearly known because it is all program-generated. When analyzing the correctness of the sampling results, not only can the ADC sampling data from two files be compared, but also the data sequences generated by the program can be compared, enabling more rigorous verification. During this process, the algorithm for generating simulated data internally within the ADC verification module can be ported to the analysis software. For the data acquired by the ADC controller at each moment in the system, the corresponding values ​​can be calculated. Therefore, the ADC sampling data and the data generated by the software algorithm can be compared to help verify whether the ADC data in the data source, ADC sampling data, and ADC interface timing data are the same, thus determining whether the system is working correctly.

[0095] The FPGA verification method for ADC chips in this embodiment has the following beneficial technical effects: the ADC verification module and the interface monitoring module work together to record the working status of the ADC controller, and use software to automatically analyze the sampled data and determine whether the module is operating normally, thereby improving the efficiency of the substrate management controller ADC chip in FPGA verification.

[0096] In some embodiments, please refer to Figure 6 As shown, the present invention also provides an FPGA verification device 200 for ADC chips, the device comprising:

[0097] Unit 201 is configured to build a central processing unit, ADC controller, ADC verification module, interface monitoring module and memory in the FPGA;

[0098] The first acquisition unit 202 is configured to acquire sampling data from the ADC chip using the ADC verification module.

[0099] The second acquisition unit 203 is configured to acquire sampling data from the ADC verification module using the ADC controller;

[0100] Sampling unit 204 is configured to use the interface monitoring module to sample the interface timing data between the ADC controller and the ADC verification module;

[0101] The writing unit 205 is configured to use the central processing unit to obtain the sampling data from the ADC controller and write it into memory to generate a first file, and to obtain the interface timing data from the interface monitoring module and write it into memory to generate a second file;

[0102] Analysis unit 206 is configured to run analysis software in a host computer, and use the analysis software to obtain a first file and a second file from the memory and perform analysis to determine whether the sampling of the ADC controller is correct.

[0103] The aforementioned FPGA verification device for ADC chips continuously samples internal signals and saves them as timing files by adding a monitoring module inside the FPGA. The timing files are then analyzed using dedicated software to help designers determine whether the ADC controller is working properly. The device can also quickly locate the location and status of problems, helping designers troubleshoot issues and improving the efficiency of FPGA verification work.

[0104] It should be noted that the specific limitations of the FPGA verification device for ADC chips can be found in the limitations of the FPGA verification method for ADC chips mentioned above, and will not be repeated here. Each unit and module in the aforementioned FPGA verification device for ADC chips can be implemented entirely or partially through software, hardware, or a combination thereof. These units and modules can be embedded in hardware or independently of the processor in a computer device, or stored in software in the memory of a computer device, so that the processor can call and execute the operations corresponding to each unit and module.

[0105] According to another aspect of the present invention, a computer device is provided, which may be a server, and its internal structure diagram is shown below. Figure 7 As shown. The computer device includes a processor, memory, network interface, and database connected via a system bus. The processor provides computing and control capabilities. The memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The database stores data. The network interface communicates with external terminals via a network connection. When the computer program is executed by the processor, it implements the FPGA verification method for ADC chips described above. Specifically, the method includes the following steps:

[0106] The central processing unit, ADC controller, ADC verification module, interface monitoring module, and memory are built in the FPGA;

[0107] The ADC verification module is used to acquire sampling data from the ADC chip;

[0108] The ADC controller is used to acquire sampling data from the ADC verification module;

[0109] The interface monitoring module is used to sample the interface timing data between the ADC controller and the ADC verification module.

[0110] The central processing unit acquires the sampling data from the ADC controller and writes it into memory to generate a first file, and acquires the interface timing data from the interface monitoring module and writes it into memory to generate a second file;

[0111] The analysis software is run on the host computer, and the analysis software is used to retrieve the first file and the second file from the memory and perform analysis to determine whether the sampling of the ADC controller is correct.

[0112] According to another aspect of the present invention, a computer-readable storage medium is provided, on which a computer program is stored, which, when executed by a processor, implements the above-described FPGA verification method for an ADC chip, specifically including the following steps:

[0113] The central processing unit, ADC controller, ADC verification module, interface monitoring module, and memory are built in the FPGA;

[0114] The ADC verification module is used to acquire sampling data from the ADC chip;

[0115] The ADC controller is used to acquire sampling data from the ADC verification module;

[0116] The interface monitoring module is used to sample the interface timing data between the ADC controller and the ADC verification module.

[0117] The central processing unit acquires the sampling data from the ADC controller and writes it into memory to generate a first file, and acquires the interface timing data from the interface monitoring module and writes it into memory to generate a second file;

[0118] The analysis software is run on the host computer, and the analysis software is used to retrieve the first file and the second file from the memory and perform analysis to determine whether the sampling of the ADC controller is correct.

[0119] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0120] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0121] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. An FPGA verification method for ADC chips, characterized in that, The method includes; The central processing unit, ADC controller, ADC verification module, interface monitoring module, and memory are built in the FPGA; The ADC verification module is used to acquire sampling data from the ADC chip; The ADC controller is used to acquire sampling data from the ADC verification module; The interface monitoring module is used to sample the interface timing data between the ADC controller and the ADC verification module. The central processing unit acquires the sampling data from the ADC controller and writes it into memory to generate a first file, and acquires the interface timing data from the interface monitoring module and writes it into memory to generate a second file; The analysis software is run on the host computer, and the analysis software is used to obtain the first file and the second file from the memory and analyze them to determine whether the ADC controller sampling is correct. The step of using the analysis software to retrieve the first and second files from the memory and analyzing them to determine whether the ADC controller sampling is correct includes: The interface timing data in the second file is compared with the ADC interface specification to determine whether the interface access between the ADC verification module and the ADC controller is correct. If the interface access between the ADC verification module and the ADC controller is correct, the sampled data is extracted from the interface timing data in the second file, and the extracted sampled data is compared with the sampled data in the first file. If the extracted sampled data is the same as the sampled data in the first file, it is confirmed that the sampling from the ADC controller is correct.

2. The method according to claim 1, characterized in that, The method further includes: The data generated internally by the ADC verification module through a software algorithm is used as the sampling data.

3. The method according to claim 1, characterized in that, The step of using the analysis software to retrieve the first and second files from the memory and analyzing them to determine whether the ADC controller sampling is correct further includes: If the sampled data is generated internally by the ADC verification module using a software algorithm, then the software algorithm is ported to the analysis software. The analysis software uses the software algorithm to generate data and determines whether the generated data is the same as the sampled data in the first file. If the generated data is the same as the sampled data in the first file, it is confirmed that the sampling from the ADC controller is correct.

4. The method according to claim 1, characterized in that, The step of comparing the interface timing data in the second file with the ADC interface specification to determine whether the interface access between the ADC verification module and the ADC controller is correct includes: The ADC digital interface timing diagram describing the operation of the ADC controller can be recovered based on the interface timing data in the second file. The relative time difference between all digital interface signals is calculated based on the ADC digital interface timing diagram to obtain the signal timing in actual operation. Compare the signal timing in the actual work with the requirements in the ADC interface specification; If the signal timing in actual operation conforms to the requirements of the ADC interface specification, then the interface access between the ADC verification module and the ADC controller is confirmed to be correct. If the signal timing in actual operation violates the requirements of the ADC interface specification, it is confirmed that the interface access between the ADC verification module and the ADC controller is incorrect, and a timing diagram for the violation is drawn and output.

5. The method according to claim 1, characterized in that, The ADC chip is an analog-to-digital converter in the baseboard management controller.

6. The method according to claim 5, characterized in that, The analog-to-digital converter is used to acquire voltage signals from the server motherboard.

7. An FPGA verification device for ADC chips, characterized in that, The device includes: The building unit is configured to build a central processing unit, ADC controller, ADC verification module, interface monitoring module and memory in the FPGA; The first acquisition unit is configured to acquire sampling data from the ADC chip using the ADC verification module. The second acquisition unit is configured to acquire sampled data from the ADC verification module using the ADC controller. A sampling unit is configured to use the interface monitoring module to sample the interface timing data between the ADC controller and the ADC verification module. The writing unit is configured to use the central processing unit to obtain the sampling data from the ADC controller and write it into memory to generate a first file, and to obtain the interface timing data from the interface monitoring module and write it into memory to generate a second file; An analysis unit is configured to run analysis software in a host computer, and use the analysis software to retrieve a first file and a second file from the memory and perform analysis to determine whether the sampling by the ADC controller is correct. The step of using the analysis software to retrieve the first and second files from the memory and analyzing them to determine whether the ADC controller sampling is correct includes: The interface timing data in the second file is compared with the ADC interface specification to determine whether the interface access between the ADC verification module and the ADC controller is correct. If the interface access between the ADC verification module and the ADC controller is correct, the sampled data is extracted from the interface timing data in the second file, and the extracted sampled data is compared with the sampled data in the first file. If the extracted sampled data is the same as the sampled data in the first file, it is confirmed that the sampling from the ADC controller is correct.

8. A computer device, characterized in that, include: At least one processor; as well as A memory storing a computer program executable in the processor, wherein the processor executes the program to perform the method according to any one of claims 1-6.

9. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it performs the method described in any one of claims 1-6.

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