Voice activity detection apparatus and voice activity detection method

Abstract

This application provides a voice activity detection device and a voice activity detection method. The voice activity detection device includes an audio processing circuit, a first memory, and a processor. The audio processing circuit processes an audio signal provided by an audio generation circuit to generate first audio data. The first memory stores the first audio data and a first code. The processor executes the first code to operate in a first mode and switches to operating in a second mode in response to an interrupt signal provided by the audio generation circuit, to execute a second code in a second memory to determine whether the first audio data stored in the first memory includes a voice signal, wherein the power consumption of the processor operating in the first mode is lower than the power consumption of the processor operating in the second mode.

Description

Technical Field

[0001] This application relates to the field of artificial intelligence technology, specifically to a speech activity detection device and a speech activity detection method. Background Technology

[0002] With technological advancements, more and more electronic devices are becoming voice-controlled. In existing technologies, voice activity detection devices typically use a master processor and a slave processor to detect voice commands. During standby, the master processor is in a sleep state, while the slave processor can operate to wait for and receive voice commands to wake up the master processor. After waking up the master processor, the slave processor enters a sleep state, and the awakened master processor can perform subsequent operations based on the voice commands. In this technology, the master and slave processors share the same memory, preventing the memory from actively switching to a low-power mode. Furthermore, during the same period, one of the master or slave processor is in a sleep state without performing any other substantial operations, leading to increased system cost and power consumption. Summary of the Invention

[0003] In some embodiments, one of the objectives of this application is to provide a voice activity detection device and a voice activity detection method that can save power consumption and system costs, thereby improving the shortcomings of the prior art.

[0004] In some embodiments, the voice activity detection device includes an audio processing circuit, a first memory, and a processor. The audio processing circuit processes an audio signal provided by an audio generation circuit to generate first audio data. The first memory stores the first audio data and a first code. The processor executes the first code to operate in a first mode and switches to operate in a second mode in response to an interrupt signal provided by the audio generation circuit, to execute a second code in a second memory to determine whether the first audio data stored in the first memory includes a voice signal, wherein the power consumption of the processor operating in the first mode is lower than the power consumption of the processor operating in the second mode.

[0005] In some embodiments, the voice activity detection method includes the following operations: generating first audio data based on an audio signal provided by an audio generation circuit, and storing the first audio data in a first memory; executing first code in the first memory via a processor to operate in a first mode; and switching the processor to operate in a second mode in response to an interrupt signal provided by the audio generation circuit, to execute second code in a second memory to determine whether the first audio data stored in the first memory includes a voice signal, wherein the power consumption of the processor operating in the first mode is lower than the power consumption of the processor operating in the second mode.

[0006] The features, implementation, and effects of this application are described in detail below with reference to the accompanying drawings, and preferred embodiments are provided in detail. Attached Figure Description

[0007] Figure 1 This is a schematic diagram of a voice activity detection device according to some embodiments of this application;

[0008] Figure 2 Drawings based on some embodiments of this application Figure 1 Flowchart of the operation of the voice activity detection device;

[0009] Figure 3 Drawings based on some embodiments of this application Figure 1 A diagram illustrating the operation of multiple memory locations;

[0010] Figure 4 Drawings based on some embodiments of this application Figure 1 Flowchart of the operation of the voice activity detection device;

[0011] Figure 5 Drawings based on some embodiments of this application Figure 1 The waveform timing diagram of the audio signal in the image; and

[0012] Figure 6 A flowchart of a speech activity detection method is provided based on some embodiments of this application.

[0013] Figure label:

[0014] 100: Voice activity detection device;

[0015] 101: Audio generation circuit;

[0016] 102, 150: Memory;

[0017] 110: Interrupt controller;

[0018] 120: Oscillator;

[0019] 130: Processor;

[0020] 140: Audio processing circuit;

[0021] 141: Analog-to-digital converter;

[0022] 142: Audio codec;

[0023] 160: Memory interface unit;

[0024] 170: Clock generator circuit;

[0025] 171, 172: Phase-locked loop;

[0026] 300: Ring buffer;

[0027] 600: Voice activity detection method;

[0028] CK1, CK2: Clock signals;

[0029] CKREF: Reference clock signal;

[0030] D1, D2, D3: Audio data;

[0031] P1, P2: Code;

[0032] RP: Read metrics;

[0033] S201~S212, S401~S412, S610, S620, S630: Operation;

[0034] SA: Audio signal;

[0035] SD: Digital Data;

[0036] ST: Interrupt signal;

[0037] WP: Write Metric;

[0038] t0, t1, t2: time. Detailed Implementation

[0039] All terms used herein have their ordinary meanings. The definitions of the above terms in commonly used dictionaries, and any examples of the use of any term discussed herein, are merely illustrative and should not limit the scope or meaning of this application. Similarly, this application is not limited to the various embodiments shown in this specification.

[0040] As used herein, “coupled” or “connected” can refer to two or more components making direct physical or electrical contact with each other, or indirectly making direct physical or electrical contact with each other, or to two or more components operating or acting on each other. As used herein, the term “circuit” can refer to a device consisting of at least one transistor and / or at least one active or passive component connected in a certain manner to process signals.

[0041] Figure 1This is a schematic diagram of a voice activity detection (VAD) device 100 according to some embodiments of this application. The VAD device 100 includes an interrupt controller 110, an oscillator 120, a processor 130, an audio processing circuit 140, memory 150, a memory interface unit 160, and a clock generator circuit 170. The interrupt controller 110 is coupled to the audio generation circuit 101 to receive an interrupt signal ST generated by the audio generation circuit 101 and to request the processor 130 to perform corresponding hardware / software processing based on the interrupt signal ST. In some embodiments, the audio generation circuit 101 can collect sound signals from the application environment and generate an audio signal SA. The audio generation circuit 101 can provide the audio signal SA to the audio processing circuit 140 and can determine whether the audio signal SA meets a predetermined condition to generate the interrupt signal ST. For example, when the audio generation circuit 101 determines that the volume of the audio signal SA exceeds a predetermined threshold, the audio generation circuit 101 can generate the interrupt signal ST.

[0042] Oscillator 120 can generate a reference clock signal CKREF and transmit the reference clock signal CKREF to clock generator circuit 170. In some embodiments, oscillator 120 may be, but is not limited to, a quartz oscillator. Clock generator circuit 170 can generate the timing required by processor 130, audio processing circuit 140, and other circuits in the system based on the reference clock signal CKREF. For example, clock generator circuit 170 may include phase-locked loop (PLL) 171 and phase-locked loop 172. PLL 171 can generate clock signal CK1 based on the reference clock signal CKREF and provide clock signal CK1 to processor 130. Similarly, PLL 172 can generate clock signal CK2 based on the reference clock signal CKREF and provide clock signal CK2 to audio processing circuit 140.

[0043] Processor 130 can access code P1 stored in memory 150 to operate in a first mode and wait for audio generation circuit 101 to generate an interrupt signal ST. When audio generation circuit 101 generates interrupt signal ST, processor 130 can respond to this interrupt signal ST and execute code P2 in memory 102 to switch from operating in the first mode to operating in a second mode, thereby determining whether one or more audio data stored in memory 150 includes human voice signals. In some embodiments, the power consumption of processor 130 operating in the first mode is lower than the power consumption of processor 130 operating in the second mode. That is, the first mode can be a low-power mode (or a wait-for-interrupt mode). When processor 130 operates in the first mode, processor 130 will operate at a lower speed and wait to receive interrupt signal ST, thereby saving power consumption. Alternatively, when processor 130 switches to operating in the second mode, processor 130 will switch to receiving a clock signal CK1 with a higher frequency, so processor 130 will operate at a higher speed to detect whether there are voice control commands to be processed more quickly.

[0044] In some embodiments, memory 150 may be, but is not limited to, static random access memory. Processor 130 may be coupled to memory 102 via memory interface unit 160. In some embodiments, memory 102 may be, but is not limited to, dynamic random access memory. Audio processing circuitry 140 may process audio signal SA to generate audio data (e.g., for...). Figure 3 The audio data (D1 to D3) in the audio processing circuit 140 may include, for example, an analog-to-digital converter 141 and an audio codec 142. The analog-to-digital converter 141 converts the audio signal SA according to the clock signal CK2 to generate digital data SD. The audio codec 142 processes the digital data SD to generate audio data.

[0045] Figure 2 Drawings based on some embodiments of this application Figure 1 A flowchart illustrating the operation of the voice activity detection device 100. In some embodiments, Figure 2The multiple operations correspond to loop mode. In operation S201, the audio processing circuit 140 and the clock generator circuit 170 are initialized. For example, after the voice activity detection device 100 is started, the processor 130 can execute the relevant software and / or firmware of the system to initially set various parameters (e.g., clock frequency, sampling rate, gain, codec format, etc.) in the audio processing circuit 140 and the clock generator circuit 170. In operation S202, some circuits (excluding the phase-locked loop 172) are set to operate in a low-speed state. For example, after initialization is completed, the aforementioned relevant software and / or firmware can further close the phase-locked loop 171 and switch the clock signal received by the processor 130 from the clock signal CK1 to another clock signal (not shown) generated based on the reference clock signal CKREF. Figure 1 Its frequency can be lower than the frequency of the reference clock signal CKREF. Simultaneously, the aforementioned related software and / or firmware can further switch the clock signal (not shown) received by the memory interface unit 160 to the reference clock signal CKREF, causing the memory interface unit 160 to also operate in a low-speed state. On the other hand, since the phase-locked loop 172 is not closed, the phase-locked loop 172 can provide a clock signal CK2 to the audio processing circuit 140 according to the reference clock signal CKREF.

[0046] In operation S203, memory 102 is controlled to operate in a third mode, and code P1 in memory 150 is executed. In operation S204, processor 130 operates in a first mode. For example, as described above, processor 130 may execute code P1 in memory 150 to operate in the first mode to wait for audio generation circuit 101 to generate interrupt signal ST. On the other hand, the aforementioned related software and / or firmware may control memory 102 to operate in the third mode. In some embodiments, the third mode may be a low-power mode of memory 102. For example, if memory 102 is dynamic random access memory, the third mode may be a self-refresh mode. When processor 130 executes code P1 in memory 150 to operate in the first mode, processor 130 does not access memory 102 or the need to access memory 102 is relatively low. Under these conditions, the operating speed of some circuits (e.g., including memory 102, memory interface unit 160, etc.) can be reduced to save overall power consumption.

[0047] In operation S205, the audio generation circuit 101 is enabled to begin generating an audio signal SA, and audio data is written to the memory 150 via the audio processing circuit 140. As previously described, when the processor 130 executes code P1 in the memory 150, the processor 130 operates in a first mode to wait for the audio generation circuit 101 to issue an interrupt signal ST. After the audio generation circuit 101 is started by the aforementioned related software and / or firmware, the audio generation circuit 101 can begin collecting ambient sound to generate an audio signal SA, and the audio data corresponding to the audio signal SA is stored in the memory 150 via the audio processing circuit 140.

[0048] In operation S206, the audio generation circuit 101 issues an interrupt signal ST, and the processor 130, in response to the interrupt signal ST, executes code P2 in memory 102 to switch to operation in the second mode. In operation S207, the clock generator circuit 170 is configured to switch some circuits to operate at a higher frequency, and the memory 102 is controlled to operate in the fourth mode. For example, when the audio generation circuit 101 determines that the volume of the audio signal SA exceeds a predetermined threshold, the audio generation circuit 101 may issue an interrupt signal ST to the interrupt controller 110, so that the processor 130 may, in response to this interrupt signal ST, switch to executing code P2 in memory 102 to operate in the second mode. On the other hand, under this condition, the aforementioned related software and / or firmware may be configured accordingly to configure the clock generator circuit 170 so that the phase-locked loops 171 and 172 can generate clock signals CK1 and CK2 with higher frequencies, and switch the memory interface unit 160 to operate based on the higher frequency clock signals. Simultaneously, the aforementioned software and / or firmware can control memory 102 to switch to a fourth mode, which can be a faster active mode. In other words, the power consumption of memory 102 operating in the third mode is lower than the power consumption of memory 102 operating in the fourth mode.

[0049] In operation S208, it is determined whether the audio data in memory 150 includes a human voice signal. If it is determined that the audio data in memory 150 includes a human voice signal, operation S209 is executed. Alternatively, if it is determined that the audio data in memory 150 does not include a human voice signal, operation S202 is executed. In operation S209, memory 150 is controlled to transfer the audio data to memory 102, and audio processing circuit 140 is controlled to store subsequently generated audio data in memory 102. For example, code P2 in memory 102 includes a signal processing algorithm for recognizing human voice signals. Processor 130 can execute code P2 to determine whether the audio data in memory 150 includes a human voice signal according to the algorithm. If the audio data includes a human voice signal, processor 130 can control memory 150 to transfer the audio data to memory 102 (instead of storing it in memory 150). Thus, after transferring the audio data to memory 102, processor 130 can release the temporary storage space in memory 150 previously used to store the audio data for use by other circuits in the system. If the audio data does not include human voice signals, then operation S202 is re-executed to wait for the next voice command.

[0050] In operation S210, it is determined whether the audio data in memory 102 includes keyword information. If it is determined that the audio data in memory 102 includes keyword information, operation S211 is executed. Alternatively, if it is determined that the audio data in memory 102 does not include keyword information, operation S212 is executed. In operation S211, subsequent processing is performed based on the keyword information. In operation S212, it continues to detect whether keyword information appears until the audio generation circuit 101 determines that the volume of the subsequently received audio signal SA does not exceed a predetermined threshold.

[0051] For example, code P2 in memory 102 also includes a signal processing algorithm for identifying keyword information. Processor 130 can execute code P2 to determine whether the audio data in memory 102 includes the keyword information according to the algorithm. In some embodiments, the keyword information may be, but is not limited to, a voice command used to control a specific device to perform a preset operation. If processor 130 determines that the audio data in memory 102 includes keyword information, processor 130 can perform subsequent processing based on this keyword information to control the specific device to perform the preset operation. Alternatively, if processor 130 determines that the audio data in memory 102 does not include keyword information, processor 130 can continue to determine whether keyword information appears based on the audio data subsequently stored in memory 102 until audio generation circuit 101 determines that the volume of the subsequently received audio signal SA does not exceed a predetermined threshold (e.g., to stop the user from inputting voice commands).

[0052] In the above operations, processor 130 executes code P1 in memory 150 to operate in a first mode to reduce power consumption and wait for interrupt signal ST. Therefore, the operations performed by processor 130 in the first mode are relatively simple. Processor 130 executes code P2 in memory 102 to operate in a second mode to perform multiple algorithms such as voice recognition and keyword recognition at a higher processing speed. Therefore, the code size and / or complexity of code P1 are relatively lower than that of code P2. In some embodiments, since the cost of memory 102 is higher than that of memory 150, the above configuration can reduce the required capacity of memory 102, thereby reducing the overall cost. In addition, after switching to use memory 102, memory 150 can release the temporary storage space originally used to store audio data, and other circuits in the system can also share memory 150 in a time-sharing manner, thereby avoiding the need for additional memory and reducing additional power consumption and / or system cost.

[0053] Figure 3 Drawings based on some embodiments of this application Figure 1 The diagram illustrates the operation of memory 150 and memory 102. As previously mentioned, memory 150 can be static random access memory. Processor 130 can configure memory 150 to plan a temporary storage space, which can be set as a ring buffer 300. Processor 130 can access this ring buffer 300 according to the write indicator WP and the read indicator RP. Before operation S209 is executed, audio data D1 and audio data D2 generated by audio processing circuit 140 according to audio signal SA from audio generation circuit 101 can be stored in this ring buffer 300. In operation S209, processor 130 reads audio data D1 according to read indicator RP and determines that audio data D1 includes human voice signal, transfers audio data D1 and audio data D2 (write indicator WP corresponds to the end position of audio data D2, indicating that audio data D2 is also valid audio data) to memory 102, and controls audio processing circuit 140 to store subsequently generated audio data D3 into memory 102. That is, the audio processing circuit 140 generates multiple audio data D1 and D2, and then generates audio data D3 based on the audio signal SA. After transferring audio data D1 and audio data D2 to memory 102, the temporary storage space corresponding to the ring buffer 300 can be released. Then, the processor 130 can determine whether it includes human voice signals and keyword information based on the multiple consecutive audio data D1, D2 and D3 in memory 102. In this way, the processor 130 can merge the multiple audio data D1, D2 and D3, and more completely determine whether the user has issued a voice command based on the continuous audio content of the merged audio data.

[0054] Figure 4Drawings based on some embodiments of this application Figure 1 A flowchart illustrating the operation of the voice activity detection device 100. In some embodiments, Figure 4 Several operations correspond to interrupt mode, which consumes less power than... Figure 2 The power consumption of the loop mode. The interrupt mode includes multiple operations S401 to S412, among which multiple operations S403 to S404, S406 and S408 to S412 are respectively the same as Figure 2 The multiple operations S203-S204, S206, and S208-S212 will not be described in detail here. The following mainly explains... Figure 2 There are differences in the operation.

[0055] In operation S401, the analog-to-digital converter 141 and the clock generator circuit 170 are initialized, and the audio codec 142 is turned off. Unlike operation S201, in this example, immediately after the voice activity detection device 100 is started, the processor 130 can execute the relevant system software and / or firmware to initialize only the analog-to-digital converter 141 and the clock generator circuit 142, while the audio codec 142 remains off. In operation S402, some circuits (including phase-locked loop 171 and phase-locked loop 172) are set to operate at low speed. Unlike operation S202, in this embodiment, the aforementioned relevant software and / or firmware further disables the phase-locked loop 172. Under this condition, the clock generator circuit 170 does not provide the clock signal CK2 to the audio processing circuit 140.

[0056] In operation S405, the audio generation circuit 101 is enabled to begin generating the audio signal SA. Unlike operation S205, in this example, since the audio processing circuit 140 has not received the clock signal CK2 and the audio codec 142 has not yet been enabled, the audio processing circuit 140 will not generate corresponding audio data based on the audio signal SA at this stage, nor will it store the corresponding audio data in the memory 150.

[0057] In operation S407, the clock generator circuit 170 is configured, enabling the phase-locked loop 172 and the audio codec 142, causing some circuitry to operate at higher frequencies, and controlling the memory 102 to operate in the fourth mode. Unlike... Figure 2In this example, when the audio generation circuit 101 determines that the volume of the audio signal SA exceeds a predetermined threshold, the aforementioned related software / firmware can configure the clock generator circuit 170 and enable all phase-locked loops (e.g., including phase-locked loops 171 and 172) and the audio codec 142 to begin generating clock signals CK1 and CK2 with higher frequencies. Thus, the clock generator circuit 170 begins providing clock signal CK2 to the analog-to-digital converter 141, allowing the audio codec 142 to begin generating corresponding audio data and begin storing this audio data in memory 150. On the other hand, the processor 130 can execute code P2 in memory 102 to determine whether the audio data in memory 150 includes a human voice signal.

[0058] Therefore, it should be understood that, Figure 2 In the loop mode, when the processor 130 operates in the first mode, the audio processing circuit 140 stores audio data into the memory 150. Unlike... Figure 2 ,exist Figure 4 In the interrupt mode, when the processor 130 operates in the first mode, the clock generator circuit 170 does not generate the clock signal CK2, causing at least a portion of the audio processing circuit 140 to be disabled and not operating, thus preventing the generation of audio data into the memory 150. Upon receiving the interrupt signal ST, the processor 130 switches to the second mode, and the audio processing circuit 140 begins generating and storing audio data into the memory 150. Thus, Figure 4 Interrupt mode can save more power consumption. In contrast, Figure 2 The loop-mode can collect more complete audio data. Please refer to [link / reference here] for more information. Figure 5 Explanation.

[0059] Figure 5 Drawings based on some embodiments of this application Figure 1 The waveform timing diagram of the audio signal SA in the image is shown below. (For easier understanding...) Figure 2 The loop pattern and Figure 4 Differences in interrupt modes, such as Figure 5As shown, in loop mode, the audio codec 142 and phase-locked loop 172 are enabled, allowing the audio processing circuit 140 to store the corresponding audio data in memory 150 starting at time t0. When the audio generation circuit 101 determines that the volume of the audio signal SA is greater than a predetermined threshold, the audio generation circuit 101 issues an interrupt signal ST, causing the processor 130 to switch to operation in a second mode at time t1 to begin determining whether the audio data includes human voice signals and keyword information, until the volume of the audio signal SA remains below the predetermined threshold starting at time t2. Unlike loop mode, in interrupt mode, the audio processing circuit 140 does not begin storing the corresponding audio data in memory 150 at time t0, but only after receiving the interrupt signal ST at time t1. That is, in loop mode, the voice activity detection device 100 can store more complete audio data for detection, achieving a higher voice detection accuracy. In interrupt mode, the audio processing circuit 140, clock generator circuit 170, and memory 150 consume less power before time t1, which allows the voice activity detection device 100 operating in interrupt mode to have lower power consumption.

[0060] Figure 6 The following flowchart illustrates a voice activity detection method 600 according to some embodiments of this application. In operation S610, first audio data is generated based on an audio signal provided by an audio generation circuit, and the first audio data is stored in a first memory. In operation S620, a processor executes first code in the first memory to operate in a first mode. In operation S630, the processor switches to a second mode in response to an interrupt signal provided by the audio generation circuit to execute second code in a second memory to determine whether the first audio data stored in the first memory includes a voice signal, wherein the power consumption of the processor operating in the first mode is lower than the power consumption of the processor operating in the second mode.

[0061] The various operations of the above-described voice activity detection method 600 are described in the foregoing embodiments and will not be repeated here. Figure 2 , Figure 4 With / or Figure 6 The operations described are merely examples and are not intended to be performed in the specific order shown in these examples. Without departing from the operational methods and scope of the various embodiments of this application, in Figure 2 , Figure 4 With / or Figure 6 Various operations can be added, replaced, omitted, or executed in different orders as appropriate (e.g., they can be executed simultaneously or partially simultaneously).

[0062] In summary, the voice activity detection apparatus and voice activity detection method in some embodiments of this application can perform voice activity detection without using an additional slave processor and can further improve power consumption.

[0063] Although the embodiments of this application are described above, these embodiments are not intended to limit this application. Those skilled in the art can make variations to the technical features of this application based on the express or implied content of this application. All such variations may fall within the scope of patent protection sought by this application. In other words, the scope of patent protection of this application shall be determined by the scope of the patent application as defined in this specification.

Claims

1. A voice activity detection device, characterized in that, include: An audio processing circuit processes an audio signal provided by an audio generation circuit to generate first audio data. A first memory location stores the first audio data and a first code; as well as A processor executes the first code to operate in a first mode and switches to operate in a second mode in response to an interrupt signal provided by the audio generation circuitry to execute a second code in a second memory to determine whether the first audio data stored in the first memory includes a human voice signal, wherein the code size of the first code is smaller than the code size of the second code. When the processor determines that the first audio data includes the human voice signal, the processor controls the first memory to transfer the first audio data to the second memory, and the audio processing circuit stores a second audio data in the second memory. The audio processing circuit generates the second audio data according to the audio signal after generating the first audio data. The power consumption of the processor operating in the first mode is lower than the power consumption of the processor operating in the second mode.

2. The voice activity detection device as described in claim 1, characterized in that, The processor determines whether the first audio data and the second audio data in the second memory include a keyword information.

3. The voice activity detection device as described in claim 1, characterized in that, After the first audio data is transferred from the first memory to the second memory, the first memory releases a temporary storage space previously used to store the first audio data.

4. The voice activity detection device as described in claim 1, characterized in that, The processor responds to the interrupt signal to control the second memory to switch from operating in a third mode to operating in a fourth mode, and the power consumption of the second memory operation in the third mode is lower than the power consumption of the second memory operation in the fourth mode.

5. The voice activity detection device as described in claim 4, characterized in that, The second memory is a dynamic random access memory, the third mode is a self-refresh mode, and the fourth mode is an active mode.

6. The voice activity detection device as described in claim 1, characterized in that, When the processor is operating in the first mode, the audio processing circuit stores the first audio data into the first memory.

7. The voice activity detection device as described in claim 1, characterized in that, When the processor is operating in the first mode, the audio processing circuit does not store the first audio data in the first memory.

8. The voice activity detection device as described in claim 1, characterized in that, The audio processing circuit includes: An analog-to-digital converter converts the audio signal into digital data; and An audio codec processes the digital data to produce the first audio data.

9. The voice activity detection device as claimed in claim 1, further comprising: A clock generator circuit generates a first clock signal based on a reference clock signal. When the processor is operating in the first mode, the clock generator circuit generates the first clock signal and sends it to the audio processing circuit, and the audio processing circuit processes the audio signal according to the first clock signal to generate the first audio data.

10. The voice activity detection device as claimed in claim 1, further comprising: A clock generator circuit generates a first clock signal based on a reference clock signal. When the processor is operating in the first mode, the clock generator circuit does not generate the first clock signal, so that the audio processing circuit does not generate the first audio data.

11. A method for detecting speech activity, characterized in that, include: A first audio data is generated based on an audio signal provided by an audio generation circuit, and the first audio data is stored in a first memory. A processor executes a first code in the first memory to operate in a first mode; as well as The processor switches to a second mode in response to an interrupt signal provided by the audio generation circuit to execute a second code in a second memory to determine whether the first audio data stored in the first memory includes a human voice signal, wherein the code size of the first code is smaller than the code size of the second code. When the processor determines that the first audio data includes the human voice signal, the processor controls the first memory to transfer the first audio data to the second memory, and the audio processing circuit stores a second audio data in the second memory. The audio processing circuit generates the second audio data according to the audio signal after generating the first audio data. The power consumption of the processor operating in the first mode is lower than the power consumption of the processor operating in the second mode.

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