Non-volatile static random access memory

Abstract

The application provides a non-volatile static random access memory, which comprises a first pass-gate transistor, a second pass-gate transistor, a first pull-up transistor, a second pull-up transistor, a first pull-down transistor and a second pull-down transistor, which together form two cross-coupled inverters and storage nodes, wherein a variable resistance memory is arranged between the first storage node and the first pull-up transistor and the first pull-down transistor, and a variable resistance memory is arranged between the second storage node and the second pull-up transistor and the second pull-down transistor.

Description

Technical Field

[0001] This invention relates to a non-volatile static random access memory (nvSRAM), and more particularly, to a non-volatile static random access memory using resistive variable memory (RRAM). Background Technology

[0002] Static Random Access Memory (SRAM) is a type of random access memory. The term "static" means that as long as power is continuously supplied, the data stored in this type of memory is permanently retained. In contrast, the data stored in Dynamic Random Access Memory (DRAM) needs to be periodically updated to be retained. However, SRAM is also a volatile memory, meaning that when the power supply is interrupted, the data stored in it is lost. This characteristic differs from Read-Only Memory (ROM) or Flash Memory, which retain data even after power is lost.

[0003] SRAM has a low read voltage (V) DD While SRAM boasts advantages such as low voltage (<1V) and fast access speed (<10ns), its volatility limits its suitability for applications requiring long-term data storage in power-off environments. In critical applications such as networking, aerospace, and medical fields, where memory offering all these advantages is needed, non-volatile SRAM (nvSRAM) was developed. Non-volatile SRAM has a wide range of applications because it not only solves the problem of SRAM's inability to permanently store data but also achieves low power consumption and high-speed access.

[0004] There are many methods to create non-volatile SRAM. One method involves transferring the values ​​within the non-volatile SRAM to other non-volatile memories, such as flash memory, magnetic RAM (MRAM), or phase-change memory (PCM), before power is turned off. The stored values ​​can then be retrieved via a restore operation, achieving the effect of non-volatile storage. However, current methods still cannot simultaneously provide non-volatile SRAM with all the advantages of high-speed access, low operating voltage, and low power consumption. Those skilled in the art still need to further develop and improve the current non-volatile SRAM architecture. Summary of the Invention

[0005] In view of the current state of the prior art, the present invention proposes a novel non-volatile static random access memory (nvSRAM), characterized by the placement of variable resistive memories between the standard SRAM storage nodes and the pull-up and pull-down transistors. These variable resistive memories are placed at the original locations of the contacts and overlap with the drains of the transistors. This achieves the advantages of high-speed access, low operating voltage, and low power consumption without increasing the area required for layout.

[0006] One aspect of this invention is to provide a non-volatile static random access memory (SRAM) comprising: a first through-gate transistor having a first gate, a first source, and a first drain, wherein the first source is connected to a bit line and the first gate is connected to a word line; a second through-gate transistor having a second gate, a second source, and a second drain, wherein the second source is connected to a complementary bit line and the second gate is connected to the word line; a first pull-up transistor having a third gate, a third source, and a third drain, wherein the third source is connected to a common first power line; a second pull-up transistor having a fourth gate, a fourth source, and a fourth drain, wherein the fourth source is connected to the common first power line; and a first pull-down transistor having a fifth gate, a second source, and a third drain. The device comprises a fifth source and a fifth drain, wherein the fifth source is connected to a common second power supply line; and a second pull-down transistor having a sixth gate, a sixth source, and a sixth drain, wherein the sixth source is connected to the common second power supply line; wherein the first drain, the fourth gate, and the sixth gate are connected to a first memory node, the second drain, the third gate, and the fifth gate are connected to a second memory node, and a first variable resistive memory is provided between the first memory node and the third drain, a second variable resistive memory is provided between the first memory node and the fifth drain, a third variable resistive memory is provided between the second memory node and the fourth drain, and a fourth variable resistive memory is provided between the second memory node and the sixth drain.

[0007] Another aspect of the present invention is to provide a method for operating the aforementioned non-volatile static random access memory, which includes initialization operations, clearing operations, writing operations, and reading operations.

[0008] These and other objects of the present invention should become more apparent to the reader after reading the detailed description of the preferred embodiments, which are illustrated in various figures and drawings below. Attached Figure Description

[0009] This specification includes accompanying drawings, which form part of the document, to provide the reader with a further understanding of embodiments of the invention. These drawings depict some embodiments of the invention and, together with the description herein, illustrate its principles. In these drawings:

[0010] Figure 1 This is a circuit diagram of a non-volatile static random access memory in a preferred embodiment of the present invention.

[0011] Figure 2 This is a three-dimensional schematic diagram of a non-volatile static random access memory circuit according to a preferred embodiment of the present invention.

[0012] Figure 3 This is a three-dimensional schematic diagram showing the connection relationship between a variable resistive memory and a transistor in a non-volatile static random access memory according to a preferred embodiment of the present invention.

[0013] Figures 4 to 6 This is a circuit diagram illustrating the steps of the non-volatile static random access memory during initialization (forming) operation in a preferred embodiment of the present invention.

[0014] Figures 7 to 9 This is a circuit diagram illustrating each step of the clear operation of a non-volatile static random access memory in a preferred embodiment of the present invention.

[0015] Figures 10 to 11 This is a circuit diagram illustrating the steps of the write operation of a non-volatile static random access memory in a preferred embodiment of the present invention; and

[0016] Figures 12 to 13 This is a circuit diagram illustrating each step of the read operation of a non-volatile static random access memory in a preferred embodiment of the present invention.

[0017] It should be noted that all illustrations in this specification are for illustrative purposes. For clarity and ease of illustration, the size and scale of the components in the illustrations may be exaggerated or reduced. Generally, the same reference symbols in the illustrations are used to indicate corresponding or similar component features in modified or different embodiments.

[0018] Symbol Explanation

[0019] 100 base

[0020] 102 doped region

[0021] 103 Polycrystalline Silicon Pattern

[0022] 104 Contacts

[0023] 106 Guide Hole Fittings

[0024] 110 Lower electrode

[0025] 112 Capacitor Dielectric Layer

[0026] 114 Titanium layer

[0027] 116 Titanium nitride layer

[0028] BL bitline

[0029] BL' Complementary Bit Line

[0030] D1~D6 Drain

[0031] Gates G1 to G6

[0032] M1, M1a, M1b First metal layer

[0033] PD1, PD2 pull-down transistors

[0034] PG1 and PG2 are connected via gate transistors.

[0035] PU1, PU2 pull-up transistors

[0036] R1~R4 Variable Resistor Memory

[0037] S First power line

[0038] S' Second power line

[0039] S1~S6 Source

[0040] SN1, SN2 storage nodes

[0041] V dd Operating voltage value

[0042] WL lettering Detailed Implementation

[0043] Exemplary embodiments of the present invention will now be described in detail below, with reference to the accompanying drawings illustrating the described features to enable the reader to understand and achieve the technical effects. The reader will understand that the descriptions herein are by way of illustration only and are not intended to limit the scope of the invention. Various embodiments of the invention and various non-conflicting features thereof can be combined or rearranged in various ways. Modifications, equivalents, or improvements to the invention will be understood by those skilled in the art without departing from the spirit and scope of the invention, and are intended to be included within the scope of the invention.

[0044] Readers should easily understand that the meanings of "on," "above," and "above" in this case should be interpreted in a broad sense, so that "on" not only means "directly on" something, but also includes the meaning of being "on" something with an intermediary feature or layer, and "above" or "above" not only means "above" or "above" something, but can also include the meaning of being "above" or "above" something without an intermediary feature or layer (i.e., directly on something).

[0045] In addition, spatial terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein for convenience to describe the relationship between one element or feature and one or more other elements or features, as shown in the accompanying drawings.

[0046] Readers can generally understand terms at least partially from their usage in context. For example, depending at least partially on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least partially on the context, terms such as "a," "an," "the," or "the" can also be understood to convey either a singular or a plural usage. Furthermore, the term "based on" can be understood not necessarily to convey an exclusive set of factors, but rather to allow for the presence of additional factors that are not necessarily explicitly described, which also depends at least partially on the context.

[0047] Readers will better understand that when words such as "comprising" and / or "containing" are used in this specification, they expressly define the presence of the stated features, areas, wholes, steps, operations, elements and / or components, but do not preclude the possibility of the presence or addition of one or more other features, areas, wholes, steps, operations, elements, components and / or combinations thereof.

[0048] First, please refer to... Figure 1This is a circuit diagram of a non-volatile static random access memory (nvSRAM) according to a preferred embodiment of the present invention. The nvSRAM of the present invention includes six field-effect transistors (FETs) and four capacitors (6T4C architecture). The four FETs (first and second pull-up transistors PU1, PU2 and first and second pull-down transistors PD1, PD2) form two cross-coupled inverters. The two inverters are symmetrical and latch "0" and "1" data to achieve data storage. The four capacitors are respectively disposed between the storage node and the four FETs to serve as non-volatile storage cells. The other two FETs (first and second through-gate transistors PG1, PG2) serve as control switches for bit lines used for read, write, and erase operations.

[0049] like Figure 1As shown, the six field-effect transistors in the non-volatile static random access memory (SRAM) are each composed of three parts: gate, source, and drain. The sources S1 and S2 of the first pass-gate transistor PG1 and the second pass-gate transistor PG2 are connected to a bit line BL and a complementary bit line BL', respectively. Their drains D1 and D2 are connected to a first storage node SN1 and a second storage node SN2, respectively. The gates G1 and G2 are connected to a common word line WL. The sources S3 and S4 of the first pull-up transistor PU1 and the second pull-up transistor PU2 are connected to a common first power supply line S. Their drains D3 and D4 are connected to the first storage node SN1 and the second storage node SN2, respectively. In a preferred embodiment of the present invention, a first resistive random access memory (RRAM) R1 is disposed between the drain D3 of the first pull-up transistor PU1 and the first storage node SN1, and a third resistive random access memory R3 is disposed between the drain D4 of the second pull-up transistor PU2 and the second storage node SN2. Similarly, the sources S5 and S6 of the first pull-down transistor PD1 and the second pull-down transistor PD2 are connected to a common second power line S', and their drains D5 and D6 are connected to the first storage node SN1 and the second storage node SN2, respectively. A second resistive random access memory R2 is disposed between the drain D5 of the first pull-down transistor PD1 and the first storage node SN1, and a fourth resistive random access memory R4 is disposed between the drain D6 of the second pull-down transistor PD2 and the second storage node SN2. Thus, the non-volatile static random access memory of the present invention comprises a total of four resistive random access memories R1 to R4, which are respectively located between the storage nodes and each pull-up and pull-down transistor to achieve non-volatile storage. Furthermore, the first memory node SN1 is connected to the drain D1 of the first through-gate transistor PG1, the first variable-resistive memory R1, and the second variable-resistive memory R2, as well as the gate G4 of the second pull-up transistor PU2 and the gate G6 of the second pull-down transistor PD2. The second memory node SN2 is connected to the drain D2 of the second through-gate transistor PG2, the third variable-resistive memory R3, and the fourth variable-resistive memory R4, as well as the gate G3 of the first pull-up transistor PU1 and the gate G5 of the first pull-down transistor PD1, thereby achieving a mutual latching effect. In this embodiment of the invention, the two pull-up transistors PU1 and PU2 can be PMOS transistors, and the two pull-down transistors PD1 and PD2 can be NMOS transistors.

[0050] Please refer to now. Figure 2This is a three-dimensional schematic diagram of the circuit of the aforementioned non-volatile static random access memory (SRAM), used to illustrate in more detail the relative positions and connection relationships of the various components of the non-volatile SRAM of the present invention. For example... Figure 2 As shown, the non-volatile static random access memory of the present invention is disposed on a substrate 100. The substrate 100 can be any component with a carrying function, such as a semiconductor substrate, including a silicon-containing substrate, a silicon insulator (SOI) substrate, or a sapphire substrate, but is not limited thereto. Multiple non-connected N-type doped regions 102a and P-type doped regions 102b are formed in the substrate 100 by ion implantation to serve as the source, drain, and channel of each transistor. Multiple strip-shaped polysilicon patterns 103 formed on the substrate 100 span these doped regions to serve as the gates of these transistors. Taking the first through-gate transistor PG1 as an example, its gate G1 is a polysilicon pattern 103a spanning the N-type doped region 102a, and the N-type doped regions 102a on both sides of the gate G1 are its source S1 and drain D1, respectively. A word line WL is disposed above the polysilicon pattern 103a, which is connected to the gate G1 via a contact (not shown) to control the switching of the first through-gate transistor PG1. The source S1 of the first through-gate transistor PG1 is connected to the bit line BL above via interconnection structures such as vias 106. In this embodiment, the word line WL may be located in the first metal layer M1, and the bit line BL may be located in the second metal layer M2.

[0051] Rereference Figure 2 In this embodiment of the invention, the first pull-down transistor PD1 is located next to the first through-gate transistor PG1 and uses a different N-type doped region 102a. The drain D5 of the first pull-down transistor PD1 is connected to the drain D1 of the first through-gate transistor PG1 via a contact and the first metal layer M1a. Similarly, the polysilicon pattern 103b spans the N-type doped region 102a as the gate G5 of the first pull-down transistor PD1, and the other side of the gate G5 is the source S5 of the first pull-down transistor PD1. In this embodiment, the source S5 of the first pull-down transistor PD1 is sequentially connected to the upper second power line S' via interconnect circuits such as a contact, the first metal layer M1, and a via 106. The second power line S' may be located in the layer of the second metal layer M2.

[0052] Rereference Figure 2In this embodiment of the invention, the first pull-up transistor PU1 is positioned a distance away from the first pull-down transistor PD1, using a separate P-type doped region 102b. The gate G3 of the first pull-up transistor PU1 can share the polysilicon pattern 103b with the gate G5 of the first pull-down transistor PD1, meaning their gates are connected. The source S3 of the first pull-up transistor PU1 is connected to the metal line of the first power line S above it via a contact, and the drain D3 of the first pull-up transistor PU1 is connected to the drain D5 of the first pull-down transistor PD1 and the drain D1 of the first through-gate transistor PG1 via a contact and the first metal layer M1a. The first power line S can be located within the first metal layer M1.

[0053] In this embodiment, the second through-gate transistor PG2, the second pull-down transistor PD2, and the second pull-up transistor PU2 are arranged in a completely mirror-symmetrical manner opposite to the first through-gate transistor PG1, the first pull-down transistor PD1, and the first pull-up transistor PU1, and have the same components and structure as described above. It should be noted that, as shown in the figure, the gate polysilicon pattern 103b shared by the first pull-up transistor PU1 and the first pull-down transistor PD1 also has branches extending towards the second pull-down transistor PD2, and is connected to the drain D6 of the second pull-down transistor PD2, the drain D4 of the second pull-up transistor PU2, and the drain D2 of the second through-gate transistor PG2 via contacts and the first metal layer M1b. Similarly, the gate polysilicon pattern 103c shared by the second pull-up transistor PU2 and the second pull-down transistor PD2 also has branches extending towards the first pull-down transistor PD1, and is connected to the drain D5 of the first pull-down transistor PD1, the drain D3 of the first pull-up transistor PU1, and the drain D1 of the first gate transistor PG1 through contacts and the first metal layer M1a, thus achieving the effect of mutual latching of the two inverters. The intersection of the extended branch of the polysilicon pattern 103b and the first metal layer M1b between the drain D4 of the second pull-up transistor PU2 and the drain D6 of the second pull-down transistor PD2 is the second memory node SN2 of the SRAM. The intersection of the extended branch of the other polysilicon pattern 103c and the first metal layer M1a between the drain D3 of the first pull-up transistor PU1 and the drain D5 of the first pull-down transistor PD1 is the first memory node SN1 of the SRAM. The second power line S' connected to the source S5 of the first pull-down transistor PD1 and the source S6 of the second pull-down transistor PD2 can be a common power line, and the first power line S connected to the source S3 of the first pull-up transistor PU1 and the source S4 of the second pull-up transistor PU2 can be a common power line. However, the source S1 of the first through-gate transistor PG1 and the source S2 of the second through-gate transistor PG2 are respectively connected to a bit line BL and a complementary bit line BL'.

[0054] The key feature of this invention is the use of resistive random access memory (RRAM) to achieve non-volatile storage functionality from volatile static random access memory (SRAM). This is achieved by placing the RRAM between two memory nodes SN1, SN2 and their respective connected transistor drains. These RRAMs are positioned where contacts would normally be, overlapping with their connected drains, thus without increasing the required layout area. Figure 2 As shown, the first variable resistive memory R1 is located at the contact point between the drain D3 of the first pull-up transistor PU1 and the first metal layer M1a. The second variable resistive memory R2 is located at the contact point between the drain D5 of the first pull-down transistor PD1 and the first metal layer M1a. The first memory node SN1 is connected to the upper electrode of the first variable resistive memory R1 and the upper electrode of the second variable resistive memory R2 through the first metal layer M1a. The third variable resistive memory R3 is located at the contact point between the drain D4 of the second pull-up transistor PU2 and the first metal layer M1b. The fourth variable resistive memory R4 is located at the contact point between the drain D6 of the second pull-down transistor PD1 and the first metal layer M1b. The second memory node SN2 is connected to the upper electrode of the third variable resistive memory R3 and the upper electrode of the fourth variable resistive memory R4 through the first metal layer M1b.

[0055] Please refer to now. Figure 3 This is a three-dimensional schematic diagram illustrating the connection relationship between the variable resistive memory and transistors in a non-volatile static random access memory according to a preferred embodiment of the present invention, to more clearly express the configuration state of the variable resistive memory in the static random access memory. Taking the first pull-up transistor PU1 as an example, as... Figure 3As shown, the lower electrode of the first variable resistive memory R1 is connected directly above the drain D3 of the first pull-up transistor PU1 via a contact 104 (shorter than a normal contact). The upper electrode of the first variable resistive memory R1 can be connected to the upper first metal layer M1a via another shorter contact. Since the location of the first variable resistive memory R1 is the original location of the normal contact and overlaps with the drain D3 of the first pull-up transistor PU1, it does not increase the area required for layout. In this embodiment of the invention, the variable resistive memory is a unipolar variable resistive memory, and can be composed of an upper electrode, a lower electrode, and a capacitor dielectric layer between the upper electrode and the lower electrode, wherein the capacitor dielectric layer generates different resistance values ​​depending on the applied bias voltage. For example, the upper electrode can be a composite layer of titanium nitride layer 116 / titanium layer 114, the lower electrode 110 can be a titanium nitride layer, the capacitor dielectric layer 112 can be a hafnium dioxide (HfO2) layer, nickel oxide (NiO) layer, etc., or the upper and lower electrodes can be platinum (Pt) metal layers, and the capacitor dielectric layer can be a silicon oxide layer or a metal oxide layer.

[0056] After describing the structural features of the non-volatile static random access memory of the present invention, the following embodiments will describe the operation of the non-volatile static random access memory of the present invention. Figures 4 to 6 This is a circuit diagram illustrating the steps of initialization operation of a non-volatile static random access memory according to a preferred embodiment of the present invention. First, please refer to... Figure 4 In the first step of initialization, an initialization voltage V is applied from the bit line BL. F And apply a 0-volt voltage from the complementary bit line BL', the first power line S, and the second power line S', respectively. Note that the initialization voltage V described here... F In a preferred embodiment of the invention, it is configured to allow the capacitor dielectric layer (i.e., in the static random access memory) in the variable resistive memory to be... Figure 3 In section 112), the threshold voltage changes from the original insulating wire forming to a variable resistance type. When word line WL activates two pass-through gate transistors PG1 and PG2, the voltage at the first memory node SN1 will also be equal to the initialization voltage V. F The voltage at the second storage node SN2 is 0V, which causes the connected transistors PU1 and PD2 to be in the on state while transistors PD1 and PU2 are in the off state (note that in this embodiment, the pull-up transistors PU1 and PU2 are PMOS, and the pull-down transistors PD1 and PD2 are NMOS). Thus, there will be a voltage equal to the initial voltage V between the drain of the first pull-up transistor PU1 (which is in the on state) and the first storage node SN1. FThe voltage difference causes a change in the resistance of the capacitor dielectric layer in the first variable resistive memory R1 located there, changing it from a high state to a low state (H→L). Other variable resistive memories, however, remain unchanged in their stored state due to insufficient voltage difference or the transistors connected to them not being turned on.

[0057] Next refer to Figure 5 In the second step of initialization, an initialization voltage V is applied from the complementary bit line BL'. F And a voltage of 0 volts is applied from the bit line BL, the first power supply line S, and the second power supply line S', respectively. When the word line WL is turned on through the gate transistors PG1 and PG2, the voltage at the first memory node SN1 is 0V, and the voltage at the second memory node SN2 will be equal to the initialization voltage V. F This causes transistors PU2 and PD1 to be in the on state, and transistors PD2 and PU1 to be in the off state. Thus, when the second pull-up transistor PU2 is in the on state, there will be a voltage equal to the initialization voltage V between the drain of the second pull-up transistor PU2 and the second memory node SN2. F The voltage difference causes a change in the resistance of the capacitor dielectric layer in the first variable resistive memory R3 located there, changing it from a high state to a low state (H→L). Other variable resistive memories, however, remain unchanged in their stored state due to insufficient voltage difference or the transistors they are connected to not being turned on.

[0058] Next refer to Figure 6 In the third step of initialization, a voltage V equal to the initialization voltage value is applied to the bit line BL, the complementary bit line BL', and the first power supply line S, respectively. F And a 0-volt voltage is applied from the common second power line S'. When word line WL is turned on through gate transistors PG1 and PG2, the voltages at the first memory node SN1 and the second memory node SN2 will both be equal to the initialization voltage V. F This causes transistors PD1 and PD2 to be in the on state, and transistors PU1 and PU2 to be in the off state. Thus, the drains of the first pull-down transistor PD1 and the second pull-down transistor PD2, which are in the on state, will have a voltage equal to the initialization value V between them and the first memory node SN1 and the second memory node SN2 they are connected to. F The voltage difference causes the resistance of the capacitor dielectric layer in the second variable resistive memory R2 and the fourth variable resistive memory R4 located there to change from the original high state to the low state (H→L).

[0059] Through the above Figures 4 to 6In the three steps, the four variable resistive memories R1 to R4 in the static random access memory can all change from their original high state to low state (H→L), that is, the capacitor dielectric layer in them changes from the original insulating wire forming to the variable resistive initialization action.

[0060] Next Figures 7 to 9 This is a circuit diagram illustrating the steps of the clear operation of a non-volatile static random access memory (SRAM) according to a preferred embodiment of the present invention. Essentially, the clear operation of the non-volatile SRAM of the present invention is similar to the aforementioned initialization operation, except that the purpose of the clear operation is to reset all the storage states (regardless of whether they were previously written as high state H or low state L) of the variable resistive memory cells in the non-volatile SRAM to low state L, to facilitate subsequent write operations under the SRAM architecture. In this embodiment of the present invention, the initialization operation and the clear operation are the same, the difference being the clear voltage V applied during the clear operation. S Below the initial voltage V F These two operations share other identical characteristics, so they will not be elaborated upon here.

[0061] Next Figures 10 to 11 This is a circuit diagram illustrating the steps of a non-volatile static random access memory (SRAM) during the write operation according to a preferred embodiment of the present invention. The write operation of the SRAM has two modes, both starting from a variable resistive memory cell in a low state L after initialization and clearing operations. First, please refer to... Figure 10 A write voltage V is applied from the bit line BL and the second power line S', respectively. R And a voltage of 0 volts is applied from the complementary bit line BL' and the first power supply line S respectively. When the word line WL is turned on through the gate transistors PG1 and PG2, the voltage at the first memory node SN1 is V. R The voltage at the second storage node SN2 is 0V, which causes transistors PU1 and PD2 to be in the on state and transistors PD1 and PU2 to be in the off state. Thus, a write voltage V will exist between the drain of the first pull-up transistor PU1 (in the on state) and the first storage node SN1. R The voltage difference causes a change in the resistance of the capacitor dielectric layer in the first variable resistive memory R1 located at that point, transitioning it from a low state to a high state (L→H). Similarly, a write voltage V will exist between the drain of the second pull-down transistor PD2, which is in the on state, and the second memory node SN2. RThe voltage difference causes the resistance of the capacitor dielectric layer in the fourth variable resistive memory R4 located there to change from the original low state to the high state (L→H). Thus, the state in which the first variable resistive memory R1 and the fourth variable resistive memory R4 are in the high state while the second variable resistive memory R2 and the third variable resistive memory R3 are in the low state can be defined as the logic state of "0".

[0062] Please refer to Figure 11 .and Figure 10 The difference is that a write voltage V is applied from the complementary bit line BL' and the second power supply line S', respectively. R And a voltage of 0 volts is applied from the bit line BL and the first power supply line S respectively. When the word line WL is turned on through the gate transistors PG1 and PG2, the voltage at the first memory node SN1 is 0V and the voltage at the second memory node SN2 is V. R This causes transistors PU2 and PD1 to be in the on state, and transistors PD2 and PU1 to be in the off state. Thus, a write voltage V will exist between the drain of the second pull-up transistor PU2 (in the on state) and the second memory node SN2. R The voltage difference causes a change in the resistance of the capacitor dielectric layer in the third variable resistive memory R3 located at that point, transitioning it from a low state to a high state (L→H). Similarly, a write voltage V will exist between the drain of the first pull-down transistor PD1, which is in the on state, and the first memory node SN1. R The voltage difference causes the resistance of the capacitor dielectric layer in the second variable resistive memory R2 located at that location to change from the original low state to the high state (L→H). Thus, the state in which the second variable resistive memory R2 and the third variable resistive memory R3 are in the high state while the first variable resistive memory R1 and the fourth variable resistive memory R4 are in the low state can be defined as a logic state of "1".

[0063] The above initial voltage V F Clear voltage V S and write voltage V R The value of V depends on the material of the capacitor's dielectric layer, but the relationship between the three values ​​all conforms to V. F >V S >V R And all are greater than the operating voltage V. dd Taking hafnium dioxide layer as an example, its initial voltage V F Approximately 3V, clear voltage V S Approximately 2.4V, write voltage V R It is approximately 1.8V.

[0064] Please refer to the following. Figures 12 to 13 This is a circuit diagram illustrating the steps of a non-volatile static random access memory (SRAM) during a read operation according to a preferred embodiment of the present invention. During the read operation, the SRAM applies a pre-charge voltage to bit line BL and its complementary bit line BL', and determines the logic state of the SRAM by observing changes in this voltage. Please refer to [link to previous text] first. Figure 12 This refers to the case where the circuit reads the "0" logic state as defined above. For example... Figure 12 As shown, a precharge voltage (V) equal to the operating voltage is applied to bit line BL and complementary bit line BL' respectively. dd A voltage equal to the operating voltage (V) is also applied from the first power supply line S. dd A voltage of 0V is applied from the second power line S'. When the word line WL is turned on through gate transistors PG1 and PG2, since the first variable resistor memory R1 and the fourth variable resistor memory R4 are in a high resistance state (H), the voltage of the first pull-up transistor PU1 will be separated from the voltage at the first memory node SN1, and the voltage of the second pull-down transistor PD2 will be separated from the voltage at the second memory node SN2. However, since the second variable resistor memory R2 and the third variable resistor memory R3 are in a low resistance state (L), the voltage of the first pull-down transistor PD1 will be connected to the voltage at the first memory node SN1 via the second variable resistor memory R2, and the voltage of the second pull-up transistor PU2 will be connected to the voltage at the second memory node SN2 via the third variable resistor memory R3. This causes the precharge voltage applied from the bit line BL to the first memory node SN1 to become 0 via the first pull-down transistor PD1 to ground, and the precharge voltage applied from the complementary bit line BL' to the second memory node SN2 to be connected to a voltage of V via the second pull-up transistor PU2. dd The first power line S remains unchanged. Thus, it can be defined that during read operation, the voltage of bit line BL becomes 0V while the voltage of the complementary bit line BL' remains at V. dd The result is that the logic state "0" of the static random access memory was read.

[0065] On the other hand, such as Figure 13 As shown, when reading the aforementioned "1" logic state circuit, a precharge voltage (V) equal to the operating voltage is applied to both bit line BL and complementary bit line BL'. dd A voltage equal to the operating voltage (V) is also applied from the first power supply line S. ddA 0V voltage is applied from the second power line S'. When the word line WL is turned on through gate transistors PG1 and PG2, since the second variable resistor memory R2 and the third variable resistor memory R3 are in a high-resistance state (H), the voltage of the second pull-up transistor PU2 will be separated from the voltage at the second memory node SN2, and the voltage of the first pull-down transistor PD1 will be separated from the voltage at the first memory node SN1. However, since the first variable resistor memory R1 and the fourth variable resistor memory R4 are in a low-resistance state (L), the voltage of the first pull-up transistor PU1 will be connected to the voltage at the first memory node SN1 via the first variable resistor memory R1, and the voltage of the second pull-down transistor PD2 will be connected to the voltage at the second memory node SN2 via the fourth variable resistor memory R4. This results in the precharge voltage applied from the bit line BL to the first memory node SN1 being connected to a voltage of V via the first pull-up transistor PU1. dd The first power line S remains unchanged, while the precharge voltage applied from the complementary bit line BL' to the second memory node SN2 becomes 0 via the second pull-down transistor PD2 to ground. Thus, the voltage of bit line BL can be defined as V during read operations. dd The result of the voltage of the complementary bit line BL' becoming 0V is that the logic state "1" is read.

[0066] In addition to the aforementioned advantages of achieving non-volatile storage and requiring no additional layout area, the circuit design described above can also enhance memory reliability. For example, please refer to... Figure 12 Suppose that the fourth variable resistor memory R4 has abnormal variable resistor properties due to variations in its manufacturing process, preventing it from transitioning to a fully high state during write operations. In such cases, during read operations, the pre-charge voltage applied from the complementary bit line BL' to the second memory node SN2 might be grounded via the fourth variable resistor memory R4, causing a voltage drop in the complementary bit line BL' and potentially leading to read errors. In this embodiment of the invention, if such a situation occurs, the dropped pre-charge voltage at the complementary bit line BL' can be mitigated by the voltage (V) of the connected first power line S. dd Compensation is provided to maintain it at the original pre-charge voltage (V). dd One of its advantages is that it is located near the target area, which prevents read errors from occurring.

[0067] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A non-volatile static random access memory, comprising: A first gate transistor has a first gate, a first source, and a first drain, wherein the first source is connected to a bit line and the first gate is connected to a word line; The second pass-gate transistor has a second gate, a second source, and a second drain, wherein the second source is connected to a complementary bit line, and the second gate is connected to the word line; The first pull-up transistor has a third gate, a third source, and a third drain, wherein the third source is connected to a common first power supply line; The second pull-up transistor has a fourth gate, a fourth source, and a fourth drain, wherein the fourth source is connected to the common first power line; The first pull-down transistor has a fifth gate, a fifth source, and a fifth drain, wherein the fifth source is connected to a common second power supply line; as well as The second pull-down transistor has a sixth gate, a sixth source, and a sixth drain, wherein the sixth source is connected to the common second power supply line; The first drain, the fourth gate, and the sixth gate are connected to the first memory node, the second drain, the third gate, and the fifth gate are connected to the second memory node, and a first variable resistive memory is provided between the first memory node and the third drain, a second variable resistive memory is provided between the first memory node and the fifth drain, a third variable resistive memory is provided between the second memory node and the fourth drain, and a fourth variable resistive memory is provided between the second memory node and the sixth drain. When the common first power line and the common second power line are performing initialization operation, clear operation, write operation, and read operation, an initialization voltage, a clear voltage, a write voltage, and an operating voltage are respectively applied, and the initialization voltage, the clear voltage, and the write voltage are all greater than the operating voltage. The initialization voltage is greater than the clear voltage, and the clear voltage is greater than the write voltage.

2. The non-volatile static random access memory as claimed in claim 1, wherein the first variable resistive memory, the second variable resistive memory, the third variable resistive memory, and the fourth variable resistive memory are disposed between the connected drain and the first metal layer, the first variable resistive memory overlaps with the third drain, the second variable resistive memory overlaps with the fifth drain, the third variable resistive memory overlaps with the fourth drain, and the fourth variable resistive memory overlaps with the sixth drain.

3. The non-volatile static random access memory as claimed in claim 2, wherein each of the variable resistive memory includes an upper electrode, a lower electrode, and a capacitor dielectric layer between the upper electrode and the lower electrode, the upper electrodes of the first variable resistive memory and the second variable resistive memory are connected to the first storage node through the first metal layer, and the upper electrodes of the third variable resistive memory and the fourth variable resistive memory are connected to the second storage node through the first metal layer.

4. The non-volatile static random access memory as described in claim 3, wherein the upper electrode is a titanium nitride / titanium composite layer, the lower electrode is a titanium nitride layer, and the capacitor dielectric layer is a hafnium dioxide layer.

5. The non-volatile static random access memory as claimed in claim 1, wherein the third gate and the fifth gate are of the same polysilicon pattern and are respectively connected to the fourth drain and the sixth drain through the third variable resistive memory and the fourth variable resistive memory, and the fourth gate and the sixth gate are of the same polysilicon pattern and are respectively connected to the third drain and the fifth drain through the first variable resistive memory and the second variable resistive memory.

6. The non-volatile static random access memory as claimed in claim 1, wherein the first gate and the second gate are of the same polysilicon pattern and are connected to the word line, the word line being located in the first metal layer.

7. The non-volatile static random access memory as claimed in claim 1, wherein the active regions of the first through-gate transistor, the first pull-down transistor, the second through-gate transistor, and the second pull-down transistor have a first doping type, and the active regions of the first pull-up transistor and the second pull-up transistor have a second doping type.

8. The non-volatile static random access memory of claim 7, wherein the active regions are each independent and unconnected to each other.

9. The non-volatile static random access memory of claim 1, wherein the bit line and the complementary bit line are located in a second metal layer.

10. The non-volatile static random access memory as claimed in claim 1, wherein the initialization operation of the non-volatile static random access memory comprises: The initialization voltage is applied to the bit line, a voltage of 0 volts is applied to the complementary bit line, and a voltage of 0 volts is applied to the common first power line and the common second power line respectively, thereby causing the first variable resistive memory to change from a high state to a low state. Applying a 0-volt voltage to the bit line, applying the initialization voltage to the complementary bit line, and applying 0-volt voltages to both the common first power line and the common second power line, thereby causing the third variable resistive memory to transition from a high state to a low state; and The initialization voltage is applied from the bit line, the complementary bit line, and the common first power line, and a voltage of 0 volts is applied from the common second power line, thereby causing the second variable resistive memory and the fourth variable resistive memory to switch from a high state to a low state.

11. The non-volatile static random access memory as claimed in claim 1, wherein the clearing operation of the non-volatile static random access memory comprises: The clear voltage is applied to the bit line, a voltage of 0 volts is applied to the complementary bit line, and a voltage of 0 volts is applied to the common first power line and the common second power line respectively, thereby causing the first variable resistive memory to change from a high state to a low state. Applying a 0-volt voltage to the bit line, applying the clear voltage to the complementary bit line, and applying 0-volt voltages to both the common first power line and the common second power line, thereby causing the third variable resistive memory to transition from a high state to a low state; and The clear voltage is applied from the bit line, the complementary bit line, and the common first power line, and a 0-volt voltage is applied from the common second power line, thereby causing the second variable resistive memory and the fourth variable resistive memory to change from a high state to a low state.

12. The non-volatile static random access memory as claimed in claim 1, wherein the write operation of the non-volatile static random access memory comprises: The write voltage is applied from the bit line, a 0-volt voltage is applied from the complementary bit line, a 0-volt voltage is applied from the common first power line, and the write voltage is applied from the common second power line, thereby causing the first variable resistive memory and the fourth variable resistive memory to change from a low state to a high state.

13. The non-volatile static random access memory as claimed in claim 1, wherein the write operation of the non-volatile static random access memory comprises: Applying a 0-volt voltage to the bit line, applying the write voltage to the complementary bit line, applying a 0-volt voltage to the common first power line, and applying the write voltage to the common second power line, thereby causing the second variable resistive memory and the third variable resistive memory to transition from a low state to a high state.

14. The non-volatile static random access memory as claimed in claim 1, wherein the read operation of the non-volatile static random access memory comprises: A precharge voltage is applied from the bit line and the complementary bit line, the operating voltage is applied from the common first power line, and a 0-volt voltage is applied from the second power line.

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