Memory device and method of operating the same

Abstract

The present disclosure relates to a memory device and a method of operating the memory device. According to one embodiment of the present disclosure, the memory device includes a peripheral circuit configured to perform a program operation including a plurality of program loops, and control logic configured to, in some of the plurality of loops of the program operation, control the peripheral circuit to apply a program voltage to a selected word line, apply a first pass voltage to an adjacent word line adjacent to the selected word line, and then apply a second pass voltage to the adjacent word line at a predetermined time point, wherein the second pass voltage has a different magnitude compared to the first pass voltage, and the control logic is configured to, in the remaining of the plurality of loops of the program operation, control the peripheral circuit to apply the second pass voltage to the adjacent word line at a time point different from the predetermined time point from the selected loop.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2022-0017783, filed on February 10, 2022, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to electronic devices, and more specifically, to memory devices and methods of operating such memory devices. Background Technology

[0004] A storage device is a device that stores data under the control of a host device such as a computer or smartphone. A storage device may include a memory device that stores data therein and a memory controller that controls the memory device. Memory devices are classified as volatile memory devices and non-volatile memory devices.

[0005] Volatile memory devices are devices that store data only while power is supplied and lose the stored data when power is cut off. Volatile memory devices include static random access memory (SRAM), dynamic random access memory (DRAM), etc.

[0006] Non-volatile memory devices are devices that do not lose data even when power is cut off. Non-volatile memory devices include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable and programmable ROM (EEPROM), flash memory, etc. Summary of the Invention

[0007] According to one embodiment of this disclosure, a memory device may include: a plurality of memory cells connected to each of a plurality of word lines; peripheral circuitry configured to perform a programming operation on the memory cells connected to a selected word line of the plurality of word lines, the programming operation including a plurality of programming cycles; and control logic configured to, in some of the plurality of programming cycles, control the peripheral circuitry to apply a programming voltage to the selected word line, apply a first through voltage to an adjacent word line adjacent to the selected word line, and then apply a second through voltage to the adjacent word line at a predetermined time point, wherein the second through voltage has a different magnitude compared to the first through voltage, and the control logic may be configured to, in the remaining cycles of the plurality of programming cycles, control the peripheral circuitry to apply the second through voltage to the adjacent word line at a time point different from the predetermined time point.

[0008] According to one embodiment, from the first cycle of a plurality of programming cycles to the selected cycle, a first time for which a first through voltage is applied to an adjacent word line is longer than a second time for which a second through voltage is applied to an adjacent word line, and from the selected cycle to the last cycle of the plurality of programming cycles, the second time is longer than the first time.

[0009] According to one embodiment, the control logic is configured to apply a programming voltage with a predetermined step voltage to a selected word line as the programming cycle in a plurality of programming cycles increases during programming operations. As the programming cycle in the plurality of programming cycles increases, the amplitude of the second voltage increases the predetermined step voltage.

[0010] According to one embodiment, the magnitude of the first through voltage is the minimum voltage used to form a channel through which current flows between the source and drain regions of a plurality of memory cells connected to adjacent word lines.

[0011] According to one embodiment of the present disclosure, a memory device may include: a plurality of memory cells connected to each of a plurality of word lines; peripheral circuitry configured to perform a programming operation on the memory cells connected to a selected word line of the plurality of word lines, the programming operation including a plurality of programming cycles; and control logic configured to, in some of the cycles of the plurality of programming operations, control the peripheral circuitry to apply a programming voltage to the selected word line and to apply a through voltage that increases at two or more time points to adjacent word lines adjacent to the selected word line, and the control logic may be configured to, in the remaining cycles of the plurality of programming operations, control the peripheral circuitry to apply a through voltage that increases at a time point different from the two or more time points at which the through voltage increases in some of the cycles of the plurality of cycles to adjacent word lines.

[0012] According to one embodiment, from the first cycle to the selected cycle, the duration for which the amplitude of the through voltage is maintained after an increase at the first time point among two or more time points is longer than the duration for which the amplitude of the through voltage is maintained after an increase at the last time point among two or more time points. From the selected cycle to the last cycle, the duration for which the amplitude of the through voltage is maintained after an increase at the first time point is shorter than the duration for which the amplitude of the through voltage is maintained after an increase at the last time point.

[0013] According to one embodiment, a predetermined step voltage is increased at each of two or more time points by means of voltage.

[0014] According to one embodiment of this disclosure, a method of operating a memory device (the memory device performing a programming operation on memory cells connected to a selected word line among a plurality of word lines, the programming operation including a plurality of programming cycles) may include: applying a programming voltage to the selected word line, and simultaneously applying a pass voltage to an adjacent word line adjacent to the selected word line, wherein in some of the plurality of programming cycles, applying the pass voltage to the adjacent word line may include: applying a first pass voltage to the adjacent word line, and then applying a second pass voltage to the adjacent word line at a predetermined time point, wherein the magnitude of the second pass voltage is different from the magnitude of the first pass voltage, and wherein in the remaining of the plurality of programming cycles, the second pass voltage may be applied to the adjacent word line at a time point different from the predetermined time point.

[0015] According to one embodiment, from the first cycle of a plurality of programming cycles to the selected cycle, a first time for which a first through voltage is applied to an adjacent word line is longer than a second time for which a second through voltage is applied to an adjacent word line, and from the selected cycle to the last cycle of the plurality of programming cycles, the second time is longer than the first time.

[0016] According to one embodiment, the magnitude of the first through voltage is the minimum voltage used to form a channel through which current flows between the source and drain regions of a plurality of memory cells connected to adjacent word lines. Attached Figure Description

[0017] Figure 1 This is a diagram illustrating a storage device according to one embodiment.

[0018] Figure 2 It's a diagram. Figure 1 A diagram of the structure of a memory device.

[0019] Figure 3 It's a diagram. Figure 2 A diagram of one embodiment of a memory cell array.

[0020] Figure 4 It's a diagram. Figure 2 The circuit diagram of any one of the memory blocks BLKa from BLK1 to BLKz.

[0021] Figure 5 It's a diagram. Figure 2 A circuit diagram of another embodiment of memory block BLKb among memory blocks BLK1 to BLKz.

[0022] Figure 6 This is a diagram illustrating an example of interference between adjacent memory cells.

[0023] Figures 7A-7C It is a diagram illustrating the charge distribution trapped inside the floating gate of a programmed memory cell.

[0024] Figure 8 This is a diagram illustrating programming operations according to one embodiment.

[0025] Figure 9 It's a diagram. Figure 2 A circuit diagram of another embodiment of memory block BLKc among memory blocks BLK1 to BLKz.

[0026] Figure 10 It is a diagram illustrating the voltage applied to the selected word line and the word lines adjacent to the selected word line during programming operations.

[0027] Figure 11 It is a timing diagram illustrating the voltage applied to the selected word line and the word lines adjacent to the selected word line during a programming operation.

[0028] Figure 12 It is a diagram illustrating the timing of applying a second through voltage in each segment of the programming operation according to one embodiment.

[0029] Figure 13 It is a diagram illustrating the timing of applying a second through voltage in each segment of the programming operation according to another embodiment.

[0030] Figure 14 It is a diagram illustrating the timing of applying the second and third through voltages in each segment of the programming operation according to another embodiment.

[0031] Figure 15 This is a flowchart illustrating the operation of a memory device according to one embodiment.

[0032] Figure 16 It's a diagram. Figure 1 A diagram of another embodiment of the memory controller.

[0033] Figure 17 This is a block diagram illustrating a memory card system, to which a storage device according to an embodiment of the present disclosure is applied in the memory card system.

[0034] Figure 18 This is a block diagram illustrating a solid-state drive (SSD) system, to which a storage device according to an embodiment of the present disclosure is applied according to an SSD system.

[0035] Figure 19 This is a block diagram illustrating a user system, in which a storage device according to an embodiment of the present disclosure is applied. Detailed Implementation

[0036] The specific structural or functional descriptions of embodiments based on the concepts disclosed in this specification or application are merely illustrative to describe embodiments based on the concepts of this disclosure. Embodiments based on the concepts of this disclosure may be implemented in various forms and should not be construed as limited to the embodiments described in this specification or application.

[0037] Hereinafter, the present disclosure will be described in detail with reference to the accompanying drawings, which illustrate preferred embodiments of the present disclosure.

[0038] Embodiments of this disclosure provide a memory device in which threshold voltage distribution degradation caused by interference between adjacent memory cells is improved.

[0039] According to the present technology, a memory device is provided in which the degradation of threshold voltage distribution caused by interference between adjacent memory cells is improved.

[0040] Figure 1 This is a diagram illustrating a storage device according to one embodiment.

[0041] refer to Figure 1 Storage device 50 may include memory device 100 and memory controller 200 for controlling the operation of memory device. Storage device 50 is a device that stores data based on instructions from a host, such as a cellular phone, smartphone, MP3 player, laptop computer, desktop computer, game console, TV, tablet PC, or in-vehicle infotainment system.

[0042] Depending on the host interface, which serves as the method of communication with the host, storage device 50 can be manufactured as one of various types of storage devices. For example, storage device 50 can be configured as any of various types of storage devices, such as SSDs, multimedia cards (in the form of MMC, eMMC, RS-MMC, and micro MMC), secure digital cards (in the form of SD, mini SD, and micro SD), universal serial bus (USB) storage devices, universal flash storage (UFS) devices, PCMCIA card type storage devices, peripheral component interconnect (PCI) card type storage devices, PCI Express (PCI-E) card type storage devices, compact flash (CF) cards, smart media cards, and memory sticks.

[0043] The storage device 50 can be manufactured in any of the various types of packages, such as stacked package (POP), system-in-package (SIP), system-on-chip (SOC), multi-chip package (MCP), chip-on-board (COB), wafer-level fabrication package (WFP), and wafer-level stacked package (WSP).

[0044] Memory device 100 can store data. Memory device 100 can operate based on instructions from memory controller 200. Memory device 100 may include a memory cell array, which includes a plurality of memory cells for storing data. The memory cell array may include a plurality of memory blocks. Each memory block may include a plurality of memory cells. A memory block may include a plurality of pages. In one embodiment, a page may be a unit for storing data in memory device 100 or retrieving data stored in memory device 100. A memory block may be a unit for erasing data. In one embodiment, the memory device 100 may be a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), a Low Power Double Data Rate 4 (LPDDR4) SDRAM, a Graphics Double Data Rate (GDDR) SDRAM, a Low Power DDR (LPDDR), a Rambus Dynamic Random Access Memory (RDRAM), a NAND flash memory, a Vertical NAND flash memory, a NOR flash memory, a Resistive Random Access Memory (RRAM), a Phase Change Random Access Memory (PRAM), a Magnetoresistive Random Access Memory (MRAM), a Ferroelectric Random Access Memory (FRAM), a Spin-Torque Random Access Memory (STT-RAM), etc. In this specification, for ease of description, it is assumed that the memory device 100 is a NAND flash memory.

[0045] Memory device 100 can be configured to receive commands and addresses from memory controller 200 and access address-selected regions of the memory cell array. That is, memory device 100 can perform operations as commands on the address-selected regions. For example, memory device 100 can perform write operations (programming operations), read operations, and erase operations. During a programming operation, memory device 100 can program data into the address-selected region. During a read operation, memory device 100 can read data from the address-selected region. During an erase operation, memory device 100 can erase data stored in the address-selected region.

[0046] In one embodiment, memory device 100 may receive programming commands, data, and addresses from memory controller 200. Memory device 100 may program data into a region selected by the address received from memory controller 200 in response to the programming command received from memory controller 200. Memory device 100 may apply a programming voltage to a selected word line during the selected programming operation. Simultaneously with the programming voltage applied to the selected word line, memory device 100 may apply a pass voltage to an adjacent word line adjacent to the selected word line. The pass voltage applied to the adjacent word line may be formed in at least two or more steps. For example, while the programming voltage is applied to the selected word line, a first pass voltage may be applied to the adjacent word line, and then a second pass voltage with a different amplitude compared to the first pass voltage may be applied at a predetermined time point. The amplitude of the second pass voltage may be greater than the amplitude of the first pass voltage.

[0047] The memory controller 200 can control the overall operation of the storage device 50.

[0048] When power is applied to storage device 50, memory controller 200 may execute firmware (FW). When storage device 100 is a flash memory device, memory controller 200 may operate firmware such as flash translation layer (FTL) to control communication between the host and storage device 100.

[0049] In one embodiment, the memory controller 200 may receive data and logical block addresses (LBAs) from a host and translate the LBAs into physical block addresses (PBAs), which indicate the addresses of memory cells in which data included in the memory device 100 is to be stored.

[0050] The memory controller 200 can control the memory device 100 to perform programming, reading, or erasing operations in response to a request from the host. During a programming operation, the memory controller 200 can provide the memory device 100 with programming commands, a PBA, and data. During a reading operation, the memory controller 200 can provide the memory device 100 with reading commands and a PBA. During an erasing operation, the memory controller 200 can provide the memory device 100 with erasing commands and a PBA.

[0051] In one embodiment, memory controller 200 may generate programming commands, addresses, and data, and transmit these commands, addresses, and data to memory device 100 without a request from the host. For example, memory controller 200 may provide commands, addresses, and data to memory device 100 to perform background operations such as programming operations for wear leveling and programming operations for garbage collection.

[0052] In one embodiment, the memory controller 200 can control at least two memory devices 100. In this case, the memory controller 200 can control the memory devices 100 according to an interleaving method to improve operational performance.

[0053] The host can communicate with the storage device 50 using at least one of a variety of communication methods, such as Universal Serial Bus (USB), Serial AT Attachment (SATA), Serial Attached SCSI (SAS), High Speed ​​Chip Interconnect (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), PCIe, Non-Volatile Memory Fast (NVMe), Universal Flash Storage (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Load-Away DIMM (LRDIMM).

[0054] Figure 2 It's a diagram. Figure 1 A diagram of the structure of a memory device.

[0055] refer to Figure 2 The memory device 100 may include a memory cell array 110, peripheral circuitry 120, and control logic 130.

[0056] The memory cell array 110 may include multiple memory blocks BLK1 to BLKz. The multiple memory blocks BLK1 to BLKz can be connected to the row decoder 121 via row lines RL. The multiple memory blocks BLK1 to BLKz can be connected to the read and write circuitry 123 via bit lines BL1 to BLm. Each memory block among the multiple memory blocks BLK1 to BLKz may include multiple memory cells. In one embodiment, the multiple memory cells may be non-volatile memory cells. Memory cells connected to the same word line among the multiple memory cells can be defined as a physical page. That is, the memory cell array 110 can be configured with multiple pages.

[0057] Each memory cell in the memory cell of the memory device 100 can be configured as: a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a three-level cell (TLC) storing three data bits, or a four-level cell (QLC) storing four data bits.

[0058] The peripheral circuitry 120 may include a line decoder 121, a voltage generator 122, a read and write circuit 123, a data input / output circuit 124, and a sensing circuit 125.

[0059] The peripheral circuitry 120 can drive the memory cell array 110. For example, the peripheral circuitry 120 can drive the memory cell array 110 to perform programming operations, reading operations, and erasing operations.

[0060] The row decoder 121 can be connected to the memory cell array 110 via row lines RL. The row lines RL may include at least one source select line, multiple word lines, and at least one drain select line. In one embodiment, the word lines may include normal word lines and dummy word lines.

[0061] The row decoder 121 can be configured to decode the row address RADD received from the control logic 130. The row decoder 121 can select at least one memory block from memory blocks BLK1 to BLKz based on the decoded address. Furthermore, the row decoder 121 can select at least one word line of the selected memory block based on the decoded address to apply the voltage generated by the voltage generator 122 to that at least one word line.

[0062] For example, during a programming operation, the line decoder 121 can apply a programming voltage to the selected word line and a programming pass voltage to the unselected word line, the programming pass voltage having a lower voltage level than the programming voltage. During a programming verification operation, the line decoder 121 can apply a verification voltage to the selected word line and a verification pass voltage to the unselected word line, the verification pass voltage having a higher voltage level than the verification voltage. During a reading operation, the line decoder 121 can apply a read voltage to the selected word line and a read pass voltage to the unselected word line, the read pass voltage having a higher voltage level than the read voltage.

[0063] In one embodiment, the erase operation of the memory device 100 can be performed on a block-by-block basis. During the erase operation, the row decoder 121 can select a memory block based on the decoded address. During the erase operation, the row decoder 121 can apply a ground voltage to the word line connected to the selected memory block.

[0064] During a read operation, the line decoder 121 can apply a read voltage to the selected word line and a read pass voltage to the unselected word line, the read pass voltage having a higher voltage level than the read voltage.

[0065] According to one embodiment, the erase operation of memory device 100 can be performed on a block-by-block basis. The address ADDR input to memory device 100 during the erase operation may include a block address. Row decoder 121 can decode the block address and select a memory block based on the decoded block address. During the erase operation, row decoder 121 can apply a ground voltage to the word lines input to the selected memory block.

[0066] Voltage generator 122 can be configured to generate multiple voltages using an external power supply voltage supplied to memory device 100. Voltage generator 122 can operate in response to control logic 130.

[0067] In one embodiment, voltage generator 122 can generate an internal power supply voltage by adjusting an external power supply voltage. The internal power supply voltage generated by voltage generator 122 can be used as the operating voltage of memory device 100.

[0068] In one embodiment, voltage generator 122 can generate multiple voltages for use with an external power supply voltage or an internal power supply voltage. Voltage generator 122 can be configured to generate various voltages required by memory device 100. For example, voltage generator 122 can generate multiple erase voltages, multiple programming voltages, multiple pass voltages, multiple select read voltages, and multiple unselect read voltages.

[0069] In order to generate multiple voltages with various voltage levels, voltage generator 122 may include multiple pump capacitors that receive internal voltages, and voltage generator 122 may selectively activate the multiple pump capacitors in response to control logic 130 to generate multiple voltages.

[0070] The generated voltages can be supplied to the memory cell array 110 via the row decoder 121.

[0071] The read and write circuitry 123 may include first page buffers PB1 through m-th page buffers PBm. First page buffers PB1 through m-th page buffers PBm may be connected to the memory cell array 110 via first bit lines BL1 through m-th bit lines BLm, respectively. First page buffers PB1 through m-th page buffers PBm may operate in response to control logic 130.

[0072] Page buffers PB1 through PBm can communicate with the data input / output circuit 124 by outputting and receiving data DATA from the data input / output circuit 124. During programming operations, page buffers PB1 through PBm can receive the data DATA to be stored in them through the data input / output circuit 124 and the data line DL.

[0073] During programming operations, when a programming pulse is applied to the selected word line, the first page buffer PB1 to the m-th page buffer PBm can transfer data DATA received through the data input / output circuit 124 to the selected memory cell via bit lines BL1 to BLm. The memory cell of the selected page can be programmed according to the transferred data DATA. Memory cells connected to bit lines to which a programming enable voltage (e.g., ground voltage) is applied can have an increased threshold voltage. The threshold voltage of memory cells connected to bit lines to which a programming disable voltage (e.g., power supply voltage) is applied can be maintained. During programming verification operations, the first page buffer PB1 to the m-th page buffer PBm can read the data DATA stored in the memory cell from the selected memory cell via bit lines BL1 to BLm.

[0074] During a read operation, the read and write circuit 123 can read data DATA from the memory cell of the selected page via bit lines BL1 to BLm, and can store the read data DATA in the first page buffer PB1 to the m-th page buffer PBm.

[0075] During the erase operation, the read and write circuitry 123 can float bit lines BL1 to BLm. In one embodiment, the read and write circuitry 123 may include column select circuitry.

[0076] The data input / output circuit 124 can be connected to the first page buffer PB1 to the m-th page buffer PBm via the data line DL. The data input / output circuit 124 can operate in response to the control logic 130.

[0077] The data input / output circuit 124 may include multiple input / output buffers (not shown) for receiving input data DATA. During programming operations, the data input / output circuit 124 may receive data DATA from an external controller (not shown). During read operations, the data input / output circuit 124 may output data DATA to the external controller, which is transmitted from the first page buffer PB1 to the m-th page buffer PBm included in the read and write circuit 123.

[0078] During a read or verification operation, the sensing circuit 125 may generate a reference current in response to the signal of the enable bit VRYBIT generated by the control logic 130, and may compare the sensed voltage VPB received from the read and write circuit 123 with the reference voltage generated by the reference current to output a pass signal PASS or a failure signal FAIL to the control logic 130.

[0079] In one embodiment, the sensing circuit 125 may include a current sensing circuit that counts the number of failure bits, which is the number of programming failure units in the target unit.

[0080] Control logic 130 can be connected to line decoder 121, voltage generator 122, read and write circuitry 123, data input / output circuitry 124, and sensing circuitry 125. Control logic 130 can be configured to control all operations of memory device 100. Control logic 130 can operate in response to commands (CMD) transmitted from external devices.

[0081] Control logic 130 can generate various signals in response to command CMD and address ADDR to control peripheral circuitry 120. For example, control logic 130 can generate operation signal OPSIG, row address RADD, read and write circuit control signal PBSIGNALS, and enable bit VRYBIT in response to command CMD and address ADDR. Control logic 130 can output operation signal OPSIG to voltage generator 122, row address RADD to row decoder 121, read and write circuit control signal PBSIGNALS to read and write circuit 123, and enable bit VRYBIT to sensing circuit 125. Furthermore, control logic 130 can determine whether the verification operation has passed or failed in response to pass signal PASS or failure signal FAIL output by sensing circuit 126.

[0082] In one embodiment, control logic 130 may receive a programming command from a memory controller. In response to the programming command received from the memory controller, control logic 130 may control peripheral circuitry 120 such that memory device 100 performs a programming operation on memory cells connected to selected word lines, the programming operation comprising multiple programming cycles. Control logic 130 may apply a programming voltage to the selected word line in each cycle of the programming operation. In some cycles of the programming operation, control logic 130 may apply a first through voltage to an adjacent word line adjacent to the selected word line, and then, at a predetermined time point, apply a second through voltage of a different magnitude than the first through voltage. In the remaining cycles of the programming operation, control logic 130 may control the peripheral circuitry to apply the second through voltage to the adjacent word line at a time point different from the predetermined time point. In other words, based on the selected cycle, the first through voltage may be applied in cycles preceding the selected cycle, and the second through voltage may be applied at a different time compared to cycles following the selected cycle.

[0083] Figure 3 It's a diagram. Figure 2 A diagram of one embodiment of a memory cell array.

[0084] refer to Figure 3 The memory cell array 110 may include multiple memory blocks BLK1 to BLKz. Each memory block may have a three-dimensional structure. Each memory block may include multiple memory cells stacked on a substrate. Such multiple memory cells may be arranged along the +X, +Y, and +Z directions. (Reference) Figure 4 The structure of each memory block is described in more detail.

[0085] Figure 4 It's a diagram. Figure 2 The circuit diagram of any one of the memory blocks BLKa from BLK1 to BLKz.

[0086] refer to Figure 4 The memory block BLKa may include multiple cell strings CS11 to CS1m and CS21 to CS2m. In one embodiment, each of the multiple cell strings CS11 to CS1m and CS21 to CS2m may be formed in a "U" shape. In the memory block BLKa, m cell strings may be arranged in the row direction (i.e., the +X direction). Figure 4 In this context, two unit strings can be arranged in the column direction (i.e., the +Y direction). However, this is for ease of description, and it can be understood that three or more unit strings can be arranged in the column direction.

[0087] Each of the multiple cell strings CS11 to CS1m and CS21 to CS2m may include at least one source selection transistor SST, a first memory cell MC1 to the nth memory cell MCn, a pipe transistor PT, and at least one drain selection transistor DST.

[0088] The selector transistors SST and DST, and each of the memory cells MC1 to MCn, may have similar structures. In one embodiment, each of the selector transistors SST and DST, and each of the memory cells MC1 to MCn, may include a channel layer, a tunneling insulating film, a charge storage film, and a barrier insulating film. In one embodiment, a pillar for providing the channel layer may be provided in each cell string. In another embodiment, a pillar may be provided in each cell string for providing at least one of the channel layer, the tunneling insulating film, the charge storage film, and the barrier insulating film.

[0089] The source selection transistor SST of each cell string can be connected between the common source line CSL and memory cells MC1 to MCp.

[0090] In one embodiment, source-select transistors of cell strings arranged in the same row can be connected to source-select lines extending in the row direction, and source-select transistors of cell strings arranged in different rows can be connected to different source-select lines. Figure 4 In the first row, the source selection transistors CS11 to CS1m can be connected to the first source selection line SSL1. The source selection transistors CS21 to CS2m in the second row can be connected to the second source selection line SSL2.

[0091] In another embodiment, the source selection transistors of cell strings CS11 to CS1m and CS21 to CS2m can be connected together to a single source selection line.

[0092] The first memory cell MC1 to the nth memory cell MCn of each cell string can be connected between the source selection transistor SST and the drain selection transistor DST.

[0093] The first memory cells MC1 to the nth memory cell MCn can be divided into first memory cells MC1 to the pth memory cell MCp, and the (p+1)th memory cells MCp+1 to the nth memory cell MCn. The first memory cells MC1 to the pth memory cell MCp can be arranged sequentially in the direction opposite to the +Z direction, and can be connected in series between the source selection transistor SST and the channel transistor PT. The (p+1)th memory cells MCp+1 to the nth memory cell MCn can be arranged sequentially in the +Z direction, and can be connected in series between the channel transistor PT and the drain selection transistor DST. The first memory cells MC1 to the pth memory cell MCp and the (p+1)th memory cells MCp+1 to the nth memory cell MCn can be connected to each other via the channel transistor PT. The gates of the first memory cells MC1 to the nth memory cell MCn in each cell string can be connected to the first word line WL1 to the nth word line WLn, respectively.

[0094] The gate of the pipe transistor PT in each cell string can be connected to the pipe line PL.

[0095] The drain select transistor (DST) of each cell string can be connected between the corresponding bit line and memory cells MCp+1 to MCn. Cell strings arranged in the row direction can be connected to drain select lines extending in the row direction. The drain select transistors of cell strings CS11 to CS1m in the first row can be connected to the first drain select line DSL1. The drain select transistors of cell strings CS21 to CS2m in the second row can be connected to the second drain select line DSL2.

[0096] A string of cells arranged in the column direction can be connected to a bit line extending in the column direction. Figure 4In the diagram, the cell strings CS11 and CS21 in the first column can be connected to the first bit line BL1. The cell strings CS1m and CS2m in the m-th column can be connected to the m-th bit line BLm.

[0097] Memory cells connected to the same word line in a cell string arranged in a row direction are configured as a page. For example, memory cells in cell strings CS11 to CS1m in the first row that are connected to the first word line WL1 can be configured as a page. Memory cells in cell strings CS21 to CS2m in the second row that are connected to the first word line WL1 can be configured as another page. A cell string arranged in a row direction can be selected by selecting either the drain select line DSL1 or DSL2. A page of the selected cell string can be selected by selecting any one of the word lines WL1 to WLn.

[0098] Figure 5 It's a diagram. Figure 2 A circuit diagram of another embodiment of memory block BLKb among memory blocks BLK1 to BLKz.

[0099] In another embodiment, even-numbered bit lines and odd-numbered bit lines can be provided to replace the first bit line BL1 to the m-th bit line BLm. Furthermore, even-numbered cell strings arranged in the row direction CS11 to CS1m or CS21 to CS2m can be connected to the even-numbered bit lines, and odd-numbered cell strings arranged in the row direction CS11 to CS1m or CS21 to CS2m can be connected to the odd-numbered bit lines.

[0100] In one embodiment, at least one of the first memory cells MC1 to the nth memory cell MCn can be used as a dummy memory cell. For example, at least one dummy memory cell can be provided to reduce the electric field between the source selection transistor SST and the memory cells MC1 to MCp. Alternatively, at least one dummy memory cell can be provided to reduce the electric field between the drain selection transistor DST and the memory cells MCp+1 to MCn. While providing more dummy memory cells can improve the reliability of operation on the memory block BLKb, it also increases the size of the memory block BLKb. Conversely, while providing fewer memory cells can reduce the size of the memory block BLKb, it may reduce the reliability of operation on the memory block BLKb.

[0101] To efficiently control at least one dummy memory cell, each dummy memory cell can have a required threshold voltage. Programming operations can be performed on all or some of the dummy memory cells before or after an erase operation on the memory block BLKb. When an erase operation is performed after a programming operation, the dummy memory cell can have the required threshold voltage by controlling the voltage applied to the dummy word line connected to the corresponding dummy memory cell.

[0102] Figure 6 This is a diagram illustrating an example of interference between adjacent memory cells.

[0103] refer to Figure 6 When multiple programmed memory cells are adjacent to each other, the threshold voltage of the memory cells may shift due to interference between adjacent memory cells. (Reference) Figure 6 As an example, a first memory cell MC1, a second memory cell MC2, and a third memory cell MC3 can be connected in a string. In this case, the threshold voltage of the first memory cell MC1 may shift due to interference from the second memory cell MC2. The threshold voltage of the second memory cell MC2 may shift due to interference from either the first memory cell MC1 or the third memory cell MC3. The threshold voltage of the third memory cell MC3 may shift due to interference from the second memory cell MC2. With technological advancements, as the number of memory cells integrated within a limited area increases, the distance between adjacent memory cells may become narrower. As the distance between adjacent memory cells narrows, the degradation of the threshold voltage distribution of multiple memory cells due to interference from adjacent memory cells may become more severe.

[0104] Figures 7A-7C It is a diagram illustrating the charge distribution trapped inside the floating gate of a programmed memory cell.

[0105] Figure 7A A schematic diagram illustrates the situation in Figure 4 and Figure 5 The structure of any one of the multiple memory cells shown. (Refer to...) Figure 7AThe gate of a memory cell may include a control gate and a floating gate. The control gate may be connected to a word line (WL). When the memory device performs a programming operation on the memory cell, a programming voltage is applied to the control gate through the word line (WL). When the programming voltage is applied to the control gate during the programming operation of the memory cell, multiple charges can be trapped inside the floating gate. As the amount of charge trapped in the memory cell increases, the threshold voltage of the memory cell can increase. Figure 7B and Figure 7C The illustration shows an example of charge distribution trapped inside a floating gate. (Reference) Figure 7B The captured charge can form a Gaussian distribution that increases from both ends of the floating gate towards the center. (Reference) Figure 7C ,and Figure 7B Compared to the distribution of charge trapped in the middle portion of a floating gate, the amount of charge trapped in the middle portion can be larger, and the amount of charge trapped in the two end portions can be smaller. As the amount of trapped charge at the two end portions of the floating gate increases, reference... Figure 6 The described interference may have a greater impact on the threshold voltage of memory cells.

[0106] In one embodiment, as an example, a structure of a memory cell including a control gate and a floating gate is described, but this disclosure is not limited to this embodiment. For example, a memory cell according to one embodiment may have a structure in which the floating gate is omitted. The type of film in which multiple charges are trapped can be present in various forms. For ease of description, as an example, a 2D memory cell structure is described, but this disclosure is not limited thereto and can be applied to 3D or 4D memory cell structures.

[0107] Figure 8 This is a diagram illustrating programming operations according to one embodiment.

[0108] refer to Figure 8 Programming operations can include multiple programming cycles PL1 to PLn. The memory device can execute multiple programming cycles PL1 to PLn to program the selected memory cell into any of a plurality of programming states.

[0109] Each of the multiple programming cycles PL1 to PLn may include: a programming voltage application step PGM Step that applies a programming voltage, and a verification step VerifyStep that determines whether a memory cell has been programmed by applying a verification voltage.

[0110] In the programming voltage application step, a programming voltage application operation can be performed to apply a programming voltage to a selected word line connected to the selected memory cell. Through the programming voltage application operation, the selected memory cell can be programmed to any of the programming states from the first state to the nth state (n is a natural number).

[0111] In one embodiment, the programming voltage can be determined using an incremental step pulse programming (ISPP) method. That is, as the programming cycle repeats, the programming voltage level can be gradually increased or decreased by a step voltage. The number of times the programming voltage is applied, the voltage level, the voltage application time, etc., used in each programming cycle can be determined by the memory controller in various ways.

[0112] A pass voltage can be applied to unselected word lines, which are word lines other than the selected word lines. In one embodiment, a pass voltage of the same level can be applied to the unselected word lines. In another embodiment, the pass voltage can have different levels depending on the location of the word line.

[0113] A ground voltage can be applied as a programming enable voltage to a selected bit line connected to the memory cell to be programmed. A programming disable voltage can be applied to an unselected bit line, which is a bit line connected to a memory cell other than the one to be programmed.

[0114] In the programming verification step, the memory device can apply a verification voltage to the selected word line and a verification pass voltage to the unselected word line. The memory device can sense the voltage or current output through the bit lines connected to the memory cells connected to the selected word lines and can determine whether the verification step has passed or failed based on the sensing results.

[0115] In the verification step, a programming verification operation can be performed for at least one of the programming states from the first programming state to the nth programming state. For example, when a memory cell to be programmed to the kth state (k is a natural number equal to or greater than 1 and equal to or less than n) is read as a shutdown cell by the verification voltage corresponding to the kth state, the programming verification operation for the kth state can be performed.

[0116] exist Figure 8In this embodiment, when the selected memory cell is an MLC storing two data bits, the selected memory cell can be programmed to any of the following programming states: erase state and first to third programming states. The number of data bits stored in the memory cell is not limited to this embodiment.

[0117] When the first programming cycle PL1 is executed, after the first programming voltage Vpgml is applied, the first verification voltage V_vfy1 to the third verification voltage V_vfy3 can be applied sequentially to verify the programming state of multiple memory cells. At this time, memory cells with a target programming state of the first programming state can be verified using the first verification voltage V_vfy1, memory cells with a target programming state of the second programming state can be verified using the second verification voltage V_vfy2, and memory cells with a target programming state of the third programming state can be verified using the third verification voltage V_vfy3. The number of verification voltages is not limited to this embodiment.

[0118] Memory cells that have been verified as passed based on each of the verification voltages V_vfy1 to V_vfy3 can be identified as having a target state and can then be disabled for programming in the second programming cycle PL2. A programming disable voltage can be applied to the bit line connected to the disabled memory cell. In the second programming cycle PL2, a second programming voltage Vpgm2 can be applied to the selected word line, the second programming voltage Vpgm2 being one voltage ΔVpgm higher than the first programming voltage Vpgm1.

[0119] Subsequently, the verification operation of the second programming cycle PL2 can be performed in the same manner as the verification operation of the first programming cycle PL1. For example, a successful verification can indicate that the memory cell is read as a shutdown cell by the corresponding verification voltage.

[0120] As described above, when the memory device programs the MLC, the memory device can verify the memory cell having the corresponding programming state as the target state by using the first verification voltage V_vfy1 to the third verification voltage V_vfy3.

[0121] Figure 9 It's a diagram. Figure 2 A circuit diagram of another embodiment of memory block BLKc among memory blocks BLK1 to BLKz.

[0122] refer to Figure 9A memory block BLKc may include multiple serial selectors (SRs). These serial selectors can be connected to multiple bit lines BL1 to BLn, respectively. Each serial selector (SR) may include a source select transistor (SST), a memory cell (MC), and a drain select transistor (DST). The source select transistor (SST) of each serial selector (SR) may be connected between the memory cell (MC) and the common source line (CSL). The source selectors (SST) of multiple serial selectors (SRs) may be connected together to the common source line (CSL). The drain selector (DST) of each serial selector (SR) may be connected between the memory cell (MC) and the bit line BL. The drain selectors (DST) of multiple serial selectors (SRs) may be connected to multiple bit lines BL1 to BLn, respectively. In each serial selector (SR), multiple memory cells (MC) may be provided between the source selector (SST) and the drain selector (DST). In each serial selector (SR), the multiple memory cells (MC) may be connected in series.

[0123] In multiple serial SRs, memory cells MC located in the same order from a common source line CSL can be connected to a single word line. The memory cells MC of multiple serial SRs can be connected to multiple word lines WL1 to WLn.

[0124] In multiple serial line arrays (SRs) arranged in the row direction, memory cells connected to the same word line can be configured as a page. For example, in multiple serial line arrays (SRs), a memory cell connected to the first word line WL1 can be configured as the first page (Page 1). A memory cell connected to the second word line WL2 can be configured as the second page (Page 2). A memory cell connected to the third word line WL3 can be configured as the third page (Page 3). A memory cell connected to the nth word line WLn can be configured as the nth page (Page n).

[0125] The memory device can perform programming operations on selected memory cells in response to programming commands provided from the memory controller. Programming operations can be performed on a page-by-page basis, corresponding to each word line from WL1 to WLn.

[0126] Figure 10 It is a diagram illustrating the voltage applied to the selected word line and the word lines adjacent to the selected word line during programming operations.

[0127] refer to Figure 10 The selected word line (WL) can refer to the word line that connects to the selected memory cell so that the memory device can perform programming operations. The adjacent word line (WL) can be the word line adjacent to the selected word line.

[0128] When the memory device performs a programming operation, a programming voltage Vpgm can be applied to the selected word line (Selected WL). A pass voltage can be applied to the remaining unselected word lines. In one embodiment, a pass voltage Vpass, comprising at least two steps, can be applied to an adjacent word line (Adjacent WL) among the unselected word lines. For example, after a first pass voltage is applied to the adjacent word line (Adjacent WL) at a first time point, a second pass voltage with a different amplitude compared to the first pass voltage can then be applied at a predetermined second time point. The amplitude of the second pass voltage can be greater than the amplitude of the first pass voltage.

[0129] In one embodiment, the electric field formed around the selected word line may need to be concentrated around the selected word line, such that after the programming operation is completed, the charge distribution inside the floating gate of the selected memory cell is formed as follows: Figure 7C The charge distribution is shown. Specifically, an electric field can be formed around the selected word line by applying a programming voltage to the selected word line and a pass voltage to the adjacent word line during programming operations. As the difference between the voltage amplitude applied to the selected word line and the voltage amplitude applied to the adjacent word line increases, the electric field can concentrate on the selected word line. When the amplitude of the pass voltage applied to the adjacent word line is small, the programming speed of the selected memory cell may decrease during programming operations. Therefore, it is necessary to select a pass voltage of appropriate amplitude.

[0130] Figure 11 It is a timing diagram illustrating the voltage applied to the selected word line and the word lines adjacent to the selected word line during a programming operation.

[0131] Specifically, programming operations on the selected memory cell may include the first programming cycle PL1 to the nth programming cycle PLn. Figure 11 The diagram illustrates the voltage amplitude over time, with reference to... Figure 8 In the programming voltage application step of a specific programming cycle among the multiple programming cycles described, the voltage is applied to the selected word line (Selected WL) and the adjacent word lines (Adjacent WLs) adjacent to the selected word line.

[0132] At t1, the first pass voltage Vpassl can be applied to the selected word line Selected WL and the adjacent word line Adjacent WLs.

[0133] At t2, a programming voltage Vpgm of predetermined amplitude can be applied to the selected word line Selected WL. (See reference...) Figure 8 As described, the programming voltage Vpgm can be increased by a step voltage as the programming cycle increases.

[0134] At t3, the potential of the selected word line Selected WL can reach the programming voltage Vpgm level.

[0135] At t4, a second pass voltage Vpass2 can be applied to the adjacent word line Adjacent WLs. The magnitude of the second pass voltage Vpass2 can be greater than the magnitude of the first pass voltage Vpass1.

[0136] At t5, the potential of the adjacent word line Adjacent WLs can reach the level of the second pass voltage Vpass2.

[0137] For reference Figure 11 As described, while the programming voltage is applied to the selected word line (Selected WL), a pass voltage can be applied to the adjacent word lines (Adjacent WLs) in two steps. The timing of the increase from the first pass voltage (Vpass1) to the second pass voltage (Vpass2) can be predetermined.

[0138] Figure 12 It is a diagram illustrating the timing of applying a second through voltage in each segment of the programming operation according to one embodiment.

[0139] In one embodiment, programming operations on the selected memory cell may include multiple programming cycles. These multiple programming cycles may be further divided into a first segment and a second segment. The first segment may include programming cycles PL1 through PL8, one of the multiple programming cycles. The second segment may include programming cycles PL9 through PLn, one of the multiple programming cycles. The nth programming cycle may be the last programming cycle among the multiple programming cycles included in the programming operation on the selected memory cell.

[0140] exist Figure 12 The upper graph illustrates the voltage amplitude over time, applied to the selected word line (WL) during the multiple programming cycles included in the first and second segments of the programming operation. The middle graph illustrates the voltage amplitude over time, applied to adjacent word lines (WLs) during the multiple programming cycles included in the first segment. The lower graph illustrates the voltage amplitude over time, applied to adjacent word lines (WLs) during the multiple programming cycles included in the second segment.

[0141] At t1a, the first pass voltage Vpassl can be applied to the selected word line Selected WL and the adjacent word line Adjacent WLs.

[0142] At t2a, the programming voltage Vpgm can be applied to the selected word line Selected WL. (See reference...) Figure 8 As described, the programming voltage Vpgm can be a voltage that increases by a predetermined step voltage as the programming cycle increases. Therefore, the amplitude of the programming voltage Vpgm can increase as the programming cycle increases.

[0143] At t3a, the potential of the selected word line Selected WL can reach the programming voltage Vpgm level.

[0144] In one embodiment, the timing at which the second pass voltage Vpass2 is applied to the adjacent word line Adjacent WLs can vary depending on the segment that includes the ongoing programming loop.

[0145] When the ongoing programming cycle is included in the first segment, the second pass voltage Vpass2 can be applied to the adjacent word line Adjacent WLs at t5a. For example, in the programming voltage application steps of the first programming cycle PL1 to the eighth programming cycle PL8, the time point at which the second pass voltage is applied to the adjacent word line Adjacent WLs can be t5a.

[0146] When the ongoing programming cycle is included in the second segment, the second pass voltage Vpass2 can be applied to the adjacent word line Adjacent WLs at t4a. For example, in the programming voltage application steps of the ninth programming cycle PL9 to the nth programming cycle PLn, the time point at which the second pass voltage is applied to the adjacent word line Adjacent WLs can be t4a.

[0147] In the programming voltage application step of the programming operation, as the programming cycle increases, the programming voltage Vpgm applied to the selected word line Selected WL can increase by a predetermined step voltage. Therefore, the magnitude of the programming voltage Vpgm applied to the selected word line Selected WL in the programming cycle included in the first section can be smaller than the magnitude of the programming voltage Vpgm applied to the selected word line Selected WL in the programming cycle included in the second section.

[0148] As the difference between the amplitude of the programming voltage Vpgm applied to the selected word line and the amplitude of the pass voltage applied to the adjacent word line AdjacentWLs increases, the electric field can be concentrated on the selected word line Selected WL. Therefore, in the programming loop included in the first segment where the amplitude of the programming voltage Vpgm is relatively low, the duration for which the first pass voltage Vpass1, which has a lower amplitude than the second pass voltage Vpass2, is applied can be set to be longer. Conversely, in the programming loop included in the second segment where the amplitude of the programming voltage Vpgm is relatively high, the duration for which the second pass voltage Vpass2, which has a higher amplitude than the first pass voltage Vpass1, is applied can be set to be longer.

[0149] Figure 13 It is a diagram illustrating the timing of applying a second through voltage in each segment of the programming operation according to another embodiment.

[0150] In one embodiment, programming operations on the selected memory cell may include multiple programming cycles. These multiple programming cycles may be further divided into a first segment, a second segment, and a third segment. The first segment may include the first programming cycle PL1 through the fourth programming cycle PL4. The second segment may include the fifth programming cycle PL5 through the eighth programming cycle PL8. The third segment may include the ninth programming cycle PL9 through the nth programming cycle PLn. The nth programming cycle may be the last programming cycle included in the programming operation on the selected memory cell.

[0151] Figure 13 The graph illustrates the magnitude of the through voltage applied to adjacent word lines (Adjacent WLs) in the programming voltage application step of the programming cycle included in each of the three segments, based on time.

[0152] refer to Figure 13 In the programming voltage application steps of the first programming cycle PL1 to the fourth programming cycle PL4 included in the first section, the first pass voltage Vpass1 can be applied to the adjacent word line Adjacent WLs at t1b, and then the second pass voltage Vpass2 can be applied to the adjacent word line Adjacent WLs at t2b.

[0153] In the programming voltage application steps of the fifth programming cycle PL5 to the eighth programming cycle PL8 included in the second section, the first pass voltage Vpass1 can be applied to the adjacent word line Adjacent WLs at t1b, and then the second pass voltage Vpass2 can be applied to the adjacent word line Adjacent WLs at t3b.

[0154] In the programming voltage application steps of the ninth programming cycle PL9 to the nth programming cycle PLn included in the third section, the first pass voltage Vpass1 can be applied to the adjacent word line Adjacent WLs at t1b, and then the second pass voltage Vpass2 can be applied to the adjacent word line Adjacent WLs at t4b.

[0155] That is, in the programming operation of the selected memory cell, as the number of segments increases, the timing of the second pass voltage being applied to the adjacent word line (Adjacent WLs) can be earlier. In other words, as the number of segments increases, the duration for which the first pass voltage (Vpass1) is applied to the adjacent word line (Adjacent WLs) can be shortened. As the number of segments increases, the duration for which the second pass voltage (Vpass2) is applied to the adjacent word line (Adjacent WLs) can become longer.

[0156] In one embodiment, as the number of segments increases, the timing at which the second voltage is applied can be set earlier by a predetermined step time. For example, the difference between t2b and t3b can be the same as the difference between t3b and t4b.

[0157] The number of segments included in multiple programming cycles is not limited to this embodiment. That is, in the programming operation on the selected memory cell, multiple programming cycles can be divided into four or more segments.

[0158] Figure 14 It is a diagram illustrating the timing of applying the second and third through voltages in each segment of the programming operation according to another embodiment.

[0159] In one embodiment, programming operations on the selected memory cell may include multiple programming cycles. These multiple programming cycles may be further divided into a first segment and a second segment. The first segment may include programming cycles PL1 through PL8, one of the multiple programming cycles. The second segment may include programming cycles PL9 through PLn, one of the multiple programming cycles. The nth programming cycle may be the last programming cycle among the multiple programming cycles included in the programming operation on the selected memory cell.

[0160] Specifically, Figure 14The graph illustrates the magnitude of the through voltage over time, which is applied to adjacent word lines (Adjacent WLs) during the programming voltage application step of the programming cycle included in each of the two segments. In one embodiment, while the programming voltage is applied to the selected word line (Selected WL), the through voltage can be applied to the adjacent word lines (Adjacent WLs) in three steps. The time points at which the through voltage increases from the first through voltage Vpass1 to the second through voltage Vpass2 and from the second through voltage Vpass2 to the third through voltage Vpass3 can be predetermined.

[0161] refer to Figure 14 In the programming voltage application step of the first programming cycle PL1 to the eighth programming cycle PL8 included in the first segment among multiple programming cycles, the first pass voltage Vpass1 can be applied to the adjacent word line Adjacent WLs at t1c.

[0162] After a predetermined time has elapsed since the first pass voltage Vpass1 is applied to the adjacent word line Adjacent WLs at t1c, the second pass voltage Vpass2 can be applied at t2c.

[0163] After a predetermined time has elapsed since the second pass voltage Vpass2 is applied to the adjacent word line Adjacent WLs at t2c, the third pass voltage Vpass3 can be applied at t3c.

[0164] In the programming voltage application step of the ninth programming cycle PL9 to the nth programming cycle PLn, which is included in the second segment among multiple programming cycles, the first pass voltage Vpassl can be applied to the adjacent word line AdjacentWLs at t1c.

[0165] After a predetermined time has elapsed since the first pass voltage Vpass1 is applied to the adjacent word line Adjacent WLs at t1c, the second pass voltage Vpass2 can be applied at t2c'.

[0166] After a predetermined time has elapsed since the second pass voltage Vpass2 is applied to the adjacent word line Adjacent WLs at t2c', the third pass voltage Vpass3 can be applied at t3c'.

[0167] In one embodiment, t2c', which is the time point at which the second through voltage Vpass2 is applied in the programming voltage application step of the programming cycle included in the second segment, can be earlier than t2c, where t2c is the time point at which the second through voltage Vpass2 is applied in the programming voltage application step of the programming cycle included in the first segment.

[0168] In one embodiment, t3c', which is the time point at which the third through voltage Vpass3 is applied in the programming voltage application step of the programming cycle included in the second segment, can be earlier than t3c, where t3c is the time point at which the third through voltage Vpass3 is applied in the programming voltage application step of the programming cycle included in the first segment.

[0169] The number of steps for applying the through voltage to adjacent word lines (Adjacent WLs) is not limited to this embodiment.

[0170] Figure 15 This is a flowchart illustrating the operation of a memory device according to one embodiment.

[0171] In step S1501, the memory device may receive a programming command from the memory controller. The programming command may be a command to perform a programming operation on memory cells connected to multiple word lines. The programming operation may include multiple programming cycles, each including a programming voltage application step.

[0172] In step S1503, in response to a programming command from the memory controller, the memory device can perform a programming operation by applying a programming voltage Vpgm to the selected word line, applying a first pass voltage to the adjacent word line, and then applying a second pass voltage at a predetermined first time point, wherein the second pass voltage is greater than the first pass voltage.

[0173] In step S1505, the memory device can determine whether the currently running programming loop is the m-th loop.

[0174] If the current programming loop is not the m-th loop, in step S1507, the memory device can execute the next programming loop by using a programming voltage Vpgm with an increased step voltage Vstep.

[0175] When the current programming loop is the m-th loop, in step S1509, the memory device can increase the programming voltage Vpgm of the next loop by a step voltage Vstep.

[0176] In step S1511, the memory device can perform a programming operation by applying a programming voltage Vpgm to the selected word line, applying a first pass voltage to the adjacent word line, and then applying a second pass voltage at a predetermined second time point, wherein the second pass voltage is greater than the first pass voltage. The second time point can be earlier than the first time point. In other words, the duration for which the first pass voltage is applied to the adjacent word line in the first to m-th programming cycles can be longer than the duration for which the first pass voltage is applied to the adjacent word line in the (m+1)-last programming cycle.

[0177] In step S1513, the memory device may check whether the programming operation is complete. If the programming operation is not complete, the memory device may re-execute the programming operation from step S1509. When the programming operation is complete, the memory device may terminate the programming operation corresponding to the programming command of the memory controller.

[0178] Figure 16 It's a diagram. Figure 1 A diagram of another embodiment of the memory controller.

[0179] refer to Figure 16 The memory controller 1000 can connect to both a host and a memory device. The memory controller 1000 can be configured to access the memory device in response to requests from the host. For example, the memory controller 1000 can be configured to control write, read, erase, and background operations on the memory device. The memory controller 1000 can be configured to provide an interface between the memory device and the host. The memory controller 1000 can be configured to drive firmware for controlling the memory device.

[0180] The memory controller 1000 may include a processor 1010, a memory buffer 1020, an error correction circuit (ECC) 1030, a host interface 1040, a buffer control circuit 1050, a memory interface 1060, and a bus 1070.

[0181] Bus 1070 can be configured to provide a channel between components of memory controller 1000.

[0182] Processor 1010 can control the overall operation of memory controller 1000 and can execute logical operations. Processor 1010 can communicate with an external host through host interface 1040 and with memory devices through memory interface 1060. Furthermore, processor 1010 can communicate with memory buffer 1020 through buffer controller 1050. Processor 1010 can use memory buffer 1020 as operational memory, cache memory, or buffer memory to control the operation of the storage device.

[0183] Processor 1010 can perform FTL functions. Processor 1010 can translate LBAs provided by the host into PBAs via FTL. FTL can receive LBAs and translate them into PBAs using a mapping table. The address mapping method of the flash translation layer can include various methods based on the mapping unit. Representative address mapping methods include page mapping, block mapping, and hybrid mapping.

[0184] Processor 1010 can be configured to randomize data received from the host. For example, processor 1010 can randomize data received from the host using a randomization seed. The randomized data can be provided to a memory device as data to be stored and can be programmed into a memory cell array.

[0185] Processor 1010 can be configured to derandomize data received from the memory device during a read operation. For example, processor 1010 can use a derandomization seed to derandomize data received from the memory device. The derandomized data can then be output to the host.

[0186] In one embodiment, the processor 1010 may perform randomization and derandomization via driver software or firmware.

[0187] The memory buffer 1020 can be used as the operating memory, cache memory, or buffer memory of the processor 1010. The memory buffer 1020 can store code and commands executed by the processor 1010. The memory buffer 1020 can store data processed by the processor 1010. The memory buffer 1020 may include static RAM (SRAM) or dynamic RAM (DRAM).

[0188] ECC 1030 can perform error correction. ECC 1030 can perform error correction coding (ECC coding) based on data to be written to the memory device via memory interface 1060. The error-corrected data can be transmitted to the memory device via memory interface 1060. ECC 1030 can perform error correction decoding (ECC decoding) on ​​data received from the memory device via memory interface 1060. For example, ECC 1030 can be included as a component of memory interface 1060 within memory interface 1060.

[0189] The host interface 1040 can be configured to communicate with an external host under the control of the processor 1010. The host interface 1040 can be configured to perform communication by using at least one of a variety of communication methods, such as Universal Serial Bus (USB), Serial AT Attachment (SATA), Serial Attached SCSI (SAS), High Speed ​​Chip Interconnect (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI Rapid), Non-Volatile Memory Rapid (NVMe), Universal Flash Storage (UFS), Secure Digital Storage (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Load-Away DIMM (LRDIMM).

[0190] The buffer controller 1050 can be configured to control the memory buffer 1020 under the control of the processor 1010.

[0191] The memory interface 1060 can be configured to communicate with a memory device under the control of the processor 1010. The memory interface 1060 can communicate commands, addresses, and data with the memory device via channels.

[0192] For example, memory controller 1000 may not include memory buffer 1020 and buffer controller 1050.

[0193] For example, processor 1010 can control the operation of memory controller 1000 using code. Processor 1010 can load code from a non-volatile memory device (e.g., read-only memory) located within memory controller 1000. In another example, processor 1010 can load code from a memory device via memory interface 1060.

[0194] For example, the bus 1070 of the memory controller 1000 can be divided into a control bus and a data bus. The data bus can be configured to transmit data within the memory controller 1000, and the control bus can be configured to transmit control information such as commands and addresses within the memory controller 1000. The data bus and the control bus can be separate from each other and can operate independently. The data bus can be connected to the host interface 1040, the buffer controller 1050, the ECC 1030, and the memory interface 1060. The control bus can be connected to the host interface 1040, the processor 1010, the buffer controller 1050, the memory buffer 1020, and the memory interface 1060.

[0195] Figure 17 This is a block diagram illustrating a memory card system, to which a storage device according to an embodiment of the present disclosure is applied in the memory card system.

[0196] refer to Figure 17 The memory card system 2000 includes a memory controller 2100, a memory device 2200, and a connector 2300.

[0197] Memory controller 2100 can be connected to memory device 2200. Memory controller 2100 can be configured to access memory device 2200. For example, memory controller 2100 can be configured to control read, write, erase, and background operations on memory device 2200. Memory controller 2100 can be configured to provide an interface between memory device 2200 and a host. Memory controller 2100 can be configured to drive firmware for controlling memory device 2200. Memory controller 2100 can be referenced... Figure 1The memory controller 200 described is implemented in the same way.

[0198] For example, memory controller 2100 may include components such as random access memory (RAM), processor, host interface, memory interface, and ECC.

[0199] The memory controller 2100 can communicate with external devices via connector 2300. The memory controller 2100 can communicate with external devices (e.g., a host) according to specific communication standards. For example, the memory controller 2100 can be configured to communicate with external devices via at least one of various communication standards, such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and NVMe. For example, connector 2300 can be defined by at least one of the aforementioned communication standards.

[0200] For example, the memory device 2200 can be configured with a variety of non-volatile memory elements, such as electrically erasable and programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase-change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin-torque magnetic RAM (STT-MRAM).

[0201] The memory controller 2100 and memory device 2200 can be integrated into a single semiconductor device to configure memory cards. For example, the memory controller 2100 and memory device 2200 can be integrated into a single semiconductor device to configure memory cards such as PC cards (Personal Computer Memory Card International Association (PCMCIA)), compact flash memory cards (CF), smart media cards (SM or SMC), memory sticks, multimedia cards (MMC, RS-MMC, micro MMC or eMMC), SD cards (SD, mini SD, micro SD or SDHC), and universal flash storage (UFS).

[0202] Figure 18 This is a block diagram illustrating a solid-state drive (SSD) system, to which a storage device according to an embodiment of the present disclosure is applied according to an SSD system.

[0203] refer to Figure 18The SSD system 3000 may include a host 3100 and an SSD 3200. The SSD 3200 can exchange signals SIG with the host 3100 through a signal connector 3001 and can receive power PWR through a power connector 3002. The SSD 3200 may include an SSD controller 3210, multiple flash memory devices 3221 to 322n, an auxiliary power device 3230, and a buffer memory 3240.

[0204] According to one embodiment of this disclosure, the SSD controller 3210 can perform reference... Figure 1 The functions of the memory controller 200 are described.

[0205] SSD controller 3210 can control multiple flash memory devices 3221 to 322n in response to signals received from host 3100. For example, the signal can be based on the interface between host 3100 and SSD 3200. For example, the signal can be defined by at least one interface such as: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and NVMe.

[0206] Auxiliary power device 3230 can be connected to host 3100 via power connector 3002. Auxiliary power device 3230 can receive power PWR from host 3100 and use this power for charging. When the power supply from host 3100 is insufficient, auxiliary power device 3230 can provide power to SSD 3200. For example, auxiliary power device 3230 can be located inside SSD 3200 or externally to SSD 3200. For example, auxiliary power device 3230 can be located on the motherboard and can provide auxiliary power to SSD 3200.

[0207] Buffer memory 3240 can operate as a buffer memory for SSD 3200. For example, buffer memory 3240 can temporarily store data received from host 3100 or data received from multiple flash memories 3221 to 322n, or it can temporarily store metadata (e.g., mapping tables) of flash memories 3221 to 322n. Buffer memory 3240 can include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0208] Figure 19 This is a block diagram illustrating a user system, in which a storage device according to an embodiment of the present disclosure is applied.

[0209] refer to Figure 19 The user system 4000 may include an application processor 4100, a memory module 4200, a network module 4300, a storage module 4400, and a user interface 4500.

[0210] Application processor 4100 can drive components, operating system (OS), user programs, etc., included in user system 4000. For example, application processor 4100 may include controllers, interfaces, graphics engines, etc., that control components included in user system 4000. Application processor 4100 can be provided as a system-on-a-chip (SoC).

[0211] The memory module 4200 can operate as the main memory, operating memory, buffer memory, or cache memory of the user system 4000. The memory module 4200 may include volatile random access memory such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM, or non-volatile random access memory such as PRAM, ReRAM, MRAM, and FRAM. For example, the application processor 4100 and the memory module 4200 may be packaged in a stacked package (POP) and provided as a semiconductor package.

[0212] Network module 4300 can communicate with external devices. For example, network module 4300 can support wireless communications such as Code Division Multiple Access (CDMA), Global System for Mobile Communications (GSM), Wideband CDMA (WCDMA), CDMA-2000, Time Division Multiple Access (TDMA), LTE, WiMAX, WLAN, UWB, Bluetooth, and Wi-Fi. For example, network module 4300 can be included in application processor 4100.

[0213] Storage module 4400 can store data. For example, storage module 4400 can store data received from application processor 4100. Alternatively, storage module 4400 can transfer data stored in storage module 4400 to application processor 4100. For example, storage module 4400 can be implemented as a non-volatile semiconductor memory element, such as phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), NAND flash memory, NOR flash memory, and 3D NAND flash memory. For example, storage module 4400 can be provided as a removable storage device (removable drive) (such as a memory card) and external drive of user system 4000.

[0214] For example, storage module 4400 may include multiple non-volatile memory devices, and these multiple non-volatile memory devices may be used with reference to... Figure 1 The memory device 100 described operates in the same manner. The memory module 4400 can be compared with the referenced... Figure 1 The storage device 50 described operates in the same manner.

[0215] User interface 4500 may include interfaces for inputting data or instructions to application processor 4100 or for outputting data to external devices. For example, user interface 4500 may include user input interfaces such as a keyboard, keypad, buttons, touch panel, touchscreen, touchpad, touchball, camera, microphone, gyroscope sensor, vibration sensor, and piezoelectric element. User interface 4500 may include user output interfaces such as liquid crystal display (LCD), organic light-emitting diode (OLED) display device, active-matrix OLED (AMOLED) display device, LED, speaker, and monitor.

Claims

1. A memory device, comprising: A plurality of memory cells, wherein the plurality of memory cells are connected to each of a plurality of word lines; Peripheral circuitry is configured to perform programming operations on memory cells connected to a selected word line among the plurality of word lines, the programming operations including a plurality of programming loops; as well as The control logic is configured to, while a programming voltage is applied to the selected word line, control the peripheral circuitry to apply a first pass voltage to an adjacent word line adjacent to the selected word line, and then apply a second pass voltage to the adjacent word line, the second pass voltage being higher than the first pass voltage. As the multiple programming loops proceed, the control logic adjusts the application time of the second through voltage.

2. The memory device of claim 1, wherein from the first cycle of the plurality of programming cycles to before the selected cycle, the first time for which the first through voltage is applied to the adjacent word line is longer than the second time for which the second through voltage is applied to the adjacent word line, and From the selected loop to the last loop among the plurality of programming loops, the second time is longer than the first time.

3. The memory device of claim 1, wherein as the plurality of programming cycles proceed, the control logic controls the peripheral circuitry to apply the second through voltage for a longer period than the first through voltage is applied.

4. The memory device of claim 1, wherein the plurality of programming cycles are divided into a plurality of segments, and The control logic is configured to control the peripheral circuitry to apply the second through voltage to the adjacent word line at a predetermined time point within a programming loop included in a first segment of the plurality of segments, wherein the first segment includes a first programming loop, and The control logic is configured to apply the second pass voltage to the adjacent word line at a time point earlier than the predetermined time point in the programming loop included in the second segment following the first segment.

5. The memory device of claim 1, wherein the control logic is configured to control the peripheral circuitry to apply a programming voltage with a predetermined step voltage to the selected word line as a programming cycle in the plurality of programming cycles is added during the programming operation.

6. The memory device of claim 5, wherein as the programming cycle in the plurality of programming cycles increases, the amplitude of the second through voltage increases the predetermined step voltage.

7. The memory device of claim 1, wherein the amplitude of the first through voltage is a minimum voltage for forming a channel through which current flows between the source and drain regions of a plurality of memory cells connected to the adjacent word lines.

8. A memory device, comprising: A plurality of memory cells, wherein the plurality of memory cells are connected to each of a plurality of word lines; Peripheral circuitry is configured to perform programming operations on memory cells connected to a selected word line among the plurality of word lines, the programming operations including a plurality of programming loops; as well as The control logic is configured to, in some of the plurality of programming cycles of the programming operation, control the peripheral circuitry to apply a programming voltage to the selected word line, and simultaneously apply a pass voltage that increases at two or more time points to adjacent word lines adjacent to the selected word line while the programming voltage is being applied. The control logic is configured to, in the remaining programming cycles of the plurality of programming cycles of the programming operation, control the peripheral circuitry to apply an increased through voltage to the adjacent word line at a time point different from the two or more time points at which the through voltage increases in some of the plurality of programming cycles.

9. The memory device of claim 8, wherein, from the first cycle to the selected cycle, the duration for which the amplitude of the through voltage is maintained after the through voltage increases at the first time point among the two or more time points is longer than the duration for which the amplitude of the through voltage is maintained after the through voltage increases at the last time point among the two or more time points, and The duration for which the amplitude of the through voltage is maintained after the selected cycle increases at the first time point is shorter than the duration for which the amplitude of the through voltage is maintained after the through voltage increases at the last time point.

10. The memory device of claim 8, wherein the through voltage is increased by a predetermined step voltage at each of the two or more time points.

11. A method of operating a memory device, the memory device performing a programming operation on memory cells connected to a selected word line of a plurality of word lines, the programming operation including a plurality of programming loops, the method comprising: Apply a programming voltage to the selected word line, and While the programming voltage is being applied, a pass voltage is applied to the adjacent word line adjacent to the selected word line. Applying the voltage includes: A first pass voltage is applied to the adjacent word line for a first time period; A second pass voltage is applied to the adjacent word line for a second time period, the second pass voltage being higher than the first pass voltage, and the second time period is adjusted as the plurality of programming cycles proceed.

12. The method of claim 11, wherein applying the second through voltage comprises: As the multiple programming cycles proceed, the second through voltage is applied for a longer period than the first through voltage is applied.

13. The method of claim 11, wherein the plurality of programming loops are divided into a plurality of segments, and Applying the second through voltage to the adjacent word line includes: In a programming loop included in a first segment of the plurality of segments, the second through voltage is applied to the adjacent word line at a predetermined time point, wherein the first segment includes a first programming loop, and When a subsequent programming loop, which is part of a different segment among the plurality of segments, is executed, the second pass voltage is applied to the adjacent word line at a time point that is a step time earlier than the predetermined time point in the programming loop included in the second segment after the first segment.

14. The method of claim 11, wherein applying the programming voltage to the selected word line comprises: As the programming cycle increases among the plurality of programming cycles, a programming voltage that increases by a predetermined step voltage is applied to the selected word line.

15. The method of claim 11, wherein the amplitude of the first through voltage is a minimum voltage for forming a channel through which current flows between the source and drain regions of a plurality of memory cells connected to the adjacent word lines.

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