Memory device and method of operation thereof

Abstract

The present technology relates to a memory device and an operating method thereof. According to an embodiment of the disclosure, a memory device can include a plurality of memory cells connected to each word line, a peripheral circuit configured to perform a program operation on the memory cells connected to a selected word line, and a control logic configured to control the peripheral circuit to perform the program operation on the memory cells connected to the selected word line after performing a pre-program operation that increases a threshold voltage of an over-erase cell having a threshold voltage of an over-erase state lower than a threshold voltage of an erase state among the memory cells connected to an adjacent word line, which is a word line next to the selected word line, to the threshold voltage of the erase state.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2022-0017787, filed on February 10, 2022, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to an electronic device, and more specifically to a memory device and a method of operating the same. Background Technology

[0004] A storage device is a device that stores data under the control of a host device such as a computer or smartphone. A storage device may include a memory device that stores the data therein and a memory controller that controls the memory device. Memory devices are classified as volatile memory devices and non-volatile memory devices.

[0005] Volatile memory devices are devices that store data only while powered on and lose the stored data when power is off. Volatile memory devices include static random access memory (SRAM), dynamic random access memory (DRAM), etc.

[0006] Non-volatile memory devices are devices that do not lose data even when power is off. Non-volatile memory devices include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, etc. Summary of the Invention

[0007] According to embodiments of the present disclosure, a memory device may include: a plurality of memory cells connected to each of a plurality of word lines; peripheral circuitry configured to perform a programming operation on memory cells connected to selected word lines among the plurality of word lines; and control logic configured to control the peripheral circuitry to perform a programming operation on memory cells connected to the selected word lines after performing a pre-programming operation, the pre-programming operation increasing the threshold voltage of an over-erased cell connected to an adjacent word line, which has a threshold voltage of an over-erased state lower than the threshold voltage of the erased state, to the threshold voltage of the erased state, wherein the adjacent word line is the word line immediately adjacent to the selected word line.

[0008] According to embodiments of the present disclosure, a memory device may include: a plurality of memory cells connected to each of a plurality of word lines; peripheral circuitry configured to perform a programming operation on memory cells connected to selected word lines among the plurality of word lines; and control logic configured to control the peripheral circuitry to perform a programming operation on memory cells connected to the selected word lines after performing a pre-programming operation, the pre-programming operation programming the threshold voltage of over-erased cells connected to adjacent word lines, which have a threshold voltage lower than the threshold voltage of the erase state, to the threshold voltage of the erase state, wherein adjacent word lines are word lines immediately adjacent to the selected word line.

[0009] According to embodiments of this disclosure, an operation includes a memory device comprising a plurality of memory cells connected to each of a plurality of word lines, and a method for performing a programming operation on memory cells connected to selected word lines. The method may include: determining an over-erased cell connected to a memory cell of an adjacent word line having a threshold voltage of an over-erased state lower than a threshold voltage of an erased state, wherein the adjacent word line is a word line immediately adjacent to the selected word line; performing a pre-programming operation to program the over-erased cell to an erased state; and performing a programming operation on the memory cell connected to the selected word line. Attached Figure Description

[0010] Figure 1 This is a diagram illustrating a storage device according to an embodiment.

[0011] Figure 2 It's a diagram. Figure 1 A diagram of the structure of a memory device.

[0012] Figure 3 It's a diagram. Figure 2 A diagram of an embodiment of a memory cell array.

[0013] Figure 4 It's a diagram. Figure 2 The circuit diagram of any one of the memory blocks BLKa from BLK1 to BLKz.

[0014] Figure 5 It's a diagram. Figure 2 A circuit diagram of another embodiment of any one of the memory blocks BLK1 to BLKz, BLKb.

[0015] Figure 6 This is a diagram illustrating programming operations according to an embodiment.

[0016] Figure 7 It's a diagram. Figure 2 A circuit diagram of another embodiment of any one of the memory blocks BLK1 to BLKz, BLKc.

[0017] Figure 8 This is a diagram illustrating the threshold voltage distribution of memory cells before programming operations are performed on adjacent word lines, after programming operations on memory cells connected to the selected word line have been completed.

[0018] Figure 9 This diagram illustrates the threshold voltage distribution of a memory cell after programming operations are performed on adjacent word lines following the completion of programming operations on the memory cell connected to the selected word line.

[0019] Figure 10 This is a diagram illustrating the pre-programming operation of memory cells connected to adjacent word lines according to an embodiment.

[0020] Figure 11 It is a flowchart illustrating the pre-programming operation and the programming operation according to an embodiment.

[0021] Figure 12 This is a diagram illustrating the over-erasing unit sensing operation and pre-programming operation according to an embodiment.

[0022] Figure 13 It is a diagram illustrating the sequence of pre-programming and programming operations for each word line according to an embodiment.

[0023] Figure 14 It is a diagram illustrating the sequence of pre-programming and programming operations for each word line according to another embodiment.

[0024] Figure 15 This is a flowchart illustrating the operation of a memory device according to an embodiment.

[0025] Figure 16 This is a flowchart illustrating the operation of a memory device according to another embodiment.

[0026] Figure 17 It's a diagram. Figure 1 A diagram of another embodiment of the memory controller.

[0027] Figure 18 This is a block diagram illustrating a memory card system employing a storage device according to an embodiment of the present disclosure.

[0028] Figure 19 This is a block diagram illustrating a solid-state drive (SSD) system using a storage device according to an embodiment of the present disclosure.

[0029] Figure 20 This is a block diagram illustrating a user system employing a storage device according to an embodiment of the present disclosure. Specific Implementation

[0031] The specific structural or functional descriptions of embodiments based on the present concept disclosed in this disclosure are merely illustrative to illustrate embodiments based on the present concept. Embodiments may be implemented in various forms according to the present concept and should not be construed as limited to the embodiments described herein.

[0032] The present disclosure will be described in detail below with reference to the accompanying drawings, which illustrate preferred embodiments of the present disclosure.

[0033] Embodiments of this disclosure provide a memory device in which the degradation of the threshold voltage distribution of memory cells due to interference between adjacent word lines during programming operations of the memory device is improved.

[0034] Figure 1 This is a diagram illustrating a storage device according to an embodiment.

[0035] refer to Figure 1 Storage device 50 may include memory device 100 and memory controller 200 for controlling the operation of memory device 100. Storage device 50 may be a device that stores data under the control of a host, such as a cellular phone, smartphone, MP3 player, laptop computer, desktop computer, game console, television, tablet PC, or in-vehicle infotainment system.

[0036] Storage device 50 can be manufactured as one of various types of storage devices depending on the host interface, which serves as the method of communication with the host. For example, storage device 50 can be configured as any of various types of storage devices, such as multimedia cards in the form of SSD, MMC, eMMC, RS-MMC and micro-MMC, secure digital cards in the form of SD, mini-SD and micro-SD, universal serial bus (USB) storage devices, universal flash memory (UFS) devices, PCMCIA card type storage devices, peripheral component interconnect (PCI) card type storage devices, PCI Express (PCI-E) card type storage devices, compact flash (CF) cards, smart media cards, and memory sticks.

[0037] Storage device 50 can be manufactured as any of various types of packages. For example, storage device 50 can be manufactured as any of various package types, such as package-on-package (POP), system-in-package (SIP), system-on-chip (SOC), multi-chip package (MCP), chip-on-board (COB), wafer-level fabrication package (WFP), and wafer-level stacked package (WSP).

[0038] Memory device 100 can store data. Memory device 100 can operate under the control of memory controller 200. Memory device 100 may include a memory cell array, which includes a plurality of memory cells for storing data. The memory cell array may include a plurality of memory blocks. Each memory block may include a plurality of memory cells. A memory block may include a plurality of pages. In one embodiment, a page may be a unit for storing data in memory device 100 or retrieving data stored in memory device 100. A memory block may be a unit for erasing data. In one embodiment, memory device 100 may be Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate 4 (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR), Rambus Dynamic Random Access Memory (RDRAM), NAND flash memory, Vertical NAND flash memory, NOR flash memory, Resistive Random Access Memory (RRAM), Phase Change Random Access Memory (PRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), Spin-Torque Random Access Memory (STT-RAM), etc. In this disclosure, for ease of description, it is assumed that memory device 100 is NAND flash memory.

[0039] Memory device 100 can be configured to receive commands and addresses from memory controller 200 and can access regions selected by addresses in the memory cell array. That is, memory device 100 can perform operations as commands on the regions selected by addresses. For example, memory device 100 can perform write operations (programming operations), read operations, and erase operations. During a programming operation, memory device 100 can program data into the region selected by the address. During a read operation, memory device 100 can read data from the region selected by the address. During an erase operation, memory device 100 can erase data stored in the region selected by the address.

[0040] In one embodiment, memory device 100 may receive a programming command PGM CMD, data DATA, and an address ADD from memory controller 200. Memory device 100 may program data DATA in the region selected by the address ADD received from memory controller 200 in response to the programming command PGM CMD received from memory controller 200. Before performing a programming operation on memory cells connected to the selected word line, memory device 100 may perform a pre-programming operation on memory cells connected to adjacent word lines adjacent to the selected word line. The pre-programming operation may be an operation of increasing the threshold voltage of a memory cell having an over-erased state threshold voltage to the erased state threshold voltage.

[0041] The memory controller 200 can control the overall operation of the storage device 50.

[0042] When power is supplied to storage device 50, memory controller 200 can execute firmware (FW). When storage device 100 is a flash memory device, memory controller 200 can operate firmware, such as flash translation layer (FTL) for controlling communication between the host and storage device 100.

[0043] In one embodiment, the memory controller 200 may receive data and a logical block address (LBA) from a host and translate the LBA into a physical block address (PBA), which indicates the address of the memory cell in which the data included in the memory device 100 will be stored.

[0044] The memory controller 200 can control the memory device 100 to perform programming, reading, or erasing operations in response to requests from the host. During a programming operation, the memory controller 200 can provide the memory device 100 with programming commands, a PBA, and data. During a reading operation, the memory controller 200 can provide the memory device 100 with read commands and a PBA. During an erasing operation, the memory controller 200 can provide the memory device 100 with erase commands and a PBA.

[0045] In one embodiment, memory controller 200 can generate and send programming commands, addresses, and data to memory device 100 without a request from the host. For example, memory controller 200 can provide commands, addresses, and data to memory device 100 to perform background operations, such as programming operations for wear leveling and programming operations for garbage collection.

[0046] In one embodiment, the memory controller 200 can control at least two memory devices 100. In this case, the memory controller 200 can control the memory devices 100 using an interleaving method to improve operational performance.

[0047] The host can communicate with the storage device 50 using at least one of a variety of communication methods, such as Universal Serial Bus (USB), Serial AT Accessory (SATA), Serial Attached SCSI (SAS), High Speed ​​Chip Interconnect (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), PCI Fast (PCIe), Non-Volatile Memory Fast (NVMe), Universal Flash (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Low Load DIMM (LRDIMM).

[0048] Figure 2 It's a diagram. Figure 1 A diagram of the structure of a memory device.

[0049] refer to Figure 2 The memory device 100 may include a memory cell array 110, peripheral circuitry 120, and control logic 130.

[0050] The memory cell array 110 may include multiple memory blocks BLK1 to BLKz. The multiple memory blocks BLK1 to BLKz can be connected to the address decoder 121 via row lines RL. The multiple memory blocks BLK1 to BLKz can be connected to the read and write circuitry 123 via bit lines BL1 to BLm. Each memory block in the multiple memory blocks BLK1 to BLKz may include multiple memory cells. As an embodiment, the multiple memory cells may be non-volatile memory cells. Among the multiple memory cells, memory cells connected to the same word line can be defined as a physical page. That is, the memory cell array 110 may consist of multiple pages.

[0051] Each memory cell of the memory device 100 can be configured as a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a three-level cell (TLC) storing three data bits, or a four-level cell (QLC) storing four data bits.

[0052] The peripheral circuit 120 may include an address decoder 121, a voltage generator 122, a read and write circuit 123, and a data input / output circuit 124.

[0053] The peripheral circuitry 120 can drive the memory cell array 110. For example, the peripheral circuitry 120 can drive the memory cell array 110 to perform programming operations, reading operations, and erasing operations.

[0054] Address decoder 121 can be connected to memory cell array 110 via row lines RL. Row lines RL may include drain select lines, word lines, source select lines, and common source lines. According to embodiments of this disclosure, word lines may include ordinary word lines and pseudo-word lines. According to embodiments of this disclosure, row lines RL may also include pipe select lines.

[0055] Address decoder 121 can be configured to operate in response to control of control logic 130. Address decoder 121 can receive address RADD from control logic 130.

[0056] Address decoder 121 can be configured to decode the block address of the received address RADD. Address decoder 121 can select at least one memory block from memory blocks BLK1 to BLKz based on the decoded block address. Address decoder 121 can be configured to decode the row address of the received address RADD. Address decoder 121 can select at least one word line of the selected memory block by applying a voltage provided from voltage generator 122 to at least one word line.

[0057] During programming operations, address decoder 121 can apply a programming voltage to the selected word line and can apply a pass voltage with a lower voltage level than the programming voltage to the unselected word line. During programming verification operations, address decoder 121 can apply a verification voltage to the selected word line and can apply a verification pass voltage with a higher voltage level than the verification voltage to the unselected word line.

[0058] During a read operation, the address decoder 121 can apply a read voltage to the selected word line and apply a read pass voltage with a higher voltage than the read voltage to the unselected word line.

[0059] According to embodiments of this disclosure, erase operations on memory device 100 can be performed on a block-by-block basis. The address ADDR input to memory device 100 during the erase operation may include a block address. Address decoder 121 can decode the block address and select a memory block based on the decoded block address. During the erase operation, address decoder 121 can apply a ground voltage to the word line connected to the selected memory block.

[0060] Voltage generator 122 can be configured to generate multiple voltages using an external power supply voltage supplied to memory device 100. Voltage generator 122 can operate in response to control of control logic 130.

[0061] As one embodiment, voltage generator 122 can generate an internal power supply voltage by adjusting an external power supply voltage. The internal power supply voltage generated by voltage generator 122 can be used as the operating voltage of memory device 100.

[0062] As one embodiment, voltage generator 122 can generate multiple voltages by using an external power supply voltage or an internal power supply voltage. Voltage generator 122 can be configured to generate various voltages required by memory device 100. For example, voltage generator 122 can generate multiple erase voltages, multiple programming voltages, multiple pass voltages, multiple select read voltages, and multiple non-select read voltages.

[0063] To generate multiple voltages with different voltage levels, voltage generator 122 may include multiple pumping capacitors that receive internal voltages and selectively activate in response to control logic 130 to generate multiple voltages.

[0064] The generated voltages can be supplied to the memory cell array 110 by the address decoder 121.

[0065] The read and write circuitry 123 may include first page buffers PB1 through m-th page buffers PBm. First page buffers PB1 through m-th page buffers PBm may be connected to the memory cell array 110 via bit lines BL1 through BLm, respectively. First page buffers PB1 through m-th page buffers PBm may operate in response to control logic 130.

[0066] Page buffers PB1 through PBm can output and receive data DATA from data input / output circuit 124. During programming operations, page buffers PB1 through PBm can receive the data DATA to be stored through data input / output circuit 124 and data line DL.

[0067] During programming operations, when a programming voltage is applied to the selected word line, the first page buffer PB1 to the m-th page buffer PBm can transfer the data DATA to be stored (that is, the data DATA received through the data input / output circuit 124) to the selected memory cell via bit lines BL1 to BLm. The memory cell of the selected page can be programmed based on the transferred data DATA. Memory cells connected to bit lines to which a programming enable voltage (e.g., ground voltage) is applied can have an increased threshold voltage. The threshold voltage of memory cells connected to bit lines to which a programming disable voltage (e.g., power supply voltage) is applied can be maintained. During programming verification operations, the first page buffer PB1 to the m-th page buffer PBm can read the data DATA stored in the memory cell from the selected memory cell via bit lines BL1 to BLm.

[0068] During a read operation, the read and write circuit 123 can read data DATA from the memory cell of the selected page via bit lines BL1 to BLm and store the read data DATA in the first page buffer PB1 to the m-th page buffer PBm.

[0069] During the erase operation, the read and write circuitry 123 can float bit lines BL1 to BLm. As one embodiment, the read and write circuitry 123 may include column select circuitry.

[0070] The data input / output circuit 124 can be connected to the first page buffer PB1 to the m-th page buffer PBm via the data line DL. The data input / output circuit 124 can operate in response to the control logic 130.

[0071] The data input / output circuit 124 may include multiple input / output buffers (not shown) for receiving data DATA. During programming operations, the data input / output circuit 124 may receive data DATA to be stored from an external controller (not shown). During read operations, the data input / output circuit 124 may output data DATA transferred from the first page buffer PB1 to the m-th page buffer PBm included in the read and write circuit 123 to the external controller.

[0072] During a read or verification operation, the sensing circuit 125 can generate a reference current in response to the signal of the enable bit VRYBIT generated by the control logic 130, and can compare the sensed voltage VPB received from the read and write circuit 123 with the reference voltage generated by the reference current to output a pass signal PASS or a failure signal FAIL to the control logic 130.

[0073] In one embodiment, the sensing circuit 125 may include a current sensing circuit that counts the number of failure bits in the target cell, which is the number of cells that have failed to be programmed.

[0074] Control logic 130 can be connected to address decoder 121, voltage generator 122, read and write circuitry 123, data input / output circuitry 124, and sensing circuitry 125. Control logic 130 can be configured to control all operations of memory device 100. Control logic 130 can operate in response to commands (CMD) transmitted from external devices.

[0075] Control logic 130 can generate various signals to control peripheral circuitry 120 in response to commands CMD and ADDR. For example, control logic 130 can generate an operation signal OPSIG, a row address RADD, read / write circuit control signals PBSIGNALS, and an enable bit VRYBIT in response to commands CMD and ADDR. Control logic 130 can output the operation signal OPSIG to a voltage generator 122, the row address RADD to an address decoder 121, the read / write circuit control signals PBSIGNALS to a read / write circuit 123, and the enable bit VRYBIT to a sensing circuit 125. Furthermore, control logic 130 can determine whether the verification operation passed or failed in response to the pass signal PASS or the failure signal FAIL output by the sensing circuit 125.

[0076] In one embodiment, control logic 130 may receive a programming command from a memory controller. Control logic 130 may control peripheral circuitry 120 such that memory device 100 performs a programming operation on memory cells connected to a selected word line in response to the programming command received from the memory controller. Control logic 130 may perform a pre-programming operation on memory cells connected to adjacent word lines before performing the programming operation on the memory cells connected to the selected word line. An adjacent word line may refer to a word line adjacent to the selected word line. The pre-programming operation may be an operation that increases the threshold voltage of a memory cell connected to the adjacent word line that has an over-erased state threshold voltage to the erased state threshold voltage. The over-erased state threshold voltage may be lower than the erased state threshold voltage.

[0077] Figure 3 It's a diagram. Figure 2 A diagram of an embodiment of a memory cell array.

[0078] refer to Figure 3 The memory cell array 110 may include multiple memory blocks BLK1 to BLKz. Each memory block may have a three-dimensional structure. Each memory block may include multiple memory cells stacked on a substrate. Such multiple memory cells may be arranged along the +X, +Y, and +Z directions. (Reference) Figure 4 The structure of each memory block is described in more detail.

[0079] Figure 4 It's a diagram. Figure 2 The circuit diagram of any one of the memory blocks BLKa from BLK1 to BLKz.

[0080] refer to Figure 4The memory block BLKa may include multiple cell strings CS11 to CS1m and CS21 to CS2m. As an example, each of the multiple cell strings CS11 to CS1m and CS21 to CS2m may be formed in a "U" shape. In the memory block BLKa, m cell strings may be arranged in the row direction (i.e., the +X direction). Figure 4 In this context, two unit strings can be arranged in the column direction (i.e., the +Y direction). However, this is for ease of description, and it can be understood that three or more unit strings can be arranged in the column direction.

[0081] Each of the multiple cell strings CS11 to CS1m and CS21 to CS2m may include at least one source selection transistor SST, a first memory cell MC1 to the nth memory cell MCn, a pipe transistor PT, and at least one drain selection transistor DST.

[0082] Each of the memory cells MC1 to MCn and the select transistors SST and DST can have a similar structure. As one embodiment, each of the memory cells MC1 to MCn and the select transistors SST and DST may include a channel layer, a tunneling insulating film, a charge storage film, and a barrier insulating film. As one embodiment, a pillar for providing the channel layer may be provided in each cell string. As one embodiment, a pillar for providing at least one of the channel layer, tunneling insulating film, charge storage film, and barrier insulating film may be provided in each cell string.

[0083] The source selection transistor SST of each cell string can be connected between the common source line CSL and memory cells MC1 to MCp.

[0084] As one embodiment, source-select transistors in cell strings arranged in the same row can be connected to source-select lines extending in the row direction, and source-select transistors in cell strings arranged in different rows can be connected to different source-select lines. Figure 4 In the first row, the source selection transistors CS11 to CS1m can be connected to the first source selection line SSL1. The source selection transistors CS21 to CS2m in the second row can be connected to the second source selection line SSL2.

[0085] As another embodiment, the source selection transistors of cell strings CS11 to CS1m and CS21 to CS2m can be connected together to a single source selection line.

[0086] The first memory cell MC1 to the nth memory cell MCn of each cell string can be connected between the source selection transistor SST and the drain selection transistor DST.

[0087] The first memory cells MC1 to the nth memory cell MCn can be divided into first memory cells MC1 to the pth memory cells MCp and (p+1)th memory cells MCp+1 to the nth memory cells MCn. The first memory cells MC1 to the pth memory cells MCp can be arranged sequentially in the direction opposite to the +Z direction and can be connected in series between the source selection transistor SST and the channel transistor PT. The (p+1)th memory cells MCp+1 to the nth memory cells MCn can be arranged sequentially in the +Z direction and can be connected in series between the channel transistor PT and the drain selection transistor DST. The first memory cells MC1 to the pth memory cells MCp and the (p+1)th memory cells MCp+1 to the nth memory cells MCn can be connected to each other via the channel transistor PT. The gates of the first memory cells MC1 to the nth memory cells MCn in each cell string can be connected to the first word line WL1 to the nth word line WLn, respectively.

[0088] The gate of the pipe transistor PT in each unit string can be connected to the pipe PL.

[0089] The drain select transistor (DST) of each cell string can be connected between the corresponding bit line and memory cells MCp+1 to MCn. Cell strings arranged in the row direction can be connected to drain select lines extending in the row direction. The drain select transistors of cell strings CS11 to CS1m in the first row can be connected to the first drain select line DSL1. The drain select transistors of cell strings CS21 to CS2m in the second row can be connected to the second drain select line DSL2.

[0090] A string of cells arranged in the column direction can be connected to a bit line extending in the column direction. Figure 4 In the diagram, the cell strings CS11 and CS21 in the first column can be connected to the first bit line BL1. The cell strings CS1m and CS2m in the m-th column can be connected to the m-th bit line BLm.

[0091] Memory cells connected to the same word line in a cell string arranged in a row direction can form a page. For example, in the cell strings CS11 to CS1m of the first row, memory cells connected to the first word line WL1 can form a page. In the cell strings CS21 to CS2m of the second row, memory cells connected to the first word line WL1 can form another page. A cell string arranged in a row direction can be selected by selecting either the drain select line DSL1 or DSL2. A page of the selected cell string can be selected by selecting any of the word lines WL1 to WLn.

[0092] Figure 5 It's a diagram. Figure 2A circuit diagram of another embodiment of any one of the memory blocks BLK1 to BLKz, BLKb.

[0093] As another embodiment, even-numbered bit lines and odd-numbered bit lines can be provided instead of the first bit line BL1 to the m-th bit line BLm. Furthermore, the even-numbered cell strings among the cell strings CS11' to CS1m' or CS21' to CS2m arranged in the row direction can be connected to the even-numbered bit lines, while the odd-numbered cell strings among the cell strings CS11' to CS1m' or CS21' to CS2m' arranged in the row direction can be connected to the odd-numbered bit lines respectively.

[0094] As one embodiment, at least one of the first memory cells MC1 to the nth memory cell MCn can be used as a dummy memory cell. For example, at least one dummy memory cell can be provided to reduce the electric field between the source selection transistor SST and the memory cells MC1 to MCp. Alternatively, at least one dummy memory cell can be provided to reduce the electric field between the drain selection transistor DST and the memory cells MCp+1 to MCn. Providing more dummy memory cells can improve the reliability of operation on the memory block BLKb; however, the size of the memory block BLKb may increase. Conversely, providing fewer memory cells can reduce the size of the memory block BLKb; however, the reliability of operation on the memory block BLKb may decrease.

[0095] To effectively control at least one pseudo-memory cell, each pseudo-memory cell can have a desired threshold voltage. Programming operations can be performed on all or some of the pseudo-memory cells before or after an erase operation on the memory block BLKb. When an erase operation is performed after a programming operation, the pseudo-memory cells can have the desired threshold voltage by controlling the voltage applied to the pseudo-word lines connected to each pseudo-memory cell.

[0096] Figure 6 This is a diagram illustrating programming operations according to an embodiment.

[0097] refer to Figure 6 Programming operations can include multiple programming cycles PL1 to PLn. A memory device can execute multiple programming cycles PL1 to PLn to program a selected memory cell into any of a plurality of programming states.

[0098] Each of the multiple programming cycles PL1 to PLn may include a programming voltage application step (PGM step) that applies a programming voltage and a verification step (Verify step) that determines whether a memory cell has been programmed by applying a verification voltage.

[0099] In the programming voltage application step, a programming voltage application operation can be performed to apply a programming voltage to a selected word line connected to the selected memory cell. Through the programming voltage application operation, the selected memory cell can be programmed to any of the first to nth (n is a natural number) programming states.

[0100] In one embodiment, the programming voltage can be determined using an incremental step pulse programming (ISPP) method. That is, the programming voltage level can be gradually increased or decreased with each programming cycle. The number of times the programming voltage is applied, the voltage level, the voltage application time, etc., used in each programming cycle can be determined in various ways according to the control of the memory controller.

[0101] A pass voltage can be applied to unselected word lines, which are word lines other than selected word lines. In one embodiment, a pass voltage of the same level can be applied to the unselected word lines. In another embodiment, the pass voltage can have different levels depending on the position of the word line.

[0102] Ground voltage can be applied as a programming-enabled voltage to selected bit lines connected to the memory cell to be programmed. Programming-disable voltage can be applied to unselected bit lines. Unselected bit lines can be bit lines connected to unselected memory cells (memory cells other than the memory cell to be programmed).

[0103] In the programming verification step, the memory device can apply a verification voltage to the selected word line and can apply a verification pass voltage to the unselected word line. The memory device can sense the voltage or current output through the bit lines connected to the memory cells connected to the selected word lines, and can determine whether the verification step passes or fails based on the sensing results.

[0104] In the verification step, a programming verification operation can be performed on at least one of the programming states from the first to the nth programming state. For example, when a memory cell to be programmed to the kth state (k is a natural number equal to or greater than 1 and equal to or less than n) is read as a cutoff cell by the verification voltage corresponding to the kth state, the programming verification operation for the kth state can be passed.

[0105] exist Figure 6 In this embodiment, when the selected memory cell is an MLC storing two data bits, the selected memory cell can be programmed into any of the programming states between the erase state and the first to third programming states. The number of data bits stored in the memory cell is not limited to this embodiment.

[0106] When executing the first programming cycle PLL, after applying the first programming voltage Vpgml, the first verification voltage V_vfy1 to the third verification voltage V_vfy3 can be applied sequentially to verify the programming state of multiple memory cells. At this time, memory cells whose target state is the first programming state can be verified by the first verification voltage V_vfy1, memory cells whose target state is the second programming state can be verified by the second verification voltage V_vfy2, and memory cells whose target state is the third programming state can be verified by the third verification voltage V_vfy3. The number of verification voltages is not limited to this embodiment.

[0107] The memory cell whose verification voltage V_vfy1 to V_vfy3 has been passed can be determined to have the target state and can then be programmed disabled in the second programming cycle PL2. A programming disable voltage can be applied to the bit line connected to the programmed disable memory cell. A second programming voltage Vpgm2, having a voltage level one unit voltage ΔVpgm higher than the first programming voltage Vpgm1, can be applied to the selected word line in the second programming cycle PL2.

[0108] Subsequently, the verification operation can be performed in the same manner as the verification operation of the first programming loop PL1. For example, a successful verification can indicate that the memory cell is read as a cutoff cell by the corresponding verification voltage.

[0109] As described above, when the memory device programs the MLC, the memory device can verify the memory cell with the corresponding programming state as the target state by using the first verification voltage V_vfy1 to the third verification voltage V_vfy3.

[0110] Figure 7 It's a diagram. Figure 2 A circuit diagram of another embodiment of any one of the memory blocks BLK1 to BLKz, BLKc.

[0111] refer to Figure 7A memory block BLKc may include multiple string SRs. These string SRs may be connected to multiple bit lines BL1 to BLn. Each string SR may include a source select transistor (SST), a memory cell (MC), and a drain select transistor (DST). The source select transistor (SST) of each string SR may be connected between the memory cell (MC) and the common source line (CSL). The source select transistors (SST) of multiple string SRs may be connected together to the common source line (CSL). The drain select transistor (DST) of each string SR may be connected between the memory cell (MC) and the bit line BL. The drain select transistors (DST) of multiple string SRs may be connected to multiple bit lines BL1 to BLn. In each string SR, multiple memory cells (MC) may be provided between the source select transistor (SST) and the drain select transistor (DST). In each string SR, the multiple memory cells (MC) may be connected in series.

[0112] In multiple serial source lines (SRs), memory cells MC located in the same order from the common source line CSL can be connected to a single word line. The memory cells MC of multiple serial source lines can be connected to multiple word lines WL1 to WLn.

[0113] Memory cells connected to the same word line in multiple serial strings (SRs) arranged in the row direction can form a page. For example, in multiple serial strings (SRs), memory cells connected to the first word line (WL1) can form the first page (PAGE1). Memory cells connected to the second word line (WL2) can form the second page (PAGE2). Memory cells connected to the third word line (WL3) can form the third page (PAGE3). Memory cells connected to the nth word line (WLn) can form the nth page (PAGEn).

[0114] The memory device can perform programming operations on selected memory cells in response to programming commands provided from the memory controller. Programming operations can be performed on a page-by-page basis, corresponding to each word line from WL1 to WLn.

[0115] In one embodiment, programming operations corresponding to programming commands from the memory controller can be performed sequentially on multiple pages based on the physical location of the word line corresponding to each page. For example, the memory controller can select pages PAGE1 through PAGEn as programming target pages. The memory controller can control the memory device to execute programming operations sequentially from pages PAGE1 to PAGEn.

[0116] This embodiment does not limit the order of programming operations on multiple pages, and the memory controller can control the memory device so that programming operations are executed sequentially from page n PAGEn to page 1.

[0117] Figure 8This diagram illustrates the threshold voltage distribution of a memory cell after programming operations on the memory cell connected to the selected word line are completed, but before programming operations on adjacent word lines are performed.

[0118] refer to Figure 8 Assume the memory cell is a TLC that stores three data bits. Figure 8 In the graph, the upper part illustrates the threshold voltage distribution of the memory cell connected to the m-th word line Wm after a programming operation is completed. The lower part illustrates the threshold voltage distribution of the memory cell connected to the (m+1)-th word line Wm+1 before a programming operation is performed on the memory cell connected to the (m+1)-th word line Wm+1. In one embodiment, the (m+1)-th word line Wm+1 may be adjacent to the m-th word line Wm and may be the word line to which a programming operation is performed.

[0119] refer to Figure 8 At the top of the graph, after the programming operation of the memory cell connected to the m-th word line Wm is completed, the memory cell connected to the m-th word line can have an erase state ER and a threshold voltage of any one of the first programming states PV1 to the seventh programming states PV7.

[0120] refer to Figure 8 The lower part of the graph includes over-erased cells, since the memory cells connected to the (m+1)th word line Wm+1 can include these cells before the programming operation is performed. An over-erased cell can be a memory cell with a threshold voltage level lower than the over-erased reference voltage Vdref. The over-erased reference voltage Vdref can be a voltage used to distinguish between the erase state ER and the over-erased state. The magnitude of the over-erased reference voltage Vdref can be the same as the lowest threshold voltage among the threshold voltages included in the erase state ER.

[0121] When a programming operation is performed on an over-erased cell, the threshold voltage of the memory cell connected to the adjacent word line can be shifted. (This is a reference.) Figure 9 Describe it.

[0122] Figure 9 This diagram illustrates the threshold voltage distribution of a memory cell after programming operations are performed on adjacent word lines following the completion of programming operations on the memory cell connected to the selected word line.

[0123] exist Figure 9In the graph, the upper part illustrates the threshold voltage distribution of the memory cell connected to the m-th word line Wm after the programming operation to the memory cell connected to the (m+1)-th word line Wm+1 is completed. The lower part of the graph illustrates the threshold voltage distribution of the memory cell connected to the (m+1)-th word line Wm+1 after the programming operation to the memory cell connected to the (m+1)-th word line Wm+1 is completed. In one embodiment, the (m+1)-th word line Wm+1 may be adjacent to the m-th word line Wm and may be the word line immediately following the m-th word line Wm that will be programmed.

[0124] refer to Figure 8 and Figure 9 After the programming operation of the memory cell connected to the m-th word line Wm is completed, a programming operation can be performed on the memory cell connected to the (m+1)-th word line Wm+1. An over-erasing unit may be included in the memory cell connected to the (m+1)-th word line Wm+1. In one embodiment, when a programming operation is performed on the over-erasing unit connected to the (m+1)-th word line Wm+1, Z-interference may occur in the memory cell connected to the m-th word line Wm. Specifically, when a programming operation is performed on the memory cell connected to the (m+1)-th word line Wm+1, the threshold voltage of the memory cell connected to the m-th word line Wm may shift based on the Z-interference occurring in the memory cell connected to the m-th word line Wm.

[0125] Furthermore, although not shown in the figure, when there are multiple over-erased cells among multiple memory cells connected to word lines, the charge trapped in the charge trapping layer of the memory cell adjacent to the over-erased cell may move to the charge trapping layer of the over-erased cell, and therefore, the threshold voltage of the adjacent memory cell adjacent to the over-erased cell may move.

[0126] Therefore, in order to reduce the degradation of the threshold voltage of the memory cell connected to the word line adjacent to the over-erased cell caused by the over-erased cell, it may be necessary to perform an operation to increase the threshold voltage of the over-erased cell to the threshold voltage of the erase state.

[0127] Figure 10 This is a diagram illustrating the pre-programming operation of memory cells connected to adjacent word lines according to an embodiment.

[0128] exist Figure 10In the graph, the upper part illustrates the threshold voltage distribution of the memory cell connected to the m-th word line Wm before a programming operation is performed on the memory cell connected to the m-th word line Wm among multiple word lines. The lower part illustrates the threshold voltage distribution of the memory cell connected to the (m+1)-th word line Wm+1 before a programming operation is performed on the memory cell connected to the (m+1)-th word line Wm+1. In one embodiment, the (m+1)-th word line Wm+1 may be adjacent to the m-th word line Wm and may be the word line immediately following the m-th word line Wm that is to be programmed.

[0129] refer to Figure 10 A pre-programming operation can be performed on the memory cell connected to the (m+1)th word line Wm+1 before performing a programming operation on the memory cell connected to the m-th word line Wm. The pre-programming operation can be an operation that increases the threshold voltage of the over-erased cell in the memory cell connected to the adjacent word line to the threshold voltage of the erase state before performing a programming operation on the selected word line. The adjacent word line can be the word line adjacent to the selected word line.

[0130] In one embodiment, the memory device may perform a pre-programming operation to increase the threshold voltage of the over-erased cell in the memory cell connected to the (m+1)th word line Wm+1 to an over-erased reference voltage Vdref or higher before performing a programming operation on the memory cell connected to the m-th word line Wm. The magnitude of the over-erased reference voltage Vdref may be the same as the lowest threshold voltage among the threshold voltages included in the erase state ER.

[0131] For reference Figure 10 The threshold voltage degradation caused by over-erasing cells can be improved by performing a pre-programming operation on memory cells connected to adjacent word lines before performing a programming operation on memory cells connected to selected word lines.

[0132] Figure 11 It is a flowchart illustrating the pre-programming operation and the programming operation according to an embodiment.

[0133] In step S1101, the memory device may receive a programming command from the memory controller. The programming command may be a command to perform a programming operation on a memory cell connected to multiple word lines.

[0134] In step S1103, the memory device may perform a pre-programming operation on the memory cells connected to the (m+1)th word line in response to a programming command from the memory controller. The (m+1)th word line may be adjacent to a selected word line. The pre-programming operation may be an operation that increases the threshold voltage of the over-erased cell in the memory cell connected to the (m+1)th word line to the threshold voltage of the erase state.

[0135] In step S1105, the memory device can perform programming operations on the memory cell connected to the m-th word line.

[0136] In step S1107, the memory device can determine whether the programming operation corresponding to the programming command received from the memory controller has been completed. When the programming operation is completed, the programming operation can be terminated. When the programming operation is not completed, the memory device can start from step S1103 to perform a programming operation on the memory cell connected to the next word line of the selected word line (step S1109).

[0137] Figure 12 This is a diagram illustrating the over-erasing unit sensing operation and pre-programming operation according to an embodiment.

[0138] Before performing a programming operation on the memory cells connected to the selected word line, the memory device can perform an over-erased cell sensing operation called "deep erase cell sensing," which senses over-erased cells among the memory cells connected to adjacent word lines. After completing the over-erased cell sensing operation "deep erase cell sensing," the memory device can perform a pre-programming operation on the over-erased cells.

[0139] In the over-erasure cell sensing operation "deep erase cell sensing", the memory device can apply an over-erasure verification voltage Vdvfy to adjacent word lines and can also apply a pass voltage to word lines other than adjacent word lines. The magnitude of the over-erasure verification voltage Vdvfy can be the same as the magnitude of the lowest threshold voltage among the threshold voltages of the erase state.

[0140] The memory device can sense the voltage or current output by the bit line connected to the memory cell connected to the adjacent word line, and can determine whether each memory cell connected to the adjacent word line is an over-erased cell based on the sensing results.

[0141] In the over-erasure cell sensing operation "deep erase cell sensing," the memory device can apply a bit line precharge voltage to the bit line connected to each memory cell connected to an adjacent word line, and can apply an over-erasure verification voltage Vdvfy to the adjacent word lines. Among the memory cells connected to adjacent word lines, memory cells with a threshold voltage lower than the over-erasure verification voltage Vdvfy can become on cells. Among the memory cells connected to adjacent word lines, memory cells with a threshold voltage higher than the over-erasure verification voltage Vdvfy can become off cells. In this case, current can flow through the bit lines connected to the on cells, while current may not flow through the bit lines connected to the off cells. The memory device can sense the current flowing through each bit line. The memory device can determine that memory cells connected to bit lines through which current flows are over-erased cells. The memory device can determine that memory cells connected to bit lines through which current does not flow are not in an over-erased state. Pre-programming operations on memory cells determined not to be over-erased cells can be disabled. Therefore, a blocking voltage used to disable preprogramming during preprogramming operations can be applied to the bit line of a memory cell connected to a memory cell that is determined not to be an over-erased cell.

[0142] After the "deep erase cell sensing" operation, which senses over-erased cells connected to adjacent word lines, is completed, the memory device can perform a pre-programming operation on the over-erased cells connected to adjacent word lines.

[0143] refer to Figure 12 The pre-programming operation may include multiple pre-programming cycles Pre-PL1 to Pre-PLn. The memory device may execute multiple pre-programming cycles Pre-PL1 to Pre-PLn to perform a pre-programming operation that increases the threshold voltage of the over-erased cell in the memory cell connected to the adjacent word line adjacent to the selected word line to the threshold voltage of the erase state.

[0144] Each programming cycle in the multiple pre-programming cycles Pre-PL1 to Pre-PLn may include a pre-programming voltage application step, “Pre-PGM step,” that applies a pre-programming voltage, and an over-erasure verification step, “deep erase verification step,” that determines whether a memory cell has been programmed by applying an over-erasure verification voltage, Vdvfy.

[0145] In the "Pre-PGM step" of the pre-programming voltage application process, a pre-programming voltage application operation can be performed to apply a pre-programming voltage to adjacent word lines. Through the pre-programming voltage application operation, the threshold voltage of the erase cell can be increased to the threshold voltage of the erase state.

[0146] In one embodiment, the preprogramming voltage can be determined using an incremental step pulse programming (ISPP) method. That is, the level of the preprogramming voltage can be progressively increased with each repetition of the preprogramming cycle. The number of times the preprogramming voltage is applied, the voltage level, the voltage application time, etc., used in each preprogramming cycle can be determined in various ways according to the control of the memory controller.

[0147] In the over-erasure verification step, the "deep erase verification step", the memory device can apply the over-erasure verification voltage Vdvfy to adjacent word lines and can apply the pass voltage to word lines other than adjacent word lines.

[0148] The memory device can sense the voltage or current output by the bit lines connected to the memory cells connected to adjacent word lines, and can determine whether the over-erasure verification step, the "deep erase verification step," passes or fails based on the sensing results. Specifically, the over-erasure verification operation passes when a cell is read as a cutoff cell in the "deep erase verification step."

[0149] In one embodiment, when executing the first pre-programming cycle Pre-PL1, after applying the first programming voltage Vpre-pgml to the adjacent word line, an over-erasure verification voltage Vdvfy can be applied to the adjacent word line to verify the state of the over-erased cell. Memory cells that pass verification based on the over-erasure verification voltage Vdvfy can be determined as having an erased state, and pre-programming operations can be disabled in subsequent pre-programming cycles. A programming disable voltage can be applied to the bit line connected to the memory cell whose pre-programming operation is disabled.

[0150] In one embodiment, the over-erased cell sensing operation "deep erased cell sensing" can be omitted. When the over-erased cell sensing operation "deep erased cell sensing" is omitted, the memory device may not be able to identify over-erased cells connected to adjacent word lines before performing pre-programming operations. Therefore, the memory device can perform pre-programming operations on all memory cells connected to adjacent word lines during the pre-programming operation. Specifically, the memory device can perform a pre-programming operation comprising multiple pre-programming cycles Pre-PL1 to Pre-PLn on all memory cells connected to adjacent word lines. During the pre-programming operation, a threshold voltage indicating an erased state can be determined for memory cells that have passed through the over-erased verification step in each pre-programming cycle. Pre-programming operations can be disabled in subsequent pre-programming cycles for memory cells that have passed through the over-erased verification step. A programming disable voltage can be applied to the bit line connected to the memory cell that is disabled for pre-programming operations.

[0151] In one embodiment, the over-erasure verification step, "deep erase verification step," can be omitted during the pre-programming operation. In this case, the pre-programming operation may not include multiple pre-programming cycles Pre-PL1 to Pre-PLn. That is, after completing the over-erasure cell sensing operation, the memory device can apply a predetermined pre-programming voltage to adjacent word lines. At this time, the level of the pre-programming voltage can be preset to a level that can increase the threshold voltage of the over-erasure cell to the threshold voltage level of the erase state. A programming disable voltage can be applied to the bit lines connected to memory cells that are not over-erasure cells.

[0152] In one embodiment, the over-erasure cell sensing operation "deep erase cell sensing" and the over-erasure verification step "deep erase verification step" of the pre-programming operation can be omitted. That is, before performing a programming operation on the memory cell connected to the selected word line, the memory device can apply a pre-programming voltage to the memory cell connected to the adjacent word line. Specifically, the memory device can apply a predetermined pre-programming voltage to the adjacent word line. At this time, the level of the pre-programming voltage can be set to a level that can increase the threshold voltage of the over-erasure cell to the threshold voltage of the erase state.

[0153] Figure 13 It is a diagram illustrating the sequence of pre-programming and programming operations for each word line according to an embodiment.

[0154] refer to Figure 13 Programming operations can be performed sequentially, starting from the memory cell connected to the m-th word line Wm among the memory cells connected to multiple word lines.

[0155] Before performing a programming operation on a memory cell connected to the m-th word line Wm, an over-erasing cell sensing operation can be performed at t1 to sense an over-erased cell connected to the (m+1)-th word line Wm+1, wherein the threshold voltage of the over-erased cell is lower than the threshold voltage of the erase state. The (m+1)-th word line Wm+1 may be adjacent to the m-th word line Wm.

[0156] When the over-erased cell sensing operation of the memory cell connected to the (m+1)th word line Wm+1 is completed, a pre-programming operation of the over-erased cell in the memory cell connected to the (m+1)th word line Wm+1 can be performed at t2. The pre-programming operation can be an operation of increasing the threshold voltage of the over-erased cell to the threshold voltage of the erase state.

[0157] When the pre-programming operation on the memory cell connected to the (m+1)th word line Wm+1 is completed, the programming operation on the memory cell connected to the mth word line Wm can be performed at t3.

[0158] When the programming operation of the memory cell connected to the m-th word line Wm is completed, an over-erasure cell sensing operation can be performed at t4 on the memory cell connected to the (m+2)-th word line Wm+2. The (m+2)-th word line Wm+2 can be adjacent to the (m+1)-th word line Wm+1.

[0159] When the over-erasing cell sensing operation of the memory cell connected to the (m+2)th word line Wm+2 is completed, the pre-programming operation of the over-erasing cell in the memory cell connected to the (m+2)th word line Wm+2 can be performed at t5.

[0160] When the pre-programming operation on the memory cell connected to the (m+2)th word line Wm+2 is completed, the programming operation on the memory cell connected to the (m+1)th word line Wm+1 can be performed at t6.

[0161] For reference Figure 13 The memory device can perform an erase cell sensing operation and a pre-programming operation on memory cells connected to adjacent word lines, and then perform a programming operation on memory cells connected to the selected word line. The adjacent word line can be a word line adjacent to the selected word line.

[0162] Figure 14 It is a diagram illustrating the sequence of pre-programming and programming operations for each word line according to another embodiment.

[0163] refer to Figure 14 Programming operations can be performed sequentially, starting from the memory cell connected to the m-th word line Wm among the memory cells connected to multiple word lines.

[0164] Before performing a programming operation on a memory cell connected to the m-th word line Wm, an over-erasing cell sensing operation can be performed at t1' to sense an over-erased cell connected to the (m+1)-th word line Wm+1, wherein the threshold voltage of the over-erased cell is lower than the threshold voltage of the erase state. The (m+1)-th word line Wm+1 may be adjacent to the m-th word line Wm.

[0165] When the over-erased cell sensing operation of the memory cell connected to the (m+1)th word line Wm+1 is completed, a pre-programming operation of the over-erased cell in the memory cell connected to the (m+1)th word line Wm+1 can be performed at t2'. The pre-programming operation can be an operation that increases the threshold voltage of the over-erased cell to the threshold voltage of the erase state.

[0166] When the pre-programming operation of the over-erased cell connected to the memory cell of word line (m+1) Wm+1 is completed, an over-erased cell sensing operation of sensing the over-erased cell connected to the memory cell of word line (m+2) Wm+2 can be performed at t3'. Word line (m+2) Wm+2 can be adjacent to word line (m+1) Wm+1.

[0167] When the over-erasing cell sensing operation of the memory cell connected to the (m+2)th word line Wm+2 is completed, the pre-programming operation of the over-erasing cell in the memory cell connected to the (m+2)th word line Wm+2 can be performed at t4'.

[0168] When the pre-programming operation on the memory cell connected to the (m+2)th word line Wm+2 is completed, the programming operation on the memory cell connected to the mth word line Wm can be performed at t5'.

[0169] When the programming operation on the memory cell connected to the m-th word line Wm is completed, the programming operation on the memory cell connected to the (m+1)-th word line Wm+1 can be performed at t6'.

[0170] When the programming operation of the memory cell connected to the (m+1)th word line Wm+1 is completed, an over-erasure cell sensing operation of the memory cell connected to the (m+3)th word line Wm+3 can be performed at t7'. The (m+3)th word line Wm+3 can be adjacent to the (m+2)th word line Wm+2.

[0171] When the over-erasure cell sensing operation of the memory cell connected to the (m+3)th word line Wm+3 is completed, the pre-programming operation of the over-erasure cell in the memory cell connected to the (m+3)th word line Wm+3 can be performed at t8'.

[0172] When the pre-programming operation on the memory cell connected to the (m+3)th word line Wm+3 is completed, an over-erasure cell sensing operation on the memory cell connected to the (m+4)th word line Wm+4 can be performed at t9'. The (m+4)th word line Wm+4 can be adjacent to the (m+3)th word line Wm+3.

[0173] When the over-erasing cell sensing operation of the memory cell connected to the (m+4)th word line Wm+4 is completed, the pre-programming operation of the over-erasing cell in the memory cell connected to the (m+4)th word line Wm+4 can be performed at t10'.

[0174] When the pre-programming operation on the memory cell connected to the (m+4)th word line Wm+4 is completed, the programming operation on the memory cell connected to the (m+2)th word line Wm+2 can be performed at t11'.

[0175] When the programming operation of the memory cell connected to the (m+2)th word line Wm+2 is completed, the programming operation of the memory cell connected to the (m+3)th word line Wm+3 can be performed at t12'.

[0176] For reference Figure 14 The memory device can perform an erase cell sensing operation and a pre-programming operation on memory cells connected to the two word lines most adjacent to the selected word line, and then perform a programming operation on the memory cells connected to the selected word line.

[0177] The number of word lines for memory cells that have undergone erase cell sensing and pre-programming operations before being programmed to the memory cell connected to the selected word line is not referenced. Figures 13 to 14 Limitations of the described embodiments. In other words, before performing a programming operation on a memory cell connected to a selected word line, an erase cell sensing operation and a pre-programming operation can be performed on a memory cell connected to three or more adjacent word lines.

[0178] In one embodiment, before performing a programming operation on the memory cells connected to the selected word line, the memory device may perform an erase cell sensing operation and a pre-programming operation on the memory cells connected to all word lines except the selected word line, and then perform a programming operation on the memory cells connected to the selected word line.

[0179] Figure 15 This is a flowchart illustrating the operation of a memory device according to an embodiment.

[0180] In step S1501, the memory device may receive a programming command from the memory controller. The programming command may be a command used to perform programming operations on memory cells connected to multiple word lines.

[0181] In step S1503, the memory device may perform an over-erased cell sensing operation on the memory cell connected to the (m+1)th word line in response to a programming command from the memory controller. The (m+1)th word line may be adjacent to a selected word line. The over-erased cell sensing operation may be an operation that senses an over-erased cell in the memory cell connected to the (m+1)th word line whose threshold voltage is lower than the threshold voltage of the erase state.

[0182] In step S1505, the memory device can determine whether there is an over-erased cell among the memory cells connected to the (m+1)th word line.

[0183] In step S1507, when an over-erased cell exists in the memory cell connected to the (m+1)th word line, the memory device can perform a pre-programming operation on the over-erased cell connected to the (m+1)th word line. The pre-programming operation can be an operation that increases the threshold voltage of the memory cell with an over-erased state threshold voltage connected to the adjacent word line to the erase state threshold voltage. When no over-erased cell exists in the memory cell connected to the (m+1)th word line, step S1507 can be omitted.

[0184] In step S1509, a programming operation can be performed on the memory cell connected to the m-th word line.

[0185] In step S1511, the memory device can determine whether all programming operations corresponding to the programming commands of the memory controller have been completed.

[0186] In step S1513, when all programming operations corresponding to the programming command are not completed, the memory device can select a memory cell connected to the (m+1)th word line as the programming target memory cell. After the programming operation on the memory cell connected to the mth word line is completed, the memory device can start from step S1503 to perform programming operations on the memory cell connected to the (m+1)th word line (i.e., the next word line).

[0187] Once all programming operations are complete, the memory device can terminate the programming operation corresponding to the programming command from the memory controller.

[0188] Figure 16 This is a flowchart illustrating the operation of a memory device according to another embodiment.

[0189] In step S1601, the memory device may receive a programming command from the memory controller. The programming command may be a command to perform a programming operation on a memory cell connected to multiple word lines.

[0190] In step S1603, the memory device may perform an over-erased cell sensing operation on the memory cell connected to the (m+1)th word line in response to a programming command from the memory controller. The (m+1)th word line may be adjacent to a selected word line. The over-erased cell sensing operation may be an operation that senses an over-erased cell in the memory cell connected to the (m+1)th word line whose threshold voltage is lower than the threshold voltage of the erase state.

[0191] In step S1605, the memory device can determine whether there is an over-erased cell among the memory cells connected to the (m+1)th word line.

[0192] In step S1607, when an over-erased cell exists among the memory cells connected to the (m+1)th word line, the memory device can perform a pre-programming operation on the over-erased cells connected to the (m+1)th word line. The pre-programming operation can be an operation that increases the threshold voltage of the memory cells connected to adjacent word lines that have an over-erased state threshold voltage to the erase state threshold voltage. When no over-erased cell exists among the memory cells connected to the (m+1)th word line, step S1607 can be omitted.

[0193] In step S1609, the memory device may perform an erase cell sensing operation on the memory cell connected to the (m+2)th word line. The (m+2)th word line may be adjacent to the (m+1)th word line.

[0194] In step S1611, the memory device can determine whether there is an over-erased cell among the memory cells connected to the (m+2)th word line.

[0195] In step S1613, when an over-erased cell exists in the memory cell connected to the (m+2)th word line, the memory device can perform a pre-programming operation on the over-erased cell connected to the (m+2)th word line. When no over-erased cell exists in the memory cell connected to the (m+2)th word line, step S1613 can be omitted.

[0196] In step S1615, a programming operation can be performed on the memory cell connected to the m-th word line.

[0197] In step S1617, a programming operation can be performed on the memory cell connected to the (m+1)th word line.

[0198] In step S1619, the memory device can determine whether all programming operations corresponding to the programming commands of the memory controller have been completed.

[0199] In step S1621, when all programming operations corresponding to the programming command are not completed, the memory device can select a memory cell connected to the (m+2)th word line as the programming target memory cell. That is, since the programming operations for the memory cells connected to the m-th word line and the (m+1)th word line adjacent to the m-th word line are completed, the memory device can select a memory cell connected to the (m+2)th word line adjacent to the (m+1)th word line as the programming target memory cell. The memory device can begin performing programming operations on the memory cell connected to the (m+2)th word line from step S1603.

[0200] Once all programming operations are complete, the memory device can terminate the programming operation corresponding to the programming command from the memory controller.

[0201] Figure 17 It's a diagram. Figure 1 A diagram of another embodiment of the memory controller.

[0202] refer to Figure 17 The memory controller 1000 can connect to both a host and a memory device. The memory controller 1000 can be configured to access the memory device in response to requests from the host. For example, the memory controller 1000 can be configured to control write, read, erase, and background operations on the memory device. The memory controller 1000 can be configured to provide an interface between the memory device and the host. The memory controller 1000 can be configured to drive firmware for controlling the memory device.

[0203] The memory controller 1000 may include a processor 1010, a memory buffer 1020, an error correction circuit (ECC) 1030, a host interface 1040, a buffer controller 1050, a memory interface 1060, and a bus 1070.

[0204] Bus 1070 can be configured to provide a channel between components of memory controller 1000.

[0205] Processor 1010 can control the overall operation of memory controller 1000 and execute logical operations. Processor 1010 can communicate with an external host through host interface 1040 and with memory devices through memory interface 1060. Furthermore, processor 1010 can communicate with memory buffer 1020 through buffer controller 1050. Processor 1010 can control the operation of memory buffer 1020 as a storage device for operation memory, cache memory, or buffer memory.

[0206] Processor 1010 can perform FTL functions. Processor 1010 can convert LBAs provided by the host to PBAs via FTL. FTL can use a mapping table to receive LBAs and convert LBAs to PBAs. The address mapping method of the flash translation layer can include various methods based on mapping cells. Representative address mapping methods can include page mapping methods, block mapping methods, and hybrid mapping methods.

[0207] Processor 1010 can be configured to randomize data received from the host. For example, processor 1010 can randomize data received from the host using a randomization seed. The randomized data can be provided to a memory device as data to be stored and can be programmed into a memory cell array.

[0208] Processor 1010 can be configured to derandomize data received from the memory device during a read operation. For example, processor 1010 can use a derandomization seed to derandomize data received from the memory device. The derandomized data can then be output to the host.

[0209] As an example, the processor 1010 can perform randomization and derandomization via driver software or firmware.

[0210] The memory buffer 1020 can be used as the operating memory, cache memory, or buffer memory of the processor 1010. The memory buffer 1020 can store code and commands executed by the processor 1010. The memory buffer 1020 can store data processed by the processor 1010. The memory buffer 1020 may include static RAM (SRAM) or dynamic RAM (DRAM).

[0211] ECC 1030 can perform error correction. ECC 1030 can perform error correction encoding (ECC encoding) based on data to be written to the memory device via memory interface 1060. The error-corrected data can be transferred to the memory device via memory interface 1060. ECC 1030 can perform error correction decoding (ECC decoding) on ​​data received from the memory device via memory interface 1060. For example, ECC 1030 can be included as a component of memory interface 1060 within memory interface 1060.

[0212] The host interface 1040 can be configured to communicate with an external host under the control of the processor 1010. The host interface 1040 can be configured to perform communication using at least one of various communication methods, such as Universal Serial Bus (USB), Serial AT Accessory (SATA), Serial Attached SCSI (SAS), High Speed ​​Chip Interconnect (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI Rapid), Non-Volatile Memory Rapid (NVMe), Universal Flash Memory (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Low Load DIMM (LRDIMM).

[0213] The buffer controller 1050 can be configured to control the memory buffer 1020 under the control of the processor 1010.

[0214] The memory interface 1060 can be configured to communicate with a memory device under the control of the processor 1010. The memory interface 1060 can transmit commands, addresses, and data with the memory device through channels.

[0215] For example, memory controller 1000 may not include memory buffer 1020 and buffer controller 1050.

[0216] For example, processor 1010 can control the operation of memory controller 1000 using code. Processor 1010 can load code from a non-volatile memory device (e.g., read-only memory) configured to reside within memory controller 1000. As another example, processor 1010 can load code from a memory device via memory interface 1060.

[0217] For example, the bus 1070 of the memory controller 1000 can be divided into a control bus and a data bus. The data bus can be configured to send data within the memory controller 1000, and the control bus can be configured to send control information, such as commands and addresses, within the memory controller 1000. The data bus and the control bus can be separate from each other and must not interfere with or affect each other. The data bus can be connected to the host interface 1040, the buffer controller 1050, the ECC 1030, and the memory interface 1060. The control bus can be connected to the host interface 1040, the processor 1010, the buffer controller 1050, the memory buffer 1020, and the memory interface 1060.

[0218] Figure 18 This is a block diagram illustrating a memory card system employing a storage device according to an embodiment of the present disclosure.

[0219] refer to Figure 18 The memory card system 2000 includes a memory controller 2100, a memory device 2200, and a connector 2300.

[0220] Memory controller 2100 can be connected to memory device 2200. Memory controller 2100 can be configured to access memory device 2200. For example, memory controller 2100 can be configured to control read, write, erase, and background operations of memory device 2200. Memory controller 2100 can be configured to provide an interface between memory device 2200 and a host. Memory controller 2100 can be configured to drive firmware for controlling memory device 2200. Memory controller 2100 can be referenced... Figure 1 The memory controller 200 described is implemented in the same way.

[0221] For example, memory controller 2100 may include components such as random access memory (RAM), processor, host interface, memory interface, and ECC.

[0222] The memory controller 2100 can communicate with external devices via connector 2300. The memory controller 2100 can communicate with external devices (e.g., a host) according to specific communication standards. For example, the memory controller 2100 can be configured to communicate with external devices via at least one of various communication standards, such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and NVMe. For example, connector 2300 can be defined by at least one of the various communication standards described above.

[0223] For example, the memory device 2200 may be composed of various non-volatile memory elements such as electrically erasable programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin torque magnetic RAM (STT-MRAM).

[0224] The memory controller 2100 and the memory device 2200 can be integrated into a single semiconductor device to configure a memory card. For example, the memory controller 2100 and the memory device 2200 can be integrated into a single semiconductor device to configure memory cards such as PC cards (Personal Computer Memory Card International Association (PCMCIA)), compact flash memory cards (CF), smart media cards (SM or SMC), memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro or eMMC), SD cards (SD, miniSD, microSD or SDHC), and universal flash memory (UFS).

[0225] Figure 19 This is a block diagram illustrating a solid-state drive (SSD) system using a storage device according to an embodiment of the present disclosure.

[0226] refer to Figure 19 The SSD system 3000 may include a host 3100 and an SSD 3200. The SSD 3200 may exchange signals with the host 3100 through a signal connector 3001 and may receive power (PWR) through a power connector 3002. The SSD 3200 may include an SSD controller 3210, multiple flash memory (NVMs) 3221 to 322n, an auxiliary power supply device 3230, and a cache memory 3240.

[0227] According to embodiments of this disclosure, the SSD controller 3210 can execute reference... Figure 1 The functions of the memory controller 200 are described.

[0228] SSD controller 3210 can control multiple flash memory modules 3221 to 322n in response to signals received from host 3100. For example, the signal can be based on the interface between host 3100 and SSD 3200. For example, the signal can be defined by at least one of the following interfaces: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and NVMe.

[0229] Auxiliary power supply device 3230 can be connected to host 3100 via power connector 3002. Auxiliary power supply device 3230 can receive power (PWR) from host 3100 and can be charged. When power supply from host 3100 is insufficient, auxiliary power supply device 3230 can provide power to SSD 3200. For example, auxiliary power supply device 3230 can be located inside SSD 3200 or external to SSD 3200. For example, auxiliary power supply device 3230 can be located on the motherboard and can provide auxiliary power to SSD 3200.

[0230] Buffer memory 3240 can operate as a buffer memory for SSD 3200. For example, buffer memory 3240 can temporarily store data received from host 3100, or data received from multiple flash memory modules 3221 to 322n, or it can temporarily store metadata (e.g., mapping tables) of flash memory modules 3221 to 322n. Buffer memory 3240 can include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0231] Figure 20 This is a block diagram illustrating a user system employing a storage device according to an embodiment of the present disclosure.

[0232] refer to Figure 20 The user system 4000 may include an application processor 4100, a memory module 4200, a network module 4300, a storage module 4400, and a user interface 4500.

[0233] Application processor 4100 can drive components, operating system (OS), user programs, etc., included in user system 4000. For example, application processor 4100 may include controllers, interfaces, graphics engines, etc., that control components included in user system 4000. Application processor 4100 may be provided as a system-on-a-chip (SoC).

[0234] Memory module 4200 can operate as main memory, operational memory, buffer memory, or cache memory of user system 4000. Memory module 4200 may include volatile random access memory (such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM) or non-volatile random access memory (such as PRAM, ReRAM, MRAM, and FRAM). For example, application processor 4100 and memory module 4200 may be packaged on a package-on-package (POP) basis and may be provided as a single semiconductor package.

[0235] Network module 4300 can communicate with external devices. For example, network module 4300 can support wireless communications such as Code Division Multiple Access (CDMA), Global System for Mobile Communications (GSM), Wideband CDMA (WCDMA), CDMA-2000, Time Division Multiple Access (TDMA), LTE, WiMax, WLAN, UWB, Bluetooth, and Wi-Fi. For example, network module 4300 can be included in application processor 4100.

[0236] Storage module 4400 can store data. For example, storage module 4400 can store data received from application processor 4100. Alternatively, storage module 4400 can send data stored in storage module 4400 to application processor 4100. For example, storage module 4400 can be implemented as a non-volatile semiconductor memory element, such as phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), NAND flash memory, NOR flash memory, and 3D NAND flash memory. For example, storage module 4400 can be provided as a removable storage device (removable drive) such as a memory card, and as an external drive for user system 4000.

[0237] For example, storage module 4400 may include multiple non-volatile memory devices, and the multiple non-volatile memory devices may be connected to a reference. Figure 1 The memory device 100 described operates in the same manner. Storage module 4400 can be compared with the referenced... Figure 1 The storage device 50 described operates in the same manner.

[0238] User interface 4500 may include interfaces for inputting data or instructions to application processor 4100 or for outputting data to external devices. For example, user interface 4500 may include user input interfaces such as a keyboard, keypad, buttons, touch panel, touchscreen, touchpad, touch ball, camera, microphone, gyroscope sensor, vibration sensor, and piezoelectric element. User interface 4500 may include user output interfaces such as liquid crystal display (LCD), organic light-emitting diode (OLED) display device, active-matrix OLED (AMOLED) display device, LED, speaker, and monitor.

Claims

1. A memory device, comprising: Multiple memory cells are connected to each of multiple word lines; The peripheral circuitry is configured to perform programming operations on selected memory cells connected to selected word lines among the plurality of word lines; as well as Control logic is configured to control the peripheral circuitry to perform the programming operation on the selected memory cell after a pre-programming operation is performed. The pre-programming operation increases the threshold voltage of an over-erased cell connected to an adjacent word line, which has a threshold voltage lower than the erase state threshold voltage, to the erase state threshold voltage. The adjacent character line is the character line that is immediately adjacent to the selected character line; Before performing the pre-programming operation on the over-erasing unit, the control logic performs an over-erasing unit sensing operation; and The over-erasing unit sensing operation is described below: Sensing the threshold voltage of the adjacent memory cells; and The memory cell among the adjacent memory cells that has a threshold voltage lower than the over-erasure verification voltage is identified as the over-erasure cell.

2. The memory device of claim 1, wherein the adjacent memory cells are respectively connected to a plurality of bit lines. The control logic is configured, during the pre-programming operation, to control the peripheral circuitry to apply a pre-programming voltage to the adjacent word lines, apply a ground voltage to the bit lines connected to the over-erased cells, and apply a power supply voltage to the bit lines connected to memory cells other than the over-erased cells. The preprogramming voltage is configured to increase the threshold voltage of a memory cell having the threshold voltage of the over-erased state to the level of the threshold voltage of the erased state.

3. The memory device of claim 1, wherein the pre-programming operation comprises a plurality of programming loops. Each of the plurality of programming cycles includes a step of applying a pre-programming voltage to the adjacent memory cell and a verification step of checking whether the adjacent memory cell has been programmed to the erase state, and Each time the programming cycle increases, the pre-programmed voltage increases by a step voltage.

4. The memory device of claim 3, wherein the control logic is configured to control the peripheral circuitry to perform the verification step by using the over-erasure verification voltage in the verification step, and The over-erasure verification voltage has the same voltage level as the lowest threshold voltage among the threshold voltages of the erase state.

5. The memory device of claim 1, wherein the over-erasure verification voltage has the same voltage level as the lowest threshold voltage among the threshold voltages of the erase state.

6. The memory device of claim 1, wherein the control logic is configured to: control the peripheral circuitry to perform the programming operation on a memory cell connected to ...

7. The memory device of claim 1, wherein the control logic controls the peripheral circuitry to perform the programming operation on memory cells connected to the m-th word line (as the selected word line) and the (m+2)-th word line (as the adjacent word line) after performing the pre-programming operation on memory cells connected to the (m+1)-th word line and the (m+2)-th word line adjacent to the (m+1)-th word line; and when the programming operation on the memory cells connected to the (m+1)-th word line is completed, to perform the programming operation on memory cells connected to the (m+2)-th word line and the (m+3)-th word line after performing the pre-programming operation on memory cells connected to the (m+2)-th word line and the (m+4)-th word line adjacent to the (m+3)-th word line.

8. The memory device of claim 1, wherein the plurality of memory cells are included in a memory block, and The control logic is configured to perform the programming operation on the selected memory cell after performing the pre-programming operation on the memory cells among the plurality of memory cells included in the memory block that are connected to all word lines except the selected word line.

9. The memory device of claim 1, wherein the plurality of memory cells includes memory cells programmed into any of a plurality of programming states.

10. The memory device of claim 1, wherein the adjacent memory cells are respectively connected to a plurality of bit lines. The control logic is configured to, during the pre-programming operation, control the peripheral circuitry to apply a pre-programming voltage to the adjacent word lines and to apply a ground voltage to the plurality of bit lines. The preprogramming voltage is configured to increase the threshold voltage of a memory cell having the threshold voltage of the over-erased state to the level of the threshold voltage of the erased state.

11. A method of operating a memory device comprising a plurality of memory cells connected to each of a plurality of word lines and performing a programming operation on selected memory cells connected to selected word lines among the plurality of word lines, the method comprising: Performing an over-erasing unit sensing operation, the over-erasing unit sensing operation including: Sensing a threshold voltage of an adjacent memory cell connected to an adjacent word line, wherein the adjacent word line is a word line immediately adjacent to the selected word line; The memory cell among the adjacent memory cells that has a threshold voltage lower than the over-erasure verification voltage is identified as an over-erasure cell, wherein the over-erasure cell has an over-erasure state threshold voltage lower than the over-erasure state threshold voltage. After performing the over-erasure unit sensing operation, a pre-programming operation is performed on the over-erasure unit, which programs the threshold voltage of the over-erasure unit to the threshold voltage of the erase state; and After the pre-programming operation is performed on the over-erased unit, the programming operation is performed on the selected memory unit.

12. The method of claim 11, wherein the over-erasure verification voltage has the same voltage level as the lowest threshold voltage among the threshold voltages of the erase state.

13. The method of claim 11, wherein performing the pre-programming operation includes a pre-programming voltage application step of applying a pre-programming voltage to the adjacent memory cell and a verification step of checking whether the adjacent memory cell has been programmed to the erase state. The pre-programming operation includes multiple programming loops, each programming loop including the pre-programming voltage application step and the verification step, and Each time the programming cycle increases, the pre-programmed voltage increases by a step voltage.

14. The method of claim 13, wherein the verification step includes checking whether the adjacent memory cell has been programmed to the erase state by using the over-erasure verification voltage, and The over-erasure verification voltage has the same voltage level as the lowest threshold voltage among the threshold voltages of the erase state.

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