Circuit devices and solenoid control devices

Abstract

The circuit device and solenoid control device. The current sensing amplifier circuit of the circuit device includes: an amplifier; a first resistor disposed between one end of the shunt resistor (12) and a first node; a first switch disposed between the first node and a first input node; a second resistor disposed between the other end of the shunt resistor (12) and a second node; a second switch disposed between the second node and a second input node; a third resistor disposed between a constant voltage node and a third node; a third switch disposed between the third node and the first input node; a fourth resistor disposed between the constant voltage node and a fourth node; and a fourth switch disposed between the fourth node and the second input node.

Description

Technical Field

[0001] This invention relates to circuit devices and solenoid control devices. Background Technology

[0002] Patent document 1 discloses a current control device for a solenoid. The current control device includes: a first current monitoring circuit that detects the current flowing through the solenoid and feeds it back to the solenoid's current control circuit; and a second current monitoring circuit, connected in parallel with the first current monitoring circuit, that also detects the current flowing through the solenoid and feeds it back to the solenoid's current control circuit. When the second current monitoring circuit detects the current flowing through the solenoid, the first current monitoring circuit performs bias calibration. The first current monitoring circuit includes a switch that short-circuits the current sensing resistor during bias detection.

[0003] Patent Document 2 discloses a voltage detection device. The voltage detection device includes: a first switch that switches the voltage input to a first input section on and off; a second switch that switches the voltage input to a second input section on and off; a third switch that switches the connection between the first and second input sections on and off; and a control device. The first input section is connected to one end of a shunt resistor, and the second input section is connected to the other end of the shunt resistor. The control device detects the bias voltage of the differential amplifier circuit when the first and second switches are disconnected and the third switch is connected.

[0004] Patent Document 1: Japanese Patent Application Publication No. 2010-170434

[0005] Patent Document 2: Japanese Patent Application Publication No. 2017-161409

[0006] In patent documents 1 and 2, a switch is provided connecting the two ends of a shunt resistor. During bias detection, the two ends of the shunt resistor are short-circuited by turning on this switch. The switch is connected to the voltage across the shunt resistor. Therefore, if a high voltage or a negative voltage is input to one or the other end of the shunt resistor, a switch capable of withstanding these voltages is required. Summary of the Invention

[0007] One aspect of the present invention relates to a circuit device comprising: a current sensing amplifier circuit that detects a current flowing through a switching element, a shunt resistor, and the shunt resistor in an inductor connected in series between a first power node and a second power node; and a processing circuit that calculates a corrected current value of the current flowing through the shunt resistor based on the output of the current sensing amplifier circuit, the current sensing amplifier circuit comprising: an operational amplifier; a first resistor disposed between a first resistor node and a first node at one end of the shunt resistor; a first switch disposed between the first node and a first input node of the operational amplifier; a second resistor disposed between a second resistor node and a second node at the other end of the shunt resistor; a second switch disposed between the second node and a second input node of the operational amplifier; and a third... A resistor is disposed between the constant voltage node and the third node; a third switch is disposed between the third node and the first input node of the operational amplifier; a fourth resistor is disposed between the constant voltage node and the fourth node; and a fourth switch is disposed between the fourth node and the second input node of the operational amplifier. During current detection, the first and second switches are turned on, and the third and fourth switches are turned off. The processing circuit obtains the detected current value based on the output of the current sensing amplifier circuit. During bias detection, the first and second switches are turned off, and the third and fourth switches are turned on. The processing circuit obtains the bias value based on the output of the current sensing amplifier circuit. The processing circuit calculates the corrected current value based on the detected current value and the bias value.

[0008] Another aspect of the present invention relates to a solenoid control device, comprising: the aforementioned circuit arrangement; the switching element; the shunt resistor; and a solenoid serving as the inductor, wherein the solenoid is controlled according to the corrected current value. Attached Figure Description

[0009] Figure 1 These are examples of the structure of circuit devices and solenoid control devices.

[0010] Figure 2 This is an example of the basic structure of a current detection circuit.

[0011] Figure 3 It is a signal waveform diagram illustrating the operation of the current detection circuit.

[0012] Figure 4 This is a detailed structural example of the current detection circuit in the first embodiment.

[0013] Figure 5 It indicates the state of the switch during bias detection.

[0014] Figure 6This is a timing diagram of the current detection operation in the first embodiment.

[0015] Figure 7 It is the first error component that depends on the common-mode voltage during current sensing.

[0016] Figure 8 It is the second error component that depends on the common-mode voltage during current sensing.

[0017] Figure 9 It is the third error component that does not depend on the common-mode voltage during current sensing.

[0018] Figure 10 It is the error component during the bias detection period.

[0019] Figure 11 This is a detailed structural example of the circuit device in the second embodiment.

[0020] Figure 12 This is the first detailed structural example of the current detection circuit in the second embodiment.

[0021] Figure 13 This is a second detailed structural example of the current detection circuit in the second embodiment.

[0022] Figure 14 This is the first detailed structural example of a variable current circuit.

[0023] Figure 15 This is the second detailed structural example of a variable current circuit.

[0024] Figure 16 This is the step to determine the correction information.

[0025] Figure 17 This is a detailed structural example of the current detection circuit in the third embodiment.

[0026] Figure 18 This is a detailed structural example of a monitoring circuit.

[0027] Figure 19 This is an explanatory diagram of the calibration parameters.

[0028] Figure 20 This is an explanatory diagram of the calibration parameters.

[0029] Figure 21 This is the first timing diagram of the current detection operation in the third embodiment.

[0030] Figure 22 This is the second timing diagram of the current detection operation in the third embodiment.

[0031] Figure 23 This is the third timing diagram of the current detection operation in the third embodiment.

[0032] Label Explanation

[0033] 10 Solenoid control device; 11 Inductor; 12 Shunt resistor; 100 Circuit device; 110 Current detection circuit; 115 Processing circuit; 120 Current sensing amplifier circuit; 121 Correction circuit; 130 Level shifter circuit; 131 Current source; 132 Variable current source; 132a, 132b Variable current source; 135, 136 Variable current circuit; 140 A / D conversion circuit; 150 Control circuit; 160 Drive circuit; 170 Storage circuit; 180 Switching element; 190 Monitoring circuit; DA diode; DT1~DT n during the first to nth detection period; IN second current; IP first current; IPC correction current; MT monitoring period; NIN second input node; NIP first input node; NMONN second resistor node; NMONP first resistor node; OPA operational amplifier; RFN feedback resistor; RIN second resistor; RIP first resistor; RIPV first variable resistor; RNT fourth resistor; RPT third resistor; RPTV second variable resistor; SNC second switch; SNT fourth switch; SPC first switch; SPT third switch; SPWM PWM signal; VM monitoring voltage; VQ detection voltage; VREFM reference voltage. Detailed Implementation

[0034] The preferred embodiments of the present invention will now be described in detail. The embodiments described below do not unduly limit the scope of the claims, and not all structures described in these embodiments are necessarily essential components.

[0035] 1. Solenoid control device, circuit device

[0036] Figure 1 This is a structural example of the circuit device of this embodiment and the solenoid control device including the circuit device. Furthermore, an example of using the circuit device of this embodiment for solenoid control will be described below. However, the circuit device of this embodiment can be applied to various devices that detect current controlled by a switch.

[0037] The solenoid controller 10 includes a shunt resistor 12, an inductor 11, a resistor RA, a capacitor CA, a diode DA, and a circuit device 100.

[0038] Inductor 11 is the coil of a solenoid. The solenoid has a coil and a plunger that can move axially along the coil. The plunger is also called a movable iron core. The displacement of the plunger relative to the coil is controlled by the current flowing through the coil.

[0039] Shunt resistor 12, resistor RA, and inductor 11 are connected in series between node NVLS and ground node. Specifically, one end of shunt resistor 12 is connected to node NVLS, and the other end is connected to one end of resistor RA. The other end of resistor RA is connected to one end of inductor 11. The other end of inductor 11 is connected to ground node.

[0040] Diode DA is positioned between node NVLS and the ground node, with the direction from the ground node to the resistor node NVLS as the positive direction. Specifically, the anode of diode DA is connected to the ground node, and the cathode is connected to node NVLS. Capacitor CA is connected in parallel with resistor RA and inductor 11. Specifically, one end of capacitor CA is connected to one end of resistor RA, and the other end is connected to the ground node.

[0041] The circuit device 100 detects the current flowing through the inductor 11 and controls the current flowing through the inductor 11 based on the detection result. The circuit device 100 includes a current detection circuit 110, a processing circuit 115, a drive circuit 160, a storage circuit 170, a switching element 180, and terminals TVDD, TVLS, TMONP, and TMONN. The circuit device 100 is, for example, an integrated circuit device in which multiple circuit elements are integrated on a semiconductor substrate. Each terminal is, for example, a pad for the integrated circuit device or a terminal of a package housing the integrated circuit device. Alternatively, the switching element 180 may be disposed externally to the circuit device 100.

[0042] A switching element 180 is disposed between power node NVDD and node NVLS. Specifically, the switching element 180 is a P-type transistor. The source of the P-type transistor is connected to terminal TVDD, and the drain is connected to terminal TVLS. Terminal TVDD is connected to power node NVDD, supplying power supply voltage VDD from outside the circuit device 100. One end of the shunt resistor 12 is connected to node NVLS and terminal TVLS.

[0043] The current detection circuit 110 detects the current flowing through the inductor 11 by detecting the current flowing through the shunt resistor 12. The current detection circuit 110 includes a current sensing amplifier circuit 120 and a level shifting circuit 130.

[0044] The voltage MONP at one end of the shunt resistor 12 is input to the current sensing amplifier circuit 120 from the first resistor node NMONP via terminal TMONP, and the voltage MONP at the other end of the shunt resistor 12 is input to the current sensing amplifier circuit 120 from the second resistor node NMONN via terminal TMONN. The first resistor node NMONP is the node connected to one end of the shunt resistor 12. The second resistor node NMONN is the node connected to the other end of the shunt resistor 12. The current sensing amplifier circuit 120 detects the potential difference across the shunt resistor 12 based on voltage MONP and voltage MONP, thereby detecting the current flowing through the shunt resistor 12, and outputs the detection voltage VQ as a result. In addition, two terminals TVLS and TMONP are connected to one end of the shunt resistor 12. The node connected to terminal TVLS is designated as node NTVLS, and the node connected to terminal TMONP is designated as resistor node NMONP. Voltages VLS and MONP are both voltages at one end of the shunt resistor 12.

[0045] The level shifting circuit 130 shifts the voltage at the input node of the operational amplifier included in the current-sensing amplifier circuit 120 by supplying current to that input node. The level shifting circuit 130 variably controls the current supplied to the input node of the operational amplifier based on the voltage VLS at one end of the shunt resistor 12, thereby maintaining the voltage at the input node of the operational amplifier at a constant value. Further details regarding the current-sensing amplifier circuit 120 and the level shifting circuit 130 will be described later.

[0046] The processing circuit 115 outputs a PWM signal SPWM for PWM control of the switching element 180 based on the detected voltage VQ. The processing circuit 115 includes an A / D conversion circuit 140 and a control circuit 150.

[0047] The A / D conversion circuit 140 performs A / D conversion on the detected voltage VQ to obtain the detected data ADQ. Specifically, the A / D conversion circuit 140 performs A / D conversion at a sampling frequency higher than the switching frequency of the switching element 180 to obtain the detected data ADQ when the switching element 180 is turned on and the detected data ADQ when the switching element 180 is turned off.

[0048] The control circuit 150 outputs a PWM signal SPWM for PWM control of the switching element 180 based on the detection data ADQ. Specifically, the storage circuit 170 stores the current setting value of the current flowing through the inductor 11. The storage circuit 170 is, for example, a volatile memory such as SRAM, a register, or a non-volatile memory such as EEPROM. The control circuit 150 smooths the detection data ADQ to obtain a time average, and controls the duty cycle of the switching element 180 in a manner that makes the average value consistent with the current setting value.

[0049] The drive circuit 160 buffers the PWM signal SPWM, thereby outputting the PWM drive signal DPWM. The PWM drive signal DPWM is input to the gate of the P-type transistor, which serves as a switching element 180. The current flowing through the inductor 11 is controlled according to the duty cycle of the switching element 180.

[0050] In the circuit device 100 of this embodiment, the current detection circuit 110 or the processing circuit 115 corrects the detection error of the current value detected by the current sensing amplification circuit 120. Details of this correction are provided below. Figure 4 The explanation will follow later. Below, we will first describe the level shifting method in the current detection circuit 110. Furthermore, the current detection error is not considered in the description of the level shifting method.

[0051] 2. Level shifting method

[0052] Figure 2 This is a basic structural example of a current detection circuit that performs level shifting. The current detection circuit 110 includes a current sensing amplifier circuit 120, a current source 131, and variable current sinks 132a and 132b. The current source 131 and the variable current sinks 132a and 132b are corresponding to... Figure 1 The level shifting circuit 130. Figure 2 An example is shown of inputting a reference voltage VREFM to the terminal TVREFM from outside the circuit device 100, but it is not limited thereto. A voltage generation circuit provided in the circuit device 100 may also generate a reference voltage VREFM.

[0053] The current sensing amplifier circuit 120 includes a first resistor RIP, a second resistor RIN, a resistor RFP, a feedback resistor RFN, and an operational amplifier OPA.

[0054] The first resistor RIP is positioned between terminal TMONP and the first input node NIP. One end of resistor RFP is connected to the first input node NIP, and the other end receives the analog ground voltage VRA. The analog ground voltage VRA is input to the other end of resistor RFP via a voltage generation circuit not shown in the diagram. The second resistor RIN is positioned between terminal TMONN and the second input node NIN. One end of feedback resistor RFN is connected to the second input node NIN, and the other end is connected to the output node NQ of operational amplifier OPA. The first input node NIP is the non-inverting input node of operational amplifier OPA, and the second input node NIN is the inverting input node of operational amplifier OPA. The first resistor RIP and the second resistor RIN have the same resistance value, and the resistor RFP and the feedback resistor RFN have the same resistance value. However, as described later, the resistance values ​​of the first resistor RIP and the second resistor RIN may also have a mismatch due to manufacturing deviations, etc. The gain of the current sensing amplifier circuit 120 is, for example, several to tens of times, but is not limited to this.

[0055] Let the current flowing through the shunt resistor 12 be ILS, and the resistance of the shunt resistor 12 be Rsh. At this time, the potential difference Vsh across the shunt resistor 12 becomes Equation (1), and the detection voltage VQ of the current sensing amplifier circuit 120 becomes Equation (2).

[0056] Vsh=MONP-MONN=Rsh×ILS···(1)

[0057] VQ=(RFN / RIN)×Vsh+VRA···(2)

[0058] The current source 131 and the variable current sink 132a and 132b of the level shifting circuit 130 cause the first current IP to flow through the first resistor RIP and the second current IN to flow through the second resistor. Figure 2 When the arrows for IP and IN are set to the positive direction of the current, the level shift ΔVIP of the voltage VIP at the first input node NIP and the level shift ΔVIN of the voltage VIN at the second input node NIN are given by the following equation (3). VIP′ and VIN′ are the voltages of the input nodes of the operational amplifier OPA assuming no current flows through IP and IN.

[0059] ΔVIP = VIP - VIP' = RIP × IP

[0060] ΔVIN=VIN-VIN'=RIN×IN···(3)

[0061] With a virtual short circuit, VIP′=VIN′ and VIP=VIN, therefore, ΔVIP=ΔVIN. Since RIP=RIN, the output current IP=IN of the level shifter circuit 130.

[0062] The level shifting circuit 130 is shown in equation (4) below, and the output is a variable current IP and IN based on the voltage VLS = MONP.

[0063] IP=IN=(VREFM-VLS) / RIP···(4)

[0064] Based on equations (3) and (4) above, the level shifts ΔVIP and ΔVIN become equation (5), and the voltages VIP and VIN at the input nodes of the operational amplifier OPA become equation (6).

[0065] ΔVIP=ΔVIN=VREFM-VLS···(5)

[0066] VIP=VIN=VIP'+ΔVIP=VIP'-VLS+VREFM···(6)

[0067] When the gain of the current sensing amplifier circuit 120 is high enough, the voltage VIP′ is approximately the same as the voltage VLS. Therefore, the voltages VIP and VIN at the input node of the operational amplifier OPA are approximately the same as the reference voltage VREFM.

[0068] More specifically, the current source 131 includes PNP bipolar transistors BPA1 to BPA4 and current source IBA.

[0069] The emitters of bipolar transistors BPA1 to BPA4 are connected to the node of the power supply voltage VDA. For example, the power supply voltage VDA is supplied from a power supply circuit located within the circuit device 100. The collector of bipolar transistor BPA1 is connected to the first input node NIP of operational amplifier OPA, the collector of bipolar transistor BPA2 is connected to the second input node NIN of amplifier OPA, and the collector of bipolar transistor BPA3 is connected to node NLSM. The bases of bipolar transistors BPA1 to BPA3 are connected to the base and collector of bipolar transistor BPA4. The current flowing through the current source IBA is the collector current of bipolar transistor BPA4. Bipolar transistors BPA1 to BPA3 mirror this collector current, outputting constant currents IC1a to IC3a from this collector. These constant currents IC1a to IC3a are source currents, where IC1a = IC2a ​​= IC3a.

[0070] The variable current sink 132 includes a resistor RLSM, an error amplifier circuit ERAM, NPN bipolar transistors BPB1 to BPB3, and a capacitor CB.

[0071] The resistor RLSM is positioned between node NVLS and node NLSM.

[0072] Capacitor CB is positioned between the output node of the error amplifier circuit ERAM and node NLSM. Specifically, one end of capacitor CB is connected to the output node of the error amplifier circuit ERAM, and the other end is connected to node NLSM.

[0073] The emitters of bipolar transistors BPB1 to BPB3 are connected to the ground node. The collector of bipolar transistor BPB1 is connected to the first input node NIP of operational amplifier OPA, the collector of bipolar transistor BPB2 is connected to the second input node NIN of operational amplifier OPA, and the collector of bipolar transistor BPB3 is connected to node NLSM.

[0074] The reference voltage VREFM is input from the terminal TVREFM to the inverting input node of the error amplifier circuit ERAM, and the voltage VLSM of node NVLS is input to the non-inverting input node. The error amplifier circuit ERAM outputs a current control signal ERQ to the base of the bipolar transistor BPB3. When the collector of the bipolar transistor BPB3 is a variable current IV3a, the error amplifier circuit ERAM performs feedback control on the variable current IV3a so that VLSM = VREFM. At this time, the current ILSM flowing from the level shift circuit 130 to the resistor RLSM is given by the following equation (7).

[0075] ILSM=IC3a-IV3a=(VREFM-VLS) / RLSM···(7)

[0076] The current ILSM becomes the current corresponding to the voltage VLS at one end of the shunt resistor 12. IC3a is a constant current, therefore, the variable current IV3a is variably controlled according to the voltage VLS.

[0077] The collector currents of bipolar transistors BPB1 and BPB2 are set as variable currents IV1a and IV2a, respectively. A current control signal ERQ is input to the base of bipolar transistors BPB1 and BPB2 from the error amplifier circuit ERAM. Therefore, IV1a = IV2a = IV3a. That is, the variable currents IV1a, IV2a, and IV3a are the same, becoming currents that are variably controlled according to the voltage VLS. The variable currents IV1a to IV3a are the sink currents.

[0078] The current IP flowing from the level shift circuit 130 to the first resistor RIP and the current IN flowing from the level shift circuit 130 to the second resistor RIN are given by the following formula (8).

[0079] IP = IC1a-IV1a,

[0080] IN=IC2a-IV2a···(8)

[0081] According to IC1a=IC2a=IC3a, IV1a=IV2a=IV3a and the above equation (8), the currents IP and IN satisfy the following equation (9).

[0082] IP = IN = ILSM···(9)

[0083] According to RIP = RIN = RLSM and the above equation (9), the level shifts ΔVIP and ΔVIN become the following equation (10).

[0084] ΔVIP=ΔVIN=RIP×IP=RLSM×ILSM···(10)

[0085] Figure 3 This is a signal waveform diagram illustrating the operation of the current detection circuit 110. First, the basic switching action is explained.

[0086] When the PWM signal SPWM is high and the switching element 180 is turned on, a current ILS flows from the power node NVDD through the switching element 180, the shunt resistor 12, and the inductor 11 to the ground node. Therefore, the current ILS flowing through the inductor 11 gradually increases. At this time, the voltage at one end of the shunt resistor 12 is VLS = VDD, and the current detection at this time is called high-side detection.

[0087] When the PWM signal SPWM is low and the switching element 180 is open, a current ILS flows from the ground node through diode DA, shunt resistor 12, and inductor 11 to the ground node. Therefore, the current ILS flowing through inductor 11 gradually decreases. At this time, the voltage across one end of shunt resistor 12 is VLS = -Vf; this current detection is called low-side detection. Furthermore, Vf is the forward voltage of diode DA.

[0088] Next, the level shifting operation will be explained. When the level shifting circuit 130 outputs current to the first resistor RIP and the second resistor RIN, this current is called the pull-in current. When the level shifting circuit 130 draws current from the first resistor RIP and the second resistor RIN, this current is called the sink current.

[0089] In high-side detection, VLS = VDD > VREFM, so the level shifter circuit 130 flows through IP = IN = -IK as the sink current. According to the above equation (4), the sink current becomes the following equation (11).

[0090] IK=VDD-VREFM) / RIP···(11)

[0091] Furthermore, according to equation (5) above, the level shift becomes equation (12) below. Since ΔVIP < 0, the voltage levels of the input nodes VIP and VIN of the operational amplifier OPA decrease during high-side detection.

[0092] ΔVIP=ΔVIN=VREFM-VDD···(12)

[0093] In low-side detection, VLS = -Vf < VREFM, so the level shifter circuit 130 flows through IP = IN = IS as the pull-in current. According to the above equation (4), the sink current and pull-in current become the following equation (13).

[0094] IS=(VREFM+Vf) / RIP···(13)

[0095] Furthermore, according to equation (5) above, the level shift becomes equation (14) below. Since ΔVIP > 0, the voltage levels of the input nodes of the operational amplifier OPA, VIP and VIN, rise during low-side detection.

[0096] ΔVIP=ΔVIN=VREFM+Vf···(14)

[0097] Based on the sink current in equation (11) and the source current in equation (13), the voltages VIP and VIN at the input nodes of the operational amplifier OPA are approximately the same as the reference voltage VREFM during both high-side and low-side detection. That is, during high-side detection, the voltages VIP and VIN at the input nodes decrease from the power supply voltage VDD to approximately the reference voltage VREFM, and during low-side detection, the voltages VIP and VIN at the input nodes decrease from a negative voltage -Vf to approximately the reference voltage VREFM. Thus, high-side and low-side detection can be performed using a single current-sensing amplifier circuit, and the input voltage range of the amplifier in this current-sensing amplifier circuit can be a relatively narrow range near the reference voltage VREFM. Furthermore, by setting the reference voltage VREFM to a voltage lower than the withstand voltage of a low-voltage process, the operational amplifier can be constructed using circuit elements from a low-voltage process.

[0098] Furthermore, since the sink current IK in equation (11) is variably controlled according to the power supply voltage VDD, even when the power supply voltage VDD changes, the voltages VIP and VIN at the input node of the operational amplifier OPA are controlled to be approximately the same as the reference voltage VREFM. Thus, various power supplies with different power supply voltages can be used, and for each power supply voltage, the voltages VIP and VIN at the input node of the amplifier OPA remain constant. Additionally, when a battery is used as the power source, the power supply voltage decreases as the battery capacity decreases, but even when the power supply voltage decreases, the voltages VIP and VIN at the input node of the operational amplifier OPA remain constant.

[0099] 3. First Implementation Method

[0100] The first embodiment of a method for correcting the detection error of the current value will be described below. Additionally, for components that are identical to those already described, illustrations and descriptions are omitted as appropriate.

[0101] Figure 4 This is a detailed structural example of the current detection circuit 110 in the first embodiment. In this structural example, the current sensing amplifier circuit 120 includes a first switch SPC, a second switch SNC, a third resistor RPT, a fourth resistor RNT, a third switch SPT, and a fourth switch SNT. The resistor RLSM of the variable sink current source 132a is referred to as the fifth resistor. The variable capacitor current source 132a includes a fifth switch SMC, a sixth resistor RMT, and a sixth switch SMT.

[0102] The first switch, SPC, is connected in series with the first resistor, RIP, between terminal TMONP and the first input node NIP. Specifically, one end of the first resistor, RIP, is connected to terminal TMONP, and the other end is connected to the first node, NPC. One end of the first switch, SPC, is connected to the first node, NPC, and the other end is connected to the first input node, NIP. The second switch, SNC, is connected in series with the second resistor, RIN, between terminal TMONN and the second input node, NIN. Specifically, one end of the second resistor, RIN, is connected to terminal TMONN, and the other end is connected to the second node, NNC. One end of the second switch, SNC, is connected to the second node, NNC, and the other end is connected to the second input node, NIN.

[0103] The third switch SPT is connected in series with the third resistor RPT between the ground node and the first input node NIP.

[0104] Specifically, one end of the third resistor RPT is connected to the ground node, and the other end is connected to the third node NPT. One end of the third switch SPT is connected to the third node NPT, and the other end is connected to the first input node NIP. The fourth switch SNT is connected in series with the fourth resistor RNT between the ground node and the second input node NIN. Specifically, one end of the fourth resistor RNT is connected to the ground node, and the other end is connected to the fourth node NNT. One end of the fourth switch SNT is connected to the fourth node NNT, and the other end is connected to the second input node NIN.

[0105] The fifth switch, SMC, is connected in series with the fifth resistor, RLSM, between terminal TVLS and node NLSM. Specifically, one end of the fifth resistor RLSM is connected to terminal TVLS, and the other end is connected to node NMC. One end of the fifth switch, SMC, is connected to node NMC, and the other end is connected to node NLSM. The sixth switch, SMT, is connected in series with the sixth resistor, RMT, between the ground node and node NLSM. Specifically, one end of the sixth resistor RMT is connected to the ground node, and the other end is connected to node NMT. ​​One end of the sixth switch, SMT, is connected to node NMT, and the other end is connected to node NLSM.

[0106] The resistance values ​​of the first resistor RIP, the second resistor RIN, the third resistor RPT, the fourth resistor RNT, the fifth resistor RLSM, and the sixth resistor RMT are the same. Figure 4 The example shown is where one end of resistor RPT (3rd), resistor RNT (4th), and resistor RMT (6th) is connected to a ground node, but one end of them can be connected to a constant voltage node with a constant potential.

[0107] The aforementioned first switch SPC, second switch SNC, third switch SPT, fourth switch SNT, fifth switch SMC, and sixth switch SMT are each, for example, transmission gates formed by N-type transistors, P-type transistors, or N-type transistors and P-type transistors connected in parallel.

[0108] Figure 4 The states of the switches during current detection are shown. During current detection, control circuit 150 turns on switches SPC, SNC, and SMC, and turns off switches SPT, SNT, and SMT. Current sensing amplifier circuit 120, as described in equations (1) and (2) above, detects the current ILS flowing through shunt resistor 12 and outputs a detection voltage VQ as a result. The detection voltage VQ obtained during this current detection period is taken as VCS, and the current value VCS / Rsh detected by the detection voltage VCS is called the detection current value.

[0109] Equations (1) and (2) above show the ideal detection voltage VQ, but in reality, as shown in equation (15), the detection voltage VCS includes the bias voltage Δvof. That is, the detection current value ICS includes the detection error corresponding to the bias voltage Δvof. In the first embodiment, the bias voltage Δvof includes, for example, the bias of the operational amplifier OPA, the bias of the analog ground voltage VRA, or both. In addition, here, equations (15-2) and (15-3) hold.

[0110] VCS=(RFN / RIN)×Rsh×ILS+VRA+Δvof···(15)

[0111] RIP=RIN, RFP=RFN···(15-2)

[0112] IC1a=IC2a, IV1a=IV2a···(15-3)

[0113] Figure 5 The state of the switches during bias detection is shown. During bias detection, control circuit 150 disconnects switches SPC, SNC, and SMC, and turns on switches SPT, SNT, and SMT. The detection voltage VQ obtained during this bias detection is set as VOST. This detection voltage VOST corresponds to the bias value contained in the detection current value ICS, and this bias value is used as IOST.

[0114] Figure 5 The state is equivalent to the state in which the two ends of the shunt resistor 12 are short-circuited to MONP = MONN = 0V during voltage detection. That is, according to the above equations (1) and (15), the detection voltage VOST becomes the following equation (16).

[0115] VOST=VRA+Δvof···(16)

[0116] As shown in equation (17), the control circuit 150 subtracts the A / D conversion data of the detection voltage VOST from the A / D conversion data of the detection voltage VCS, thereby obtaining the data of the detection voltage VQcul after bias elimination. If the current value detected based on this voltage VQcul is set as the corrected current value ILScul, the relationship between VQcul and ILScul is shown in equation (18). According to equations (17) and (18), the voltage VQcul obtained by equation (17) corresponds to the corrected current value ILScul obtained by equation (19). The control circuit 150 performs PWM control on the switching element 180 based on the data of the detection voltage VQcul, thereby enabling PWM control based on the accurate corrected current value ILScul after bias elimination.

[0117] VQcul=VCS-VOST···(17)

[0118] VQcul=((RFN / RIN))×Rsh×ILScul···(18)

[0119] ILScul=ICS-IOST···(19)

[0120] Figure 6This is a timing diagram of the current detection operation in the first embodiment. Here, the current detection operation is shown in one cycle of the PWM signal SPWM, but the same current detection operation is performed in each cycle. When the PWM signal SPWM is high, the switching element 180 is turned on, and when the PWM signal SPWM is low, the switching element 180 is turned off.

[0121] The control circuit 150 sets the PWM signal SPWM from low to high. After a waiting period, it performs the actions of detection periods DT1 to DTm (from the 1st to the mth period). After another waiting period, it sets the PWM signal SPWM from high to low. After the waiting period, the control circuit 150 performs the actions of detection periods DTm+1 to DTn (from the (m+1)th to the nth period). After another waiting period, it sets the PWM signal SPWM from low to high. n is an integer greater than or equal to 2, and m is an integer greater than or equal to 1 and less than n. The high-level period of the PWM signal SPWM is determined based on the current detection results in the previous period. The control circuit 150 determines the value of m based on this high-level period.

[0122] The first detection period DT1 includes the bias detection period indicated by “OST” and the current detection period indicated by “CS”. Figure 6 An example is shown where the bias detection period precedes the current detection period; the order can also be reversed. The current sensing amplifier circuit 120 detects a detection voltage VOST1 representing the bias value during the bias detection period and a detection voltage VCS1 representing the detected current value during the current detection period. Similarly, the current sensing amplifier circuit detects detection voltages VOST2 to VOSTn during the bias detection period (DT2 to DTn) from the 2nd to the nth detection period and detection voltages VCS2 to VCSn during the current detection period. The control circuit 150 calculates the voltage VQcul representing the corrected current value ILScul according to the following equation (20).

[0123]

[0124] In this embodiment described above, the circuit device 100 includes a current sensing amplifier circuit 120 and a processing circuit 115. A switching element 180, a shunt resistor 12, and an inductor 11 are connected in series between the first power node and the second power node. The current sensing amplifier circuit 120 detects the current flowing through the shunt resistor 12. The processing circuit 115 calculates the corrected current value ILScul of the current ILS flowing through the shunt resistor 12 based on the output of the current sensing amplifier circuit 120. The current sensing amplifier circuit 120 includes an operational amplifier OPA, a first resistor RIP, a first switch SPC, a second resistor RIN, a second switch SNC, a third resistor RPT, a third switch SPT, a fourth resistor RNT, and a fourth switch SNT. The first resistor RIP is disposed between the first resistor node NMONP and the first node NPC at one end of the shunt resistor 12. The first switch SPC is disposed between the first node NPC and the first input node NIP of the operational amplifier OPA. The second resistor RIN is positioned between the second resistor node NMONN and the second node NNC at the other end of the shunt resistor 12. The second switch SNC is positioned between the second node NNC and the second input node NIN of the operational amplifier OPA. The third resistor RPT is positioned between the constant voltage node and the third node NPT. The third switch SPT is positioned between the third node NPT and the first input node NIP. The fourth resistor RNT is positioned between the constant voltage node and the fourth node NNT. The fourth switch SNT is positioned between the fourth node NNT and the second input node NIN. During current detection, the first switch SPC and the second switch SNC are turned on, and the third switch SPT and the fourth switch SNT are turned off. The processing circuit 115 obtains the detected current value ICS based on the output of the current sensing amplifier circuit 120. During bias detection, the first switch SPC and the second switch SNC are turned off, and the third switch SPT and the fourth switch SNT are turned on. The processing circuit 115 obtains the bias value IOST based on the output of the current sensing amplifier circuit 120. The processing circuit 115 calculates the corrected current value ILScul based on the detected current value ICS and the bias value IOST.

[0125] According to this embodiment, one end of the third resistor RPT and one end of the fourth resistor RNT are connected to the constant voltage node. During bias detection, the first switch SPC and the second switch SNC are open, while the third switch SPT and the fourth switch SNT are closed. Therefore, the differential input of the current sensing amplifier circuit 120 becomes the same as in the short-circuit state, enabling the measurement of the bias of the detection voltage VQ.

[0126] Furthermore, unlike resistors RIP and RIN, the four switches mentioned above are connected to the input node side of the operational amplifier (OPA). Therefore, applying the voltage to the input node of the OPA to the four switches does not directly apply the voltage to one or the other end of shunt resistor 12. The voltage at one or the other end of the shunt resistor may sometimes be near or negative than the power supply voltage VDD, but these voltages are not applied to the switches. Therefore, the switches do not need to be manufactured or constructed to withstand high or negative voltages.

[0127] In addition, Figure 1 In the example, the first power node is one of the power node NVDD and the ground node, and the second power node is the other of the power node NVDD and the ground node. Figure 4 and Figure 5 In the example, the constant voltage node is the ground node. In equation (17) above, the voltage VQcul corresponding to the corrected current value ILScul is calculated, as explained in equations (18) and (19) above. This is equivalent to calculating the corrected current value ILScul.

[0128] In addition, in this embodiment, the circuit device 100 includes a level shifting circuit 130. The level shifter circuit 130 supplies a first current IP to the first input node NIP and supplies a second current IN to the second input node NIN, thereby level shifting the voltages of the first input node NIP and the second input node NIN.

[0129] like Figure 3 As explained, the voltage VLS, equivalent to the common-mode voltage, fluctuates significantly due to PWM driving. Without the level shifting circuit 130, if the common-mode voltage fluctuates, the input voltages VIP and VIN of the operational amplifier OPA also fluctuate. According to this embodiment, the level shifting circuit 130 shifts the voltages of the first input node NIP and the second input node NIN, thereby reducing the fluctuations in the input voltages VIP and VIN of the operational amplifier OPA.

[0130] In addition, in this embodiment, the level shifting circuit 130 variably controls the first current IP and the second current IN according to the voltage VLS of the first resistor node NMONP, thereby level shifting the voltages of the first input node NIP and the second input node NIN according to the level shift amount that varies with the voltage VLS of the first resistor node NMONP.

[0131] According to this embodiment, the input voltages VIP and VIN of the operational amplifier OPA are level-shifted according to the level shift amount based on the voltage VLS change of the first resistor node NMONP, and the level shift amount is also applied to the input voltages VIP and VIN of the operational amplifier OPA according to the level shift amount corresponding to the common-mode voltage. Therefore, the input voltages VIP and VIN of the operational amplifier OPA are controlled according to the common-mode voltage, thus reducing their variation.

[0132] Furthermore, in this embodiment, the level shift is the difference between the reference voltage VREFM and the voltage VLS of the first resistor node NMONP.

[0133] According to this embodiment, the input voltages VIP and VIN of the operational amplifier OPA can be shifted to approximately the reference voltage VREFM. Therefore, even with common-mode voltage variations, the input voltages VIP and VIN of the operational amplifier OPA can be maintained approximately at the reference voltage VREFM. Since the voltages applied to the first to fourth switches are approximately the reference voltage VREFM, the first to fourth switches can be manufactured or constructed using a process or structure capable of withstanding approximately the reference voltage VREFM.

[0134] Furthermore, in this embodiment, the circuit device 100 includes a drive circuit 160, which drives the switching element 180 using a PWM signal SPWM based on the corrected current value ILScul. The processing circuit 115 acquires the detected current value ICS during the current detection period and the bias value IOST during the bias detection period during each of the first to nth detection periods DT1 to DTn in one cycle of the PWM signal SPWM.

[0135] like Figure 3 As explained, the current ILS flowing through the shunt resistor 12 varies via PWM drive. According to this embodiment, multiple current detections are performed within one cycle of the PWM signal SPWM, thereby enabling the calculation of the average current value.

[0136] In addition, in this embodiment, the processing circuit 115 calculates the average value of the difference between the detection current value ICS and the bias value IOST obtained in each detection period during the first to nth detection periods DT1 to DTn as the corrected current value ILScul in one cycle.

[0137] According to this embodiment, the current value after bias elimination in each detection period is obtained by measuring the difference between the detected current value ICS and the bias value IOST, and the corrected current value ILScul in one cycle is obtained based on the average value of the current value.

[0138] In addition, in the above equation (20), the voltage VQcul corresponding to the corrected current value ILScul is obtained, which is equivalent to obtaining the corrected current value ILScul.

[0139] Furthermore, in this embodiment, the first to nth detection periods DT1 to DTn include the first to mth detection periods DT1 to DTm during the first voltage level period of the PWM signal SPWM and the (m+1)th to nth detection periods DTm+1 to DTn during the second voltage level period of the PWM signal SPWM. The processing circuit 115 calculates the average of the difference between the detected current value ICS and the bias value IOST obtained in each of the first to mth detection periods DT1 to DTm as the corrected current value during the first voltage level period. The processing circuit 115 also calculates the average of the difference between the detected current value ICS and the bias value IOST obtained in each of the (m+1)th to nth detection periods DTm+1 to DTn as the corrected current value during the second voltage level period. The processing circuit 115 calculates the corrected current value ILScul based on the corrected current value during the first voltage level and the corrected current value during the second voltage level.

[0140] like Figure 3 As explained, the current ILS flowing through the shunt resistor 12 rises during the on-time of the switching element 180 and falls during the off-time. According to this embodiment, the switching element 180 sets a detection period in both the on-time and off-time, so the corrected current value ILScul in one cycle can be accurately determined.

[0141] In addition, Figure 6 In the example, the first voltage level period is the high level period of the PWM signal or the on period of the switching element 180, and the second voltage level period is the low level period of the PWM signal or the off period of the switching element 180. In the above equation (20), the first sum on the right corresponds to the average value of DT1 to DTm during the first to m detection periods, and the second sum on the right corresponds to the average value of DTm+1 to DTn during the (m+1)th to nth detection periods.

[0142] In this embodiment, the switching element 180 is connected between the first power supply node and the first resistor node NMONP. The diode DA is connected between the first resistor node NMONP and the second power supply node, which serves as a ground node. The inductor 11 is connected between the second resistor node NMONN and the ground node. The current sensing amplifier circuit 120 detects the current value ICS by detecting the voltage difference between the first resistor node NMONP and the second resistor node NMONN.

[0143] During the on period of the switching element 180, the common-mode voltage is near the power supply voltage of the first power supply node, and during the off period of the switching element 180, the common-mode voltage is a negative voltage. The negative voltage is the voltage after dropping the forward voltage of the diode DA from the ground voltage. According to the present embodiment, as described above, these voltages are not directly applied to the first to fourth switches.

[0144] 4. Second Embodiment

[0145] A second embodiment of a method for detecting an error in the correction current value will be described. In addition, for structural elements that are the same as those already described, illustration and description are appropriately omitted.

[0146] In the second embodiment, the bias of the operational amplifier OPA and the like is eliminated in the same manner as in the first embodiment, and the current detection error caused by the mismatch of resistors or currents can be eliminated. First, use Figures 7-10 to illustrate the current detection error caused by the mismatch of resistors or currents.

[0147] Figure 7 Shown in Figure 4 the first error component depending on the common-mode voltage during the current detection of Figure 7 Shown is the first error component of the detection voltage VQ when both ends of the shunt resistor 12 are short-circuited and the voltage MONP at one end is changed. Here, it is assumed that IP = IN.

[0148] The first error component is caused by the mismatch between the resistance value of the first resistor RIP and the resistance value of the second resistor RIN. In the case of no mismatch where RIP = RIN, the detection voltage VQ becomes the analog ground voltage VRA which is the expected value. As shown by LA1, when RIP < RIN, the detection voltage VQ has a positive linear characteristic with respect to the voltage MONP. As shown by LA2, when RIP > RIN, the detection voltage VQ has a negative linear characteristic with respect to the voltage MONP.

[0149] Since VIP = VIN = VREFM, when MONP = VREFM, IP = IN = 0. Therefore, RIP×IP = RIN×IN = 0, and the influence of resistor mismatch does not occur, so VQ = VRA. When MONP ≠ VREFM, IP = IN ≠ 0, so RIP×IP ≠ RIN×IN. This is equivalent to the case where a potential difference is generated across the shunt resistor 12, so an error occurs with respect to VQ = VRA which is the expected value. Since the first current IP and the second current IN depend on the voltage MONP, the first error component of the detection voltage VQ depends on the voltage MONP.

[0150] Figure 8 Shown in Figure 4A second error component that depends on the common-mode voltage during current detection. Figure 8 Shows the second error component of the detection voltage VQ when both ends of the shunt resistor 12 are short-circuited and the voltage MONP at one end is changed. Here, RIP = RIN, IC1a = IC2a.

[0151] The second error component is caused by the mismatch between the current values of the variable current IV1a and the variable current IV2a. In the case of no mismatch where IV1a = IV2a, the detection voltage VQ becomes the analog ground voltage VRA as the expected value. As shown in LG1, when IV1a < IV2a, the detection voltage VQ has a positive linear characteristic with respect to the voltage MONP. As shown in LG2, when IV1a > IV2a, the detection voltage VQ has a negative linear characteristic with respect to the voltage MONP.

[0152] When IV1a ≠ IV2a, IP ≠ IN, so RIP × IP ≠ RIN × IN. Therefore, an error occurs with respect to VQ = VRA as the expected value. Since the variable current IV1a and the variable current IV2a depend on the voltage MONP, the second error component of the detection voltage VQ depends on the voltage MONP. Even when MONP = VREFM, since IV1a ≠ IV2a, VQ ≠ VRA at MONP = VREFM.

[0153] Figure 9 Shows during Figure 4 A third error component that does not depend on the common-mode voltage during current detection. Figure 9 Shows the third error component of the detection voltage VQ when both ends of the shunt resistor 12 are short-circuited and the voltage MONP at one end is changed. Here, RIP = RIN, IV1a = IV2a.

[0154] The third error component is caused by the mismatch between the current values of the constant current IC1a and the constant current IC2a. In the case of no mismatch where IC1a = IC2a, the detection voltage VQ becomes the analog ground voltage VRA as the expected value. As shown in LB1, when IC1a > IC2a, the detection voltage VQ is a constant value that does not depend on the voltage MONP, and VQ > VRA. As shown in LB2, when IC1a < IC2a, the detection voltage VQ is a constant value that does not depend on the voltage MONP, and VQ < VRA.

[0155] When IC1a ≠ IC2a, IP ≠ IN, so RIP × IP ≠ RIN × IN. Therefore, an error occurs with respect to VQ = VRA as the expected value. Since the constant current IC1a and the constant current IC2a do not depend on the voltage MONP, the third error component of the detection voltage VQ does not depend on the voltage MONP.

[0156] During current detection, the current detection error caused by the mismatch of resistors or currents is the error after summing the first to third error components described above.

[0157] Figure 10 Show Figure 5 The error components during the bias detection shown. One end of the third resistor RPT and one end of the fourth resistor RNT are connected to the ground node, so the detection error when the output common-mode voltage is 0V.

[0158] This error component is caused by at least one of the mismatch between the resistance value of the third resistor RPT and the resistance value of the fourth resistor RNT, the mismatch between the current value of the variable current IV1a and the current value of the variable current IV2a, or the mismatch between the current value of the constant current IC1a and the current value of the constant current IC2a. In the absence of mismatch, the detection voltage VQ is the analog ground voltage VRA as the expected value. As shown in LC1 or LC2, in the presence of mismatch, an error occurs with respect to VQ = VRA as the expected value. Whether VQ > VRA or VQ < VRA is determined by the sum of the errors based on each mismatch.

[0159] Figure 11 This is a detailed structural example of the circuit device 100 in the second embodiment. In this structural example, the current sensing amplifier circuit 120 includes a correction circuit 121.

[0160] The correction circuit 121 corrects at least one of the mismatch between the resistance values of the first resistor RIP and the second resistor RIN, or the mismatch between the first current IP and the second current IN. The storage circuit 170 stores correction information for correcting at least one of the above mismatches. The control circuit 150 sets the correction circuit 121 according to the correction information stored in the storage circuit 170, and the correction circuit 121 becomes a state capable of correcting at least one of the above mismatches. This setting is performed, for example, during initialization when the power is turned on.

[0161] The correction information is obtained, for example, during inspection during manufacturing. The correction information is written into the storage circuit 170 from an external processing device or the like, for example, during initialization when the power is turned on. Alternatively, the storage circuit 170 is a non-volatile memory, and the correction information is stored in the non-volatile memory during manufacturing.

[0162] Figure 12 This is a first detailed structural example of the current detection circuit 110 in the second embodiment. In this structural example, the current sensing amplifier circuit 120 includes a first variable resistor RIPV, a second variable resistor RPTV, and a variable current circuit 135 as the correction circuit 121.

[0163] The first variable resistor RIPV is connected in series with the first resistor RIP between terminal TMONP and node NPC. Specifically, one end of the first variable resistor RIPV is connected to the other end of the first resistor RIP, and the other end of the first variable resistor RIPV is connected to node NPC. The first variable resistor RIPV may consist, for example, of multiple resistors and multiple switches that switch their connections.

[0164] The second variable resistor RPTV is connected in series with the third resistor RPT between the ground node and the third node NPT. Specifically, one end of the second variable resistor RPTV is connected to the other end of the third resistor RPT, and the other end of the second variable resistor RPTV is connected to the third node NPT. The second variable resistor RPTV may consist, for example, of multiple resistors and multiple switches that switch their connections.

[0165] The output node of the variable current circuit 135 is connected to the first input node NIP of the operational amplifier OPA. The variable current circuit 135 supplies a correction current IPC to the first input node NIP as a source or sink current. Figure 12 An example is shown where the correction current IPC is a source current. Additionally, the output node of the variable current circuit 135 may not be connected to the first input node NIP, but instead connected to the second input node NIN.

[0166] The calibration information includes the resistance setting value of the first variable resistor RIPV, the resistance setting value of the second variable resistor RPTV, and the current setting value of the calibration current IPC. Based on the calibration information, the control circuit 150 sets the resistance setting value of the first variable resistor RIPV, the resistance setting value of the second variable resistor RPTV, and the current setting value of the calibration current IPC.

[0167] Furthermore, the operation during current detection and bias detection, as well as the processing of calculating the corrected current value based on the detected current value and bias value, are the same as in the first embodiment.

[0168] Figure 13 This is a second detailed structural example of the current detection circuit 110 in the second embodiment. In this structural example, the current sensing amplifier circuit 120 includes a first variable resistor RIPV, a second variable resistor RPTV, a third variable resistor RINV, a fourth variable resistor RNTV, a variable current circuit 135, and a variable current circuit 136 as a correction circuit 121.

[0169] The second variable resistor RPTV is connected in series with the second resistor RIN between terminal TMONN and the second node NNC. The fourth variable resistor RNTV is connected in series with the fourth resistor RNT between the ground node and the fourth node NNT. The correction current IPC is used as the first correction current. The variable current circuit 136 supplies the second correction current INC to the second input node NIN as a source or sink current.

[0170] Figure 14 This is the first detailed structural example of the variable current circuit 135. The variable current circuit 135 includes P-type transistors TA1 and TA2 constituting a current mirror circuit and a variable current source IBVA. The current mirror circuit mirrors the output current of the variable current source IBVA, thereby outputting a correction current IPC as the sourcing current.

[0171] Figure 15 This is the second detailed structural example of the variable current circuit 135. The variable current circuit 135 includes N-type transistors TB1 and TB2 constituting a current mirror circuit and a variable current source IBVB. The current mirror circuit mirrors the output current of the variable current source IBVB, thereby outputting a correction current IPC as a sink current.

[0172] The control circuit 150 controls the current value of the correction current IPC by controlling the output current value of the variable current source IBVA or IBVB.

[0173] Variable current circuit 135 includes Figure 14 Structure and Figure 15 Both circuits selectively output either source or sink current. The above explanation uses variable current circuit 135 as an example, but the structure of variable current circuit 136 is the same as that of variable current circuit 135.

[0174] Figure 16 This diagram illustrates the steps involved in determining correction information. This step is performed, for example, during inspection during manufacturing. The following describes an example of how an inspection device performs these steps.

[0175] In step 1, the inspection device sets the switch state during current detection to short-circuit both ends of the shunt resistor 12 and sets MONP = VREFM. The inspection device monitors the detection data ADQ while changing the current setting value of the calibration current IPC, and determines the current setting value that satisfies VQ = VRA. When changing the calibration current IPC, the slope of the detection voltage VQ with respect to the voltage MONP does not change, but the intercept changes. Therefore, in step 1, the detection voltage VQ in MONP = VREFM is corrected to the expected value. Hereinafter, let the calibration current IPC be a pull current. As shown in LD1, when VQ > VRA in MONP = VREFM, the inspection device reduces the calibration current IPC, and thus, as shown in LE1, the detection voltage VQ decreases. As shown in LD2, when VQ < VRA in MONP = VREFM, the inspection device increases the calibration current IPC, and thus, as shown in LE2, the detection voltage VQ increases.

[0176] In step 2, the inspection device sets the switch state during current detection to short-circuit both ends of the shunt resistor 12 and sets MONP ≠ VREFM. The inspection device monitors the detection data ADQ while changing the resistance setting value of the first variable resistor RIPV, and determines the resistance setting value that satisfies VQ = VRA. When changing the resistance value of the first variable resistor RIPV, while maintaining VQ = VRA in MONP = VREFM, the slope of the detection voltage VQ with respect to the voltage MONP changes. Therefore, in step 2, the detection voltage VQ is corrected to the expected value regardless of the voltage MONP. As shown in LE1, when the detection voltage VQ has a positive slope, the inspection device can make the slope of the detection voltage VQ approach zero by increasing the resistance setting value of the first variable resistor RIPV, as shown in LF1. As shown in LE2, when the detection voltage VQ has a negative slope, the inspection device reduces the resistance setting value of the first variable resistor RIPV, and thus, as shown in LF2, can make the slope of the detection voltage VQ approach zero.

[0177] In addition, in step 2, the inspection device sets the switch state during bias detection, monitors the detection data ADQ while changing the resistance setting value of the second variable resistor RPTV, and determines the resistance setting value that satisfies VQ = VRA. Thereby, in the bias detection, the detection voltage VQ is corrected to the expected value. The detection voltage VOST representing the bias value may vary due to power supply voltage or temperature changes, etc. This variation amount is detected during the bias detection and eliminated by the above formula (17).

[0178] In this embodiment described above, the circuit device 100 includes a current sensing amplifier circuit 120, a level shifting circuit 130, and a storage circuit 170. A switching element 180, a shunt resistor 12, and an inductor 11 are connected in series between the first power node and the second power node. The current sensing amplifier circuit 120 detects the current flowing through the shunt resistor 12. The current sensing amplifier circuit 120 includes an operational amplifier OPA, a first resistor RIP, a second resistor RIN, and a correction circuit 121. The first resistor RIP is disposed between the first resistor node NMONP at one end of the shunt resistor 12 and the first input node NIP of the operational amplifier OPA. The second resistor RIN is disposed between the second resistor node NMONN at the other end of the shunt resistor 12 and the second input node NIN of the operational amplifier OPA. The level shifting circuit 130 supplies a first current IP to the first input node NIP and a second current IN to the second input node NIN, thereby level-shifting the voltages at the first input node NIP and the second input node NIN. The storage circuit 170 stores correction information for at least one mismatch, either a mismatch between the first resistor RIP and the second resistor RIN, or a mismatch between the first current IP and the second current IN. The correction circuit 121 corrects the at least one mismatch based on the correction information, thereby correcting the detection error of the current sensing amplifier circuit 120 caused by the at least one mismatch.

[0179] In the event of a mismatch between the first resistor RIP and the second resistor RIN, or a mismatch between the first current IP and the second current IN, a detection error occurs in the current sensing amplifier circuit 120 due to this mismatch. According to this embodiment, at least one mismatch is corrected based on correction information for correcting the mismatch between the first resistor RIP and the second resistor RIN, or the mismatch between the first current IP and the second current IN. This corrects the detection error of the current sensing amplifier circuit 120 caused by the at least one mismatch. Consequently, the current sensing amplifier circuit 120 accurately detects the current flowing through the shunt resistor 12.

[0180] In addition, such as Figure 7 and Figure 8 As explained, the detection error may depend on the common-mode voltage. Figure 16 As explained, according to this embodiment, it is possible to correct detection errors that depend on the common-mode voltage.

[0181] Additionally, the mismatch between resistor RIP and resistor RIN is due to their different resistance values. Furthermore, the mismatch between current IP and current IN is due to their different current values.

[0182] Furthermore, in this embodiment, the calibration circuit 121 includes a first variable resistor RIPV. The first variable resistor RIPV is connected in series with the first resistor RIP between the first resistor node NMONP and the first input node NIP. The storage circuit 170 stores the resistance setting value of the first variable resistor RIPV as calibration information.

[0183] like Figure 16 As described in step 2, by adjusting the resistance value of the first variable resistor RIPV, the slope of the detection voltage VQ caused by the at least one mismatch can be corrected. According to this embodiment, the resistance setting value of the first variable resistor RIPV for correcting the slope of the detection voltage VQ is stored in the storage circuit 170, and the resistance value of the first variable resistor RIPV is set according to this resistance setting value, thereby correcting the slope of the detection voltage VQ caused by the at least one mismatch.

[0184] Furthermore, in this embodiment, the first variable resistor RIPV is disposed between the first resistor RIP and the first input node NIP.

[0185] According to this embodiment, the first variable resistor RIPV is connected to the input node side of the operational amplifier OPA, compared to the first resistor RIP. Therefore, the voltage near or negative of the power supply voltage VDD at one or the other end of the shunt resistor 12 is not applied to the first variable resistor RIPV. Thus, it is not necessary to make the switches or the like included in the first variable resistor RIPV resistant to high or negative voltages using advanced technology or structures.

[0186] Furthermore, in this embodiment, the first input node NIP is the non-inverting input node of the operational amplifier OPA, and the second input node NIN is the inverting input node of the operational amplifier OPA. The current sensing amplifier circuit 120 includes a feedback resistor RFN disposed between the output node NQ and the inverting input node of the operational amplifier OPA.

[0187] According to this embodiment, the gain of the current sensing amplifier circuit 120 is the ratio of the resistance value of the second resistor RIN to the resistance value of the feedback resistor RFN. The first variable resistor RIPV is disposed on the side of the first resistor RIP, thereby reducing the detection error caused by at least one mismatch without changing the gain of the current sensing amplifier circuit 120.

[0188] Furthermore, in this embodiment, the correction circuit 121 includes a variable current circuit 135, which supplies a correction current IPC to either the first input node NIP or the second input node NIN. The storage circuit 170 stores the current setting value of the correction current IPC as correction information.

[0189] like Figure 16As described in step 1, the intercept of the detection voltage VQ caused by at least one mismatch is corrected by adjusting the current value of the correction current IPC. According to this embodiment, the current setting value of the correction current IPC for correcting the intercept of the detection voltage VQ is stored in the storage circuit 170, and the current value of the correction current IPC is set according to this current setting value, thereby correcting the intercept of the detection voltage VQ caused by at least one mismatch.

[0190] In this embodiment, the first resistor RIP and the first variable resistor RIPV are disposed between the first resistor node NMONP and the first node NPC. The second resistor RIN is disposed between the second resistor node NMONN and the second node NNC. The current sensing amplifier circuit 120 includes an operational amplifier OPA, a first switch SPC, a second switch SNC, a third resistor RPT, a third switch SPT, a fourth resistor RNT, and a fourth switch SNT. The first switch SPC is disposed between the first node NPC and the first input node NIP of the operational amplifier OPA. The second switch SNC is disposed between the second node NNC and the second input node NIN of the operational amplifier OPA. The third resistor RPT is disposed between the constant voltage node and the third node NPT. The third switch SPT is disposed between the third node NPT and the first input node NIP. The fourth resistor RNT is disposed between the constant voltage node and the fourth node NNT. The fourth switch SNT is disposed between the fourth node NNT and the second input node NIN.

[0191] According to this embodiment, when the first switch SPC and the second switch SNC are turned on, the current flowing through the shunt resistor 12 can be detected. The current detection error is corrected by correcting at least one mismatch, either the mismatch between the first resistor RIP and the second resistor RIN, or the mismatch between the first current IP and the second current IN.

[0192] Furthermore, in this embodiment, the calibration circuit 121 includes a second variable resistor RPTV, which is connected in series with the third resistor RPT between the constant voltage node and the third node NPT. The storage circuit 170 stores the resistance setting value of the second variable resistor RPTV as calibration information.

[0193] According to this embodiment, when the third switch SPT and the fourth switch SNT are turned on, the bias of the current sensing amplifier circuit 120 can be detected. Figure 16 As explained in step 2, by adjusting the resistance value of the second variable resistor RPTV, the error of the detection voltage VQ in the bias detection can be corrected.

[0194] Furthermore, in this embodiment, the level shifting circuit 130 includes a first constant current source, a second constant current source, a first variable current source, a second variable current source, and a current control circuit. The first constant current source supplies a first constant current IC1a as a pull-in current to the first input node NIP. The second constant current source supplies a second constant current IC2a ​​as a sink current to the second input node NIN. The first variable current source supplies a first variable current IV1a as a sink current to the first input node NIP. The second variable current source supplies a second variable current IV2a as a sink current to the second input node NIN. The current control circuit variably controls the first variable current IV1a and the second variable current IV2a according to the voltage VLS of the first resistor node NMONP.

[0195] like Figure 8 As explained, a current sensing error dependent on the common-mode voltage arises due to the mismatch between the first variable current IV1a and the second variable current IV2a. Additionally, as... Figure 9 As explained, a current sensing error independent of the common-mode voltage arises due to the mismatch between the first constant current IC1a and the second constant current IC2a. Figure 16 As explained, according to this embodiment, the correction circuit 121 is able to correct current detection errors caused by these mismatches.

[0196] In addition, Figure 2 In this circuit, bipolar transistor BPA1 corresponds to the first constant current source, and bipolar transistor BPA2 corresponds to the second constant current source. Bipolar transistor star-connected BPB1 corresponds to the first variable current source, and bipolar transistor BPB2 corresponds to the second variable current source. The error amplifier circuit ERAM, the fifth resistor RLSM, and bipolar transistors BPA3 and BPB3 correspond to the current control circuit.

[0197] 5. Third Implementation Method

[0198] Figure 17 This is a detailed structural example of the current detection circuit 110 in the third embodiment. In this structural example, the current sensing amplifier circuit 120 includes a monitoring circuit 190. The structure and operation of the current sensing amplifier circuit 120, the current source 131, and the variable current sinks 132a and 132b are the same as in the first embodiment.

[0199] The monitoring circuit 190 switches the input voltage ADIN of the A / D conversion circuit 140. That is, during current detection and bias detection, the monitoring circuit 190 selects the detection voltage VQ as the input voltage ADIN, and during monitoring, it selects the monitoring voltage VM based on voltage MONP as the input voltage ADIN.

[0200] Figure 18This is a detailed structural example of the monitoring circuit 190. The monitoring circuit 190 includes resistors RC1 and RC2, an N-type transistor TC, and switches SWC1 and SWC2.

[0201] During current detection and bias detection, control circuit 150 turns on switch SWC1 and turns off switch SWC2. Thus, the detected voltage VQ is output as the input voltage ADIN. During monitoring, control circuit 150 turns on the N-type transistor TC and switch SWC2, and turns off switch SWC1. Thus, voltage MONP is divided by resistors RC1 and RC2 into a monitoring voltage VM, which is output as the input voltage ADIN. Resistors RC1 and RC2 divide voltage MONP, thereby making the monitoring voltage VM below the withstand voltage of the circuit elements constituting switches SWC1 and SWC2 and the A / D conversion circuit 140.

[0202] During current detection, control circuit 150 acquires the detected current value ICS; during bias detection, it acquires the bias value IOST; and during monitoring, it acquires the monitoring voltage VM based on voltage MONP. Control circuit 150 performs a correction calculation on the detected current value ICS based on the bias value IOST, the monitoring voltage VM, and the correction parameters stored in storage circuit 170, thereby obtaining the corrected current value ILScul. The correction parameters and correction process are described in detail below.

[0203] Figure 19 and Figure 20 An explanatory diagram showing the calibration parameters is provided. These calibration parameters are obtained, for example, during manufacturing inspections. The following describes an example of the calibration parameter acquisition process performed by the inspection device.

[0204] Figure 19 This diagram illustrates the calibration parameters for the detected current value ICS. The testing device short-circuits the two ends of shunt resistor 12 and monitors the detection data ADQ while changing the voltage MONP. The testing device is set to a switching state during current detection, and while changing the voltage MONP, it acquires the detection voltage VQ = VRcs. Additionally, the testing device is set to a switching state during monitoring, and while changing the voltage MONP, it acquires the monitoring voltage VM. Based on the acquired data, the testing device calculates the slope value 'a' and the intercept value 'Vb' of VRcs = a × VM + Vb, and sets them as calibration parameters.

[0205] Figure 20 This is an explanatory diagram of the correction parameters for the bias value IOST. The inspection device is set to the switching state during bias detection, monitors the detection data ADQ, and obtains the data of detection voltage VQ = VRost. The bias value detected by the detection voltage VRost is called the reference bias value. The inspection device sets VRost as the correction parameter.

[0206] The aforementioned correction parameters are written to the storage circuit 170 from an external processing device, for example, during initialization when the power is turned on. Alternatively, the storage circuit 170 may be a non-volatile memory, and the correction parameters may be stored in the non-volatile memory during manufacturing.

[0207] Next, the correction process using the above-mentioned correction parameters will be explained. During current detection, the control circuit 150 acquires the detection voltage VCS representing the detected current value ICS, during bias detection, it acquires the detection voltage VOST representing the bias value IOST, and during monitoring, it acquires the monitoring voltage VM based on the voltage MONP. As shown in the following equation (21), the control circuit 150 uses the correction parameters stored in the storage circuit 170 to calculate the voltage VQcul representing the corrected current value ILScul.

[0208] VQcul=(VCS-VRcs)-(VOST-VRost)

[0209] ={VCS-(a×VM+Vb)}-(VOST-VRost)

[0210] ···(twenty one)

[0211] Furthermore, the third embodiment can also be combined with the second embodiment. That is, if there is a residual error in the detection voltage VQ after correction by the second embodiment, the residual error can also be corrected by the correction process of the third embodiment.

[0212] Figure 21 This is the first timing diagram of the current detection operation in the third embodiment. The control method circuit 150 changes the PWM signal SPWM from low to high, and after a waiting period, performs the operation of detection periods DT1 to DTk from the 1st to the kth. The control circuit 150 performs the operation of the monitoring period MT, performs the operation of detection periods DTk+1 to DTm from the (k+1)th to the mth, and after a waiting period, changes the PWM signal SPWM from high to low. After a waiting period, the control circuit 150 performs the operation of detection periods DTm+1 to DTn from the (m+1)th to the nth, and after a waiting period, changes the PWM signal SPWM from low to high. n is an integer of 3 or more, m is an integer of 2 or more and less than n, and k is an integer of 1 or more and less than m. For example, if m is an even number, k = m / 2. The length of the monitoring period MT is, for example, the same as the length of one detection period, but is not limited thereto.

[0213] Figure 22This is the second timing diagram of the current detection operation in the third embodiment. After the control circuit 150 changes the PWM signal SPWM from low to high, it performs the monitoring period MT operation before the first detection period DT1. Alternatively, the monitoring period MT can be set during the waiting period before the start of the first detection period DT.

[0214] Figure 23 This is the third timing diagram for the current detection operation in the third embodiment. The control method circuit 150 performs the operation of DT1 to DTm during the first to m detection periods, and performs the monitoring period MT. After a waiting period, the PWM signal SPWM is changed from high to low. Alternatively, the monitoring period MT can be set during the waiting period before the PWM signal SPWM changes from high to low.

[0215] Control circuit 150 calculates the voltage VQcul, representing the corrected current value ILScul, according to the following formula (22). VMon is... Figures 21-23 The monitoring voltage obtained by MT during the monitoring period shown is the monitoring voltage during the on-state of the switching element 180. VMoff is the monitoring voltage during the off-state of the switching element 180, but this monitoring voltage VMoff is not measured. Assuming that when the forward voltage of diode DA is Vf, MONP = -Vf, the voltage value of the monitoring voltage VMoff after dividing MONP = -Vf is stored in the storage circuit 170, and this voltage value can be used in the following equation (22).

[0216]

[0217] As shown in equation (23), the control circuit 150 can also calculate the voltage VQcul by taking into account the A / D gain ADG of the A / D conversion circuit 140. The A / D gain is measured during inspection and stored in the storage circuit 170 as a correction parameter. In addition, the slope value a / ADG, the intercept value Vb / ADG, and the reference bias value VRost / ADG after the A / D gain is corrected are stored in the storage circuit 170 as correction parameters.

[0218]

[0219] After the power is turned on, during the initial turn-on period when the switching element 180 is initially turned on, the control circuit 150 uses a predetermined initial value VMonini for VMon in the above formula (22) or (23). At this time, the initial value VMonini is stored as a correction parameter in the storage circuit 170.

[0220] In this embodiment described above, the circuit device 100 includes a current sensing amplifier circuit 120, a level shifting circuit 130, and a processing circuit 115. A switching element 180, a shunt resistor 12, and an inductor 11 are connected in series between the first power node and the second power node. The current sensing amplifier circuit 120 detects the current flowing through the shunt resistor 12. The processing circuit 115 calculates the corrected current value ILScul of the current ILS flowing through the shunt resistor 12 based on the output of the current sensing amplifier circuit 120. The current sensing amplifier circuit 120 includes an operational amplifier OPA, a first resistor RIP, and a second resistor RIN. The first resistor RIP is disposed between the first resistor node NMONP at one end of the shunt resistor 12 and the first input node NIP of the operational amplifier OPA. The second resistor RIN is disposed between the second resistor node NMONN at the other end of the shunt resistor 12 and the second input node NIN of the operational amplifier OPA. Level shifting circuit 130 supplies a first current IP to the first input node NIP and a second current IN to the second input node NIN, thereby shifting the voltage levels of the first input node NIP and the second input node NIN. Processing circuit 115 detects the detected current value ICS based on the output of current sensing amplifier circuit 120. Processing circuit 115 performs a correction calculation on the detected current value ICS based on the monitoring result of the voltage MONP at the first resistor node NMONP, i.e., the monitoring voltage VM, thereby obtaining the corrected current value ILScul.

[0221] According to this embodiment, in the event of a mismatch between the first resistor RIP and the second resistor RIN, or a mismatch between the first current IP and the second current IN, a detection error occurs in the current sensing amplifier circuit 120 due to this mismatch. According to this embodiment, the processing circuit 115 performs a calculation to correct the detected current value ICS, thereby correcting the detection error of the current sensing amplifier 120 caused by at least one mismatch. Therefore, the current sensing amplifier circuit 120 can accurately detect the current flowing through the shunt resistor 12.

[0222] In addition, such as Figure 19 As explained, the detection error may depend on the common-mode voltage. According to this embodiment, the processing circuit 115 corrects the detection current value ICS based on the monitoring voltage VM corresponding to the common-mode voltage, thereby correcting the detection error that depends on the common-mode voltage.

[0223] In this embodiment, the circuit device 100 includes a storage circuit 170 that stores the slope value and intercept value of the detected current value ICS for the monitoring voltage VM. The processing circuit 115 performs a calculation to correct the detected current value ICS based on the monitoring voltage VM, the slope value, and the intercept value.

[0224] According to this embodiment, the slope and intercept values ​​of the detection current value ICS for the monitoring voltage VM are correction parameters representing the detection error dependent on the monitoring voltage VM. The detection current value ICS is corrected based on these correction parameters, thereby correcting the detection error dependent on the monitoring voltage VM.

[0225] In addition, Figure 19 In the example, the slope of the detected current value ICS corresponds to the slope a of the detected voltage VQ = VRcs, and the intercept of the detected current value ICS corresponds to the intercept of the voltage VRcs. The current ILS flowing through the shunt resistor 12 is used as the detected voltage VQ of the current sensing amplifier circuit 120. Therefore, the corrected detected current value ICS is equivalent to the corrected detected voltage VQ.

[0226] In addition, in this embodiment, the processing circuit 115 performs a calculation to correct the detected current value ICS obtained based on the output of the current sensing circuit 120 during the current detection period, based on the monitoring voltage VM obtained during the monitoring period and the bias value IOST obtained based on the output of the current sensing amplifier circuit 120 during the bias detection period, thereby obtaining the corrected current value ILScul.

[0227] According to this embodiment, the detection current value ICS is corrected based on the monitoring voltage VM and the bias value IOST, thereby correcting the detection error that depends on the common-mode voltage and the detection error caused by the bias.

[0228] In this embodiment, the circuit device 100 includes a storage circuit 170 that stores the slope value, intercept value, and reference bias value of the detected current value ICS for the monitoring voltage VM. The processing circuit 115 performs a calculation to correct the detected current value ICS based on the monitoring voltage VM, the slope value, the intercept value, and the reference bias value.

[0229] According to this embodiment, the detection current value ICS is corrected based on the monitoring voltage VM, the slope value, and the intercept value, thereby correcting the detection error that depends on the monitoring voltage VM. Furthermore, the detection current value ICS is corrected based on a reference bias value, thereby correcting the detection error caused by the bias.

[0230] In addition, Figure 20 In the example, the reference bias value corresponds to the detection voltage VQ = VRost. The reference bias value is equivalent to the bias of the detection current value ICS, and the corresponding bias of the detection voltage VQ is VRost.

[0231] In addition, in this embodiment, the detection voltage of the current sensing amplifier circuit 120 obtained as the detection current value ICS is VCS, the slope value is a, the monitoring voltage is VM, the intercept value is Vb, the detection voltage obtained as the bias value is VOST, the voltage corresponding to the reference bias value is VRost, and the voltage corresponding to the corrected current value ILScul is set as VQcul. As explained in the above formula (21), VQcul={VCS-(a×VM+Vb)}-(VOST-VRost).

[0232] According to this embodiment, by performing the above calculations based on the slope value, intercept value, and reference bias value, a voltage VQcul equivalent to the corrected current value ILScul can be calculated. Therefore, the current detection error caused by the aforementioned mismatch can be corrected through this calculation.

[0233] Furthermore, in this embodiment, the circuit device 100 includes a drive circuit 160, which drives the switching element 180 via a PWM signal SPWM based on the corrected current value ILScul. The processing circuit 115 acquires the detected current value ICS during the current detection period and the bias value IOST during the bias detection period during each of the first to m detection periods DT1 to DTm in the first voltage level period of the PWM signal SPWM.

[0234] Furthermore, in this embodiment, the processing circuit 115 acquires the monitoring voltage VM during the monitoring period MT between the k-th detection period DTk and the (k+1)-th detection period DTk+1.

[0235] According to this embodiment, the monitoring voltage VM is obtained between the k-th detection period DTk and the (k+1)-th detection period DTk+1 during the first voltage level period of the PWM signal SPWM.

[0236] In addition, in this embodiment, the processing circuit 115 may also obtain the monitoring voltage VM during the monitoring period MT before the first detection period DT1.

[0237] According to this embodiment, the monitoring voltage VM can also be obtained before the first detection period DT1 during the first voltage level of the PWM signal SPWM.

[0238] Furthermore, in this embodiment, the processing circuit 115 can also obtain the monitoring voltage VM during the monitoring period MT after the m-th detection period DTm.

[0239] According to this embodiment, the monitoring voltage VM can be obtained after the m-th detection period DTm during the first voltage level of the PWM signal SPWM.

[0240] 6. Summary

[0241] The circuit arrangement of this embodiment described above includes a current sensing amplifier circuit and a processing circuit. The current sensing amplifier circuit detects the current flowing through a switching element, a shunt resistor, and a shunt resistor in an inductor connected in series between the first power node and the second power node. The processing circuit calculates a corrected current value for the current flowing through the shunt resistor based on the output of the current sensing amplifier circuit. The current sensing amplifier circuit includes an operational amplifier, a first resistor, a first switch, a second resistor, a second switch, a third resistor, a third switch, a fourth resistor, and a fourth switch. The first resistor is disposed between the first resistor node and the first node at one end of the shunt resistor. The first switch is disposed between the first node and the first input node of the operational amplifier. The second resistor is disposed between the second resistor node and the second node at the other end of the shunt resistor. The second switch is disposed between the second node and the second input node of the operational amplifier. The third resistor is disposed between the constant voltage node and the third node. The third switch is disposed between the third node and the first input node of the operational amplifier. The fourth resistor is disposed between the constant voltage node and the fourth node. The fourth switch is positioned between the fourth node and the second input node of the operational amplifier. During current detection, switches 1 and 2 are on, and switches 3 and 4 are off. The processing circuit obtains the detected current value based on the output of the current sensing amplifier circuit. During bias detection, switches 1 and 2 are off, and switches 3 and 4 are on. The processing circuit obtains the bias value based on the output of the current sensing amplifier circuit. The processing circuit calculates the corrected current value based on the detected current value and the bias value.

[0242] According to this embodiment, during bias detection, switches 3 and 4 are turned on, thereby making the differential input of the current sensing amplifier circuit the same as the short-circuit state. This allows for the measurement of the bias of the current sensing amplifier circuit. Furthermore, compared to resistors 1 and 2, switches 1 through 4 are connected to the input node side of the operational amplifier. Therefore, the voltage at one end or the other end of the shunt resistor, which is near the power supply voltage or a negative voltage, is not directly applied to the four switches. Thus, it is unnecessary to use a process or structure that requires the switches to withstand high or negative voltages.

[0243] Alternatively, in this embodiment, the circuit arrangement may also include a level shifting circuit. The level shifting circuit supplies a first current to the first input node of the operational amplifier and a second current to the second input node of the operational amplifier, thereby shifting the voltage levels of the first and second input nodes.

[0244] The common-mode voltage at the input of the current-sensing amplifier circuit fluctuates significantly due to PWM driving. Without a level-shifting circuit, the input voltage of the operational amplifier also fluctuates significantly if the common-mode voltage changes. According to this embodiment, the level-shifting circuit shifts the voltages of the first and second input nodes, thereby reducing the fluctuation of the operational amplifier's input voltage.

[0245] In addition, in this embodiment, the level shifting circuit variably controls the first current and the second current according to the voltage of the first resistor node, thereby level shifting the voltages of the first input node and the second input node of the operational amplifier according to the level shift amount that varies according to the voltage of the first resistor node.

[0246] According to this embodiment, the input voltage of the operational amplifier is level-shifted according to a level shift amount corresponding to the common-mode voltage. Therefore, the input voltage of the operational amplifier is controlled in accordance with the common-mode voltage, thus reducing its fluctuation.

[0247] In addition, in this embodiment, the level shift is the difference between the reference voltage and the voltage of the first resistor node.

[0248] According to this embodiment, the input voltage level of the operational amplifier can be shifted to approximately a reference voltage. Therefore, even in the event of common-mode voltage fluctuations, the input voltage of the operational amplifier can be maintained at approximately a reference voltage. Since the voltage applied to the first to fourth switches is approximately a reference voltage, the first to fourth switches only need to be manufactured or constructed to withstand approximately a reference voltage.

[0249] Furthermore, in this embodiment, the circuit device includes a drive circuit that drives a switching element via a PWM signal based on the corrected current value. The processing circuit acquires the detected current value during the current detection period and the bias value during the bias detection period during each detection period from the first to the nth detection period within one cycle of the PWM signal. n is an integer of 2 or more.

[0250] The current flowing through the shunt resistor varies via PWM drive. According to this embodiment, by performing multiple current detections within one cycle of the PWM signal, the average current value can be calculated.

[0251] In addition, in this embodiment, the processing circuit calculates the corrected current value in one cycle by averaging the difference between the detection current value and the bias value obtained in each detection period from the first detection period to the nth detection period.

[0252] According to this embodiment, the current value after bias elimination in each detection period is obtained by detecting the difference between the current value and the bias value, and the corrected current value in one cycle is obtained based on the average value of the current value.

[0253] Furthermore, in this embodiment, the first detection period to the nth detection period includes the first detection period to the mth detection period within the first voltage level period of the PWM signal and the (m+1)th detection period to the nth detection period within the second voltage level period of the PWM signal. m is an integer greater than or equal to 1 and less than n. The processing circuit calculates the corrected current value in the first voltage level period by averaging the difference between the detected current value and the bias value obtained in each of the first to mth detection periods as the corrected current value. The processing circuit calculates the corrected current value in the second voltage level period by averaging the difference between the detected current value and the bias value obtained in each of the (m+1)th to nth detection periods as the corrected current value. The processing circuit calculates the corrected current value based on the corrected current value in the first voltage level period and the corrected current value in the second voltage level period.

[0254] The current flowing through the shunt resistor increases during the on-time of the switching element and decreases during the off-time. According to this embodiment, a detection period is set for both the on-time and off-time of the switching element, so the corrected current value in one cycle can be accurately determined.

[0255] In this embodiment, a switching element is connected between the first power supply node and the first resistor node, a diode is connected between the first resistor node and the second power supply node (which serves as a ground node), and an inductor is connected between the second resistor node and the ground node. The current sensing amplifier circuit detects the current value by detecting the voltage difference between the first and second resistor nodes.

[0256] During the on-state of the switching element, the common-mode voltage is near the power supply voltage of the first power node; during the off-state of the switching element, the common-mode voltage becomes a negative voltage. The negative voltage is the voltage resulting from the voltage below the forward voltage of the diode after the voltage to ground has decreased. According to this embodiment, as described above, these voltages are not directly input to the first to fourth switches.

[0257] Furthermore, the solenoid control device of this embodiment includes the above-described circuit device, switching element, shunt resistor, and solenoid as inductor, and controls the solenoid based on the corrected current value.

[0258] Furthermore, while this embodiment has been described in detail above, those skilled in the art will readily understand that various modifications can be made without substantially departing from the novel aspects and effects of the invention. Therefore, all such modifications are included within the scope of the invention. For example, a term described at least once with a broader or synonymous term may be replaced with a different term anywhere in the specification or drawings. Additionally, all combinations of this embodiment and its modifications are also included within the scope of the invention. Furthermore, the structure and operation of current sensing amplifier circuits, level shifting circuits, current detection circuits, inductors, circuit devices, and solenoid control devices are not limited to those described in this embodiment, and various modifications can be implemented.

Claims

1. A circuit device, characterized in that, It has the following characteristics: A current sensing amplifier circuit that detects the current flowing through a switching element, a shunt resistor, and the shunt resistor in an inductor connected in series between a first power node and a second power node. as well as The processing circuit calculates the corrected current value of the current flowing through the shunt resistor based on the output of the current sensing amplifier circuit. The current sensing amplifier circuit includes: Operational amplifier; The first resistor is disposed between the first resistor node and the first node at one end of the shunt resistor; A first switch is disposed between the first node and the first input node of the operational amplifier; The second resistor is disposed between the second resistor node and the second node at the other end of the shunt resistor; A second switch is disposed between the second node and the second input node of the operational amplifier; The third resistor is located between the constant voltage node and the third node; A third switch is disposed between the third node and the first input node of the operational amplifier; A fourth resistor is disposed between the constant voltage node and the fourth node; as well as A fourth switch is disposed between the fourth node and the second input node of the operational amplifier. During current detection, the first and second switches are turned on, while the third and fourth switches are turned off. The processing circuit obtains the detected current value based on the output of the current sensing amplification circuit. During bias detection, the first and second switches are open, while the third and fourth switches are closed. The processing circuit obtains the bias value based on the output of the current sensing amplifier circuit. The processing circuit calculates the corrected current value based on the detected current value and the bias value.

2. The circuit device according to claim 1, characterized in that, The circuit device includes a level shifting circuit that supplies a first current to the first input node of the operational amplifier and a second current to the second input node of the operational amplifier, thereby causing a level shift of the voltages at the first and second input nodes.

3. The circuit device according to claim 2, characterized in that, The level shifting circuit variably controls the first current and the second current according to the voltage of the first resistor node, thereby level shifting the voltages of the first input node and the second input node of the operational amplifier according to a level shift amount that varies according to the voltage of the first resistor node.

4. The circuit device according to claim 3, characterized in that, The level shift is the difference between the reference voltage and the voltage of the first resistor node.

5. The circuit device according to any one of claims 1 to 4, characterized in that, The circuit arrangement includes a drive circuit that drives the switching element via a PWM signal based on the corrected current value. The processing circuit obtains the detected current value during the current detection period and the bias value during the bias detection period during each detection period from the first detection period to the nth detection period in one cycle of the PWM signal, where n is an integer greater than or equal to 2.

6. The circuit device according to claim 5, characterized in that, The processing circuit calculates the corrected current value in one cycle by averaging the difference between the detection current value and the bias value obtained in each detection period from the first detection period to the nth detection period.

7. The circuit device according to claim 5, characterized in that, The first detection period to the nth detection period includes the first detection period to the mth detection period within the first voltage level period of the PWM signal and the (m+1)th detection period to the nth detection period within the second voltage level period of the PWM signal, where m is an integer greater than or equal to 1 and less than n. The processing circuit calculates the corrected current value during the first voltage level period by averaging the differences between the detected current value and the bias value obtained during each of the first detection period to the m-th detection period. The processing circuit calculates the corrected current value during the second voltage level period by averaging the differences between the detected current value and the bias value obtained during each of the (m+1)th detection period to the nth detection period. The processing circuit calculates the corrected current value based on the corrected current value during the first voltage level period and the corrected current value during the second voltage level period.

8. The circuit device according to any one of claims 1 to 4, characterized in that, The switching element is connected between the first power supply node and the first resistor node. A diode is connected between the first resistor node and the second power supply node, which serves as a ground node. The inductor is connected between the second resistor node and the ground node. The current sensing amplifier circuit detects the current value by detecting the voltage difference between the first resistor node and the second resistor node.

9. A solenoid control device, characterized in that, It has the following characteristics: The circuit device according to any one of claims 1 to 8; The switching element; The shunt resistor; and The solenoid of the inductor The solenoid is controlled based on the corrected current value.

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